Lattice Semiconductor Corporation ISPLSI2128VL-135LQ160, ISPLSI2128VL-135LB208, ISPLSI2128VL-135LB100, ISPLSI2128VL-100LT176, ISPLSI2128VL-100LT100 Datasheet

ispLSI® 2128VL

Global Routing Pool (GRP)

Output Routing Pool (ORP) Output Routing Pool (ORP)

Output Routing Pool (ORP) Output Routing Pool (ORP)

Output Routing Pool (ORP) Output Routing Pool (ORP)

CLK 0

Output Routing Pool (ORP) Output Routing Pool (ORP)

CLK 1

CLK 2

Logic
Array

GLB

DQ

DQ

DQ

DQ

0139A/2128VL

C7

C6

C5

C4

C3

C2

C1

C0

D3

D2

D1

D0

D7

D6

D5

D4

B4

B5

B6

B7

B0

B1

B2

B3

A0

A1

A2

A3

A4

A5

A6

A7

*128 I/O version shown

2.5V In-System Programmable

SuperFAST™ High Density PLD

• SuperFAST HIGH DENSITY IN-SYSTEM

• 2.5V LOW VOLTAGE 2128 ARCHITECTURE

• HIGH PERFORMANCE E

• IN-SYSTEM PROGRAMMABLE

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. September 2000
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

2128vL_02 1

Features

PROGRAMMABLE LOGIC
— 6000 PLD Gates

— 128 and 64 I/O Pin Versions, Eight Dedicated Inputs
— 128 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible

with ispLSI 2128V and 2128VE Devices

— Interfaces with Standard 3.3V Devices (Inputs and

I/Os are 3.3V Tolerant)
— 125 mA Typical Active Current

2

CMOS® TECHNOLOGY

—

fmax = 150 MHz Maximum Operating Frequency

tpd = 6.0 ns Propagation Delay

—
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power

— 2.5V In-System Programmability (ISP™) Using

Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of Wired-

OR Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global

Interconnectivity

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms

Functional Block Diagram*

Description

The ispLSI 2128VL is a High Density Programmable
Logic Device available in 128 and 64 I/O-pin versions.
The device contains 128 Registers, eight Dedicated
Input pins, three Dedicated Clock Input pins, two dedi­cated Global OE input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 2128VL fea­tures in-system programmability through the Boundary
Scan Test Access Port (TAP) and is 100% IEEE 1149.1
Boundary Scan Testable. The ispLSI 2128VL offers non­volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.

The basic unit of logic on the ispLSI 2128VL device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 2128VL device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.

Specifications ispLSI 2128VL

Functional Block Diagram

Figure 1. ispLSI 2128VL Functional Block Diagram (128-I/O and 64-I/O Versions)

I/O 127

I/O 126

I/O 125

I/O 124

I/O 123

I/O 122

I/O 121

I/O 120

I/O 119

I/O 118

I/O 117

I/O 116

I/O 115

I/O 114

I/O 113

I/O 112

I/O 111

I/O 110

I/O 109

I/O 108

I/O 107

I/O 106

I/O 105

I/O 104

I/O 103

I/O 102

I/O 101

I/O 100

I/O 99

I/O 98

I/O 97

I/O 96

IN 7

RESET

GOE 0
GOE 1

I/O 10
I/O 11

I/O 12
I/O 13
I/O 14
I/O 15

I/O 16
I/O 17
I/O 18
I/O 19

I/O 20
I/O 21
I/O 22
I/O 23

I/O 24
I/O 25
I/O 26
I/O 27

I/O 28
I/O 29
I/O 30
I/O 31

TDI/IN 0

TMS/IN 1

BSCAN

IN 6

I/O 42

I/O 43

Input Bus

D5

D4

Global

Routing

Pool

(GRP)

B3

Input Bus

I/O 44

I/O 45

I/O 46

I/O 47

I/O 48

D2

D3

B5

B4

I/O 49

I/O 50

I/O 51

I/O 52

I/O 53

I/O 54

I/O 55

I/O 56

I/O 57

D0

D1

C7

C6

C5

C4

Input Bus

C3

C2

C1

Output Routing Pool (ORP) Output Routing Pool (ORP)

C0

B7

B6

CLK 0

CLK 1

CLK 2

0139B/2128VL

I/O 60

I/O 61

I/O 62

I/O 63

Y0Y1Y2

I/O 58

I/O 59

Megablock

G

e

n

e

r

c

L

i

o

g

c

i

)

s

(

s

G

L

k

B

o

l

c

B

I/O 0
I/O 1
I/O 2
I/O 3

I/O 4
I/O 5
I/O 6
I/O 7

I/O 8
I/O 9

A0

A1

A2

A3

Input Bus

A4

A5

A6

Output Routing Pool (ORP) Output Routing Pool (ORP)

A7

TDO/IN 2

Output Routing Pool (ORP) Output Routing Pool (ORP)

D7

D6

B0

B1

B2

Output Routing Pool (ORP) Output Routing Pool (ORP)

I/O 32

I/O 33

I/O 34

I/O 35

I/O 36

I/O 37

I/O 38

I/O 39

I/O 40

TCK/IN 3

I/O 41

IN 5
IN 4

I/O 95
I/O 94
I/O 93
I/O 92

I/O 91
I/O 90
I/O 89
I/O 88

I/O 87
I/O 86
I/O 85
I/O 84

I/O 83
I/O 82
I/O 81
I/O 80

I/O 79
I/O 78
I/O 77
I/O 76

I/O 75
I/O 74
I/O 73
I/O 72

I/O 71
I/O 70
I/O 69
I/O 68

I/O 67
I/O 66
I/O 65
I/O 64

RESET

GOE 0
GOE 1

I/O 10
I/O 11

I/O 12
I/O 13
I/O 14
I/O 15

TDI/IN 0

TMS/IN 1

BSCAN

Megablock

G

e

n

e

r

i

k

o

s

l

c

B

I/O 0
I/O 1
I/O 2
I/O 3

I/O 4
I/O 5
I/O 6
I/O 7

Input Bus

I/O 8
I/O 9

Output Routing Pool (ORP)

I/O 63

I/O 62

I/O 61

I/O 60

I/O 59

I/O 58

c

L

o

g

c

i

D7

D6

B1

D5

B2

Output Routing Pool (ORP)

I/O 20

I/O 21

I/O 22

I/O 23

)

(

s

G

L

B

A0

A1

A2

A3

A4

A5

A6

A7

B0

I/O 16

I/O 17

I/O 18

I/O 19

TCK/IN 3

TDO/IN 2

I/O 57

I/O 56

Input Bus

Output Routing Pool (ORP)

D4

D3

Global

Routing

Pool

(GRP)

B3

B4

Input Bus

I/O 55

I/O 54

I/O 53

I/O 52

D2

D1

B5

B6

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

*Not available on 84-PLCC Device

I/O 51

I/O 50

I/O 49

I/O 48

IN 7*

IN 6*

Input Bus

Output Routing Pool (ORP)

CLK 1

CLK 2

0139B/2128VL.64IO

IN 5*
IN 4*

I/O 47
I/O 46
I/O 45
I/O 44

I/O 43
I/O 42
I/O 41
I/O 40

I/O 39
I/O 38
I/O 37
I/O 36

I/O 35
I/O 34
I/O 33
I/O 32

D0

C7

C6

C5

C4

C3

C2

C1

C0

B7

CLK 0

Y0Y1Y2

I/O 30

I/O 31

The 128-I/O 2128VL contains 128 I/O cells, while the 64­I/O version contains 64 I/O cells. Each I/O cell is directly
connected to an I/O pin and can be individually pro­grammed to be a combinatorial input, output or
bi-directional I/O pin with 3-state control, and the output
drivers can source 4mA or sink 8mA. Each output can be
programmed independently for fast or slow output slew
rate to minimize overall output switching noise. Device
pins can be safely driven to 3.3V signal levels to support
mixed-voltage systems.

Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and
two or one ORPs are connected together to make a
Megablock (see Figure 1). The outputs of the eight GLBs
are connected to a set of 32 or 16 universal I/O cells by
the two or one ORPs. Each ispLSI 2128VL device con­tains four Megablocks.

The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.

Clocks in the ispLSI 2128VL device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a

GLB basis. The asynchronous or Product Term clock can
be generated in any GLB for its own clock.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the
outputs of the ispLSI 2128VL are individually program­mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro­grammable fuse. The default configuration is a totem-pole
configuration. The open-drain/totem-pole option is se­lectable through the ispDesignEXPERT software tools.

2

Specifications ispLSI 2128VL

Absolute Maximum Ratings

1

Supply Voltage Vcc................................ -0.5 to +4.05V

Input Voltage Applied............................. -0.5 to +4.05V

Off-State Output Voltage Applied .......... -0.5 to +4.05V

Storage Temperature................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (TJ) with Power Applied ... 150°C

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Condition

V
V

V

CC

IL
IH

SYMBOL

Supply Voltage

Input Low Voltage
Input High Voltage

PARAMETER

Commercial
Industrial

TA = 0°C to + 70°C

= -40°C to + 85°C

T

A

MIN. MAX. UNITS

2.3

2.3

-0.3

1.7

2.7

2.7

0.7

3.6

Table 2-0005/2128VL

V
V
V
V

Capacitance (TA=25°C, f=1.0 MHz)

SYMBOL

C

1

C

2

C

3

I/O Capacitance
Clock and Global Output Enable Capacitance

PARAMETER

Erase Reprogram Specifications

PARAMETER MINIMUM MAXIMUM UNITS

Erase/Reprogram Cycles

UNITSTYPICAL TEST CONDITIONS

8Dedicated Input Capacitance
6

10

10,000 – Cycles

pf
pf
pf V = 2.5V, V = 0.0V

V = 2.5V, V = 0.0V

CC

V = 2.5V, V = 0.0V

CC I/O

CC Y

IN

Table 2-0006/2128VL

Table 2-0008/2128VL

3

Switching Test Conditions

Specifications ispLSI 2128VL

Input Pulse Levels
Input Rise and Fall Time

Input Timing Reference Levels
Output Timing Reference Levels
Output Load

3-state levels are measured 0.15V from
steady-state active level.

GND to V

≤ 1.5ns 10% to 90%

See Figure 2

CC

V

/2

CC

/2

V

CC

Table 2 - 0003/2128VL

Figure 2. Test Load

Device

Output

V

CC

R

1

Test

Point

R

2

C

*

L

Output Load Conditions (see Figure 2)

TEST CONDITION R1 R2 CL

A 250Ω 218Ω 35pF

Active High

B

Active Low
Active High to Z

at V -0.15V

C

Active Low to Z
at V +0.15V

OH

OL

∞

250Ω

∞

250Ω

218Ω 35pF

∞

35pF

218Ω 5pF

∞

Table 2-0004/2128VL

5pF

*

CL includes Test Fixture and Probe Capacitance.

0213A/2128VL

DC Electrical Characteristics

Over Recommended Operating Conditions

—

——VIOH = -100µA
—

—
—
—
—
—

125

3

0.2

—

-10
10

-150

-150

-100

Table 2-0007/2128VL

SYMBOL

V

OL

V

OH

5

I

IL

I

IH

I

IL-isp

I

IL-PU

1

I

OS

2, 4

I

CC

Output Low Voltage

Output High Voltage

Input or I/O Low Leakage Current
Input or I/O High Leakage Current
BSCAN Input Pull-Up Current
I/O Active Pull-Up Current
Output Short Circuit Current

Operating Power Supply Current

PARAMETER

IOL = 100µA
I

OL

I

OH
OH

0V ≤ V ≤ V (Max.)

V

IH

0V ≤ V ≤ V
0V ≤ V ≤ V
V = 2.5V, V = 0.5V

CC OUT

V = 0.0V, V = 2.5V

IL IH

f = 1 MHz

CLK

1. One output at a time for a maximum duration of one second. V

CONDITION MIN. TYP. MAX. UNITS

—

= 8mA

= -1mA

= -4mA

IN IL

(min) ≤ VIN ≤ 3.6V

IL

IN
IN IL

——0.4 V

VCC - 0.2

2.0

1.8 ——VI

—
—
—
—
—

—

= 0.5V was selected to avoid test

OUT

problems by tester ground degradation. Characterized but not 100% tested.

2. Measured using eight 16-bit counters.

3. Typical values are at V

4. Maximum I

varies widely with specific device configuration and operating frequency. Refer to Power Consumption

CC

= 2.5V and TA = 25°C.

CC

section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I

CC

.

5. With no pull-up resistors.

V

V

µA
µA
µA
µA

mA
mA—

4

External Timing Parameters

Over Recommended Operating Conditions

Specifications ispLSI 2128VL

3

TEST

COND.

tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl

1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.

2. Standard 16-bit counter using GRP feedback.

3. Reference Switching Test Conditions section.

A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass — 7.5 — 10.0 ns
A 2 Data Propagation Delay —— ns
A 3 Clock Frequency with Internal Feedback 135 — 100 — MHz

— 4 Clock Frequency with External Feedback ——MHz
— 5 Clock Frequency, Max. Toggle ——MHz
— 6 GLB Reg. Setup Time before Clock, 4 PT Bypass ——ns
A 7 GLB Reg. Clock to Output Delay, ORP Bypass —— ns
— 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 — ns
— 9 GLB Reg. Setup Time before Clock 6.0 — ns
A 10 GLB Reg. Clock to Output Delay —— ns
— 11 GLB Reg. Hold Time after Clock 0.0 — ns
A 12 Ext. Reset Pin to Output Delay, ORP Bypass —— ns
— 13 Ext. Reset Pulse Duration 5.5 — ns

B 14 Input to Output Enable —— ns
C 15 Input to Output Disable —— ns
B 16 Global OE Output Enable —— ns
C 17 Global OE Output Disable —— ns

— 18 External Synchronous Clock Pulse Duration, High 3.5 ——ns
— 19 External Synchronous Clock Pulse Duration, Low 3.5 ——ns

DESCRIPTION#PARAMETER

1

2

1

( )

tsu2 + tco1

-150

MIN. MAX.

— 6.0

8.5

—

150 —
111

—

166

—

4.0

—

4.0

—

—

0.0

—

5.0

5.0

—

—

0.0

6.0

—

—

5.0

10.0

—

10.0

—

6.0

—

6.0

—

3.0 —

3.0 —

MIN.

95

143

5.0

-135

10.0

4.5

—
—

5.5

—

8.0

—

12.0

12.0

7.0

7.0

-100

MIN.MAX. MAX.

13.0

77

100

6.5

5.0

0.0

8.0

6.0

0.0

13.5

6.5

15.0

15.0

9.0

9.0

5.0

5.0

Table 2-0030/2128VL

UNITS

5

Specifications ispLSI 2128VL

Internal Timing Parameters

1

Over Recommended Operating Conditions

PARAMETER

Inputs

t

io

t

din

GRP

t

grp

GLB

t

4ptbpc

t

4ptbpr

t

1ptxor

t

20ptxor

t

xoradj

t

gbp

t

gsu

t

gh

t

gco

t

gro

t

ptre

t

ptoe

t

ptck

ORP

t

orp

t

orpbp

Outputs

t

ob

t

sl

t

oen

t

odis

t

goe

Clocks

t

gy0

t

gy1/2

Global Reset

t

gr

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

2

20 Input Buffer Delay — ns
21 Dedicated Input Delay — ns

22 GRP Delay — ns

23 4 Product Term Bypass Path Delay (Combinatorial) — ns
24 4 Product Term Bypass Path Delay (Registered) — ns
25 1 Product Term/XOR Path Delay — ns
26 20 Product Term/XOR Path Delay — ns
27 XOR Adjacent Path Delay — ns
28 GLB Register Bypass Delay — ns
29 GLB Register Setup Time before Clock 1.7 ns
30 GLB Register Hold Time after Clock 4.8 ns
31 GLB Register Clock to Output Delay — ns
32 GLB Register Reset to Output Delay — ns
33 GLB Product Term Reset to Register Delay — ns
34 GLB Product Term Output Enable to I/O Cell Delay — ns
35 GLB Product Term Clock Delay 2.8 ns

36 ORP Delay — ns
37 ORP Bypass Delay — ns

38 Output Buffer Delay — ns
39 Output Slew Limited Delay Adder — ns
40 I/O Cell OE to Output Enabled — ns
41 I/O Cell OE to Output Disabled — ns
42 Global Output Enable — ns

43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 2.6 ns
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 2.8 ns

45 Global Reset to GLB —

DESCRIPTION#

3

-135-150

MIN.

1.0

—

0.4

—

2.2

—

1.5

—

1.2

—

1.1

—

3.2

—

2.5

—

3.2

—

3.0

—

4.2

—

4.0

—

4.2

—

4.0

—

4.2

—

4.0

—

0.5

—

0.0

—

—
—

—
—

—
—

—
—
—
—
—

—

—
—

0.3

1.1

6.6

5.8

4.5

1.5

0.5

1.6

2.0

4.0

4.0

3.0

2.1

2.3

4.8

1.7

—

1.2

3.3

—

2.8

0.3

—

0.6

—

4.9

—

5.0

—

2.1

4.2

1.2

1.4

—

0.4

—

1.6

—

2.0

—

3.5

—

3.5

—

2.5

—

2.1

1.7

1.7

2.3

1.9

1.9

3.4

— ns

-100

MIN.MAX.MIN. MAX. MAX.

0.9

2.7

1.8

5.2

4.7

6.2

6.2

6.2

1.0

—
—

0.3

4.3

8.9

7.4

4.8

1.5

0.5

1.6

2.0

4.9

4.9

4.1

2.6

2.8

7.1

Table 2-0036/2128VL

UNITS

6