Lattice Semiconductor Corporation ISPLSI2128E-180LT176, ISPLSI2128E-135LT176, ISPLSI2128E-100LT176 Datasheet

ispLSI® 2128E

Global Routing Pool (GRP)

Output Routing Pool (ORP) Output Routing Pool (ORP)

Output Routing Pool (ORP) Output Routing Pool (ORP)

Output Routing Pool (ORP) Output Routing Pool (ORP)

CLK 0

Output Routing Pool (ORP) Output Routing Pool (ORP)

CLK 1

CLK 2

Logic
Array

GLB

DQ

DQ

DQ

DQ

0139(9A)/2128

C7

C6

C5

C4

C3

C2

C1

C0

D3

D2

D1

D0

D7

D6

D5

D4

B4

B5

B6

B7

B0

B1

B2

B3

A0

A1

A2

A3

A4

A5

A6

A7

In-System Programmable

SuperFAST™ High Density PLD

Features

• SUPERFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC

— 6000 PLD Gates
— 128 I/O Pins, Eight Dedicated Inputs
— 128 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional/JEDEC Upward Compatible with

ispLSI 2128 Devices

• HIGH PERFORMANCE E
—

fmax = 180 MHz Maximum Operating Frequency
tpd = 5.0 ns Propagation Delay

—
— TTL Compatible Inputs and Outputs
— 5V Programmable Logic Core
— ispJTAG™ In-System Programmable via IEEE 1149.1

(JTAG) Test Access Port

— User-Selectable 3.3V or 5V I/O Supports Mixed-

Voltage Systems
— PCI Compatible Outputs
— Open-Drain Output Option
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Unused Product Term Shutdown Saves Power

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to

Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM­PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

2128e_02 1

2

CMOS® TECHNOLOGY

Functional Block Diagram

Description

The ispLSI 2128E is a High Density Programmable Logic
Device. The device contains 128 Registers, 128 Univer­sal I/O pins, eight Dedicated Input pins, three Dedicated
Clock Input pins, two dedicated Global OE input pins and
a Global Routing Pool (GRP). The GRP provides com­plete interconnectivity between all of these elements.
The ispLSI 2128E features 5V in-system programmabil­ity and in-system diagnostic capabilities. The ispLSI
2128E offers non-volatile reprogrammability of all logic,
as well as the interconnect to provide truly reconfigurable
systems.

The basic unit of logic on the ispLSI 2128E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 2128E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or
registered.Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any GLB on the device.

The device also has 128 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be

November 1998

Functional Block Diagram

Figure 1. ispLSI 2128E Functional Block Diagram

I/O 127

I/O 126

I/O 125

I/O 124

I/O 123

I/O 122

I/O 121

RESET

GOE 0
GOE 1

I/O 10
I/O 11

I/O 12
I/O 13
I/O 14
I/O 15

I/O 16
I/O 17
I/O 18
I/O 19

I/O 20
I/O 21
I/O 22
I/O 23

I/O 24
I/O 25
I/O 26
I/O 27

I/O 28
I/O 29
I/O 30
I/O 31

TCK/ IN 0
TMS/IN 1

BSCAN

Megablock

G

e

n

e

r

c

i

L

o

g

c

i

(

G

o

l

L

c

B

s

k

I/O 0
I/O 1
I/O 2
I/O 3

I/O 4
I/O 5
I/O 6
I/O 7

I/O 8
I/O 9

Input Bus

Output Routing Pool (ORP) Output Routing Pool (ORP)

D7

s

B

)

A0

A1

A2

A3

A4

A5

A6

A7

B0

Output Routing Pool (ORP) Output Routing Pool (ORP)

IN 2

IN 3

I/O 32

I/O 33

I/O 34

I/O 35

I/O 120

Output Routing Pool (ORP) Output Routing Pool (ORP)

D6

B1

B2

I/O 36

I/O 37

I/O 38

I/O 39

I/O 40

I/O 41

I/O 42

I/O 119

D5

I/O 43

I/O 118

I/O 44

I/O 117

B3

I/O 45

I/O 116

Input Bus

I/O 46

I/O 115

I/O 114

I/O 113

Input Bus

D4

Global

Routing

Pool

(GRP)

B4

I/O 47

I/O 48

I/O 49

Specifications ispLSI 2128E

I/O 112

I/O 111

I/O 110

I/O 109

I/O 108

I/O 107

I/O 106

I/O 105

I/O 104

I/O 103

I/O 102

I/O 101

I/O 100

I/O 99

I/O 98

I/O 97

I/O 96

TDI/IN 7

TDO/IN 6

IN 5
IN 4

I/O 95
I/O 94
I/O 93
I/O 92

I/O 91
I/O 90
I/O 89
I/O 88

I/O 87
I/O 86
I/O 85
I/O 84

I/O 83
I/O 82
I/O 81
I/O 80

I/O 79

Input Bus

I/O 78
I/O 77
I/O 76

I/O 75
I/O 74
I/O 73
I/O 72

I/O 71
I/O 70
I/O 69
I/O 68

Output Routing Pool (ORP) Output Routing Pool (ORP)

I/O 67
I/O 66
I/O 65
I/O 64

0139/2128E

I/O 50

I/O 51

I/O 59

D1

I/O 60

B7

I/O 61

I/O 62

I/O 63

D0

C7

C6

C5

C4

C3

C2

C1

C0

CLK 0

CLK 1

CLK 2

Y0Y1Y2

D2

D3

B5

B6

I/O 52

I/O 53

I/O 54

I/O 55

I/O 56

I/O 57

I/O 58

individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise. By
connecting the VCCIO pins to a common 5V or 3.3V
power supply, I/O output levels can be matched to 5V or

3.3V compatible voltages. When connected to a 5V

supply, the I/O pins provide PCI-compatible output drive.
Eight GLBs, 32 I/O cells, two dedicated inputs and two

ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2128E device contains four Megablocks.

The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.

Clocks in the ispLSI 2128E device are selected using the
dedicated clock pins. Three dedicated clock pins (Y0, Y1,
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the
outputs of the ispLSI 2128E are individually program­mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro­grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.

2

Specifications ispLSI 2128E

Absolute Maximum Ratings

1

Supply Voltage Vcc.................................. -0.5 to +7.0V

Input Voltage Applied........................-2.5 to VCC +1.0V

Off-State Output Voltage Applied .....-2.5 to VCC +1.0V

Storage Temperature................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (TJ) with Power Applied ... 150°C

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Condition

V
V

V
V

CC
CCIO

IL
IH

SYMBOL

PARAMETER

Supply Voltage: Logic Core, Input Buffers
Supply Voltage: Output Drivers

Input Low Voltage
Input High Voltage

5V

3.3V

TA = 0°C to +70°C

MIN. MAX. UNITS

4.75

4.75 5.25 V

3.0 3.6 V
0

2.0

5.25

0.8

V

cc

+1

V

V
V

Table 2-0005/2128E

Capacitance (TA=25°C, f=1.0 MHz)

SYMBOL

C

1

C

2

C

3

Dedicated Input Capacitance
I/O Capacitance
Clock Capacitance

PARAMETER

Erase/Reprogram Specification

PARAMETER MINIMUM MAXIMUM UNITS

Erase/Reprogram Cycles

TYP

8
8

10

10,000 – Cycles

UNITS TEST CONDITIONS

pf
pf
pf V = 5.0V, V = 2.0V

V = 5.0V, V = 2.0V

CC

V = 5.0V, V = 2.0V

CC I/O

CC Y

IN

Table 2-0006/2128E

Table 2-0008/2128E

3

Switching Test Conditions

+ 5V

R

1

R

2

C

L

*

Device
Output

Test

Point

*

CL includes Test Fixture and Probe Capacitance.

0213A

Specifications ispLSI 2128E

Input Pulse Levels
Input Rise and Fall Time 10% to 90%

Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.5V from

steady-state active level.

GND to 3.0V

1.5 ns

1.5V

1.5V

See Figure 2

Table 2-0003/2128E

Figure 2. Test Load

Output Load Conditions (see Figure 2)

TEST CONDITION R1 R2 CL

A 470Ω 390Ω 35pF

Active High

B

Active Low
Active High to Z

at V -0.5V

C

Active Low to Z
at V +0.5V

OH

OL

∞ 390Ω 35pF

470Ω 390Ω 35pF

∞ 390Ω 5pF

470Ω 390Ω 5pF

Table 2 - 0004A/2000

DC Electrical Characteristics

Over Recommended Operating Conditions

SYMBOL

V

OL

V

OH

I

IL

I

IH

I

IL-PU

I

OS

I

CC

Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current

Input or I/O High Leakage Current

I/O Active Pull-Up Current

1

Output Short Circuit Current V

3,4

Operating Power Supply Current

1. One output at a time for a maximum duration of one second. V

PARAMETER

I

= 8 mA

OL

= -4 mA

I

OH

0V ≤ V
(V
V
0V ≤ V

V
f

TOGGLE

≤ VIL (Max.)

IN

- 0.2)V ≤ VIN ≤ V

CCIO

≤ V

CCIO

CCIO

= 0.0V, VIH = 3.0V

IL

≤ 5.25V

IN

≤ 2.0V

IN

= 5.0V or 3.3V, V

= 1 MHz

CONDITION MIN. TYP.

–

2.4

–

CCIO

–
–

-10

= 0.5V ––-240 mA

OUT

– 165 mA–

= 0.5V was selected to avoid test

OUT

problems by tester ground degradation. Characterized but not 100% tested.

2. Meaured using eight 16-bit counters.

3. Typical values are at V

= 5V and TA = 25°C.

CC

4. Unused inputs held at 0.0V.

5. Maximum I

varies widely with specific device configuration and operating frequency. Refer to the

CC

Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor
Data Book or CD-ROM to estimate maximum I

CC

.

3

MAX. UNITS

–
–
–
–
–

–

0.4

–

-10
10

10

-250

Table 2-0007/2128E

V
V

µA
µA

µA
µA

4