Lattice Semiconductor Corporation ISPLSI2096VE-250LT128, ISPLSI2096VE-200LT128, ISPLSI2096VE-135LT128I, ISPLSI2096VE-135LT128, ISPLSI2096VE-100LT128 Datasheet

ispLSI® 2096VE

Global Routing Pool

(GRP)

Output Routing Pool (ORP)

Output Routing Pool (ORP)

0919/2096VE

C

7

C

4

C

5

C

6

A

4

A

7

A

6

A

5

GLB

Logic
Array

DQ

DQ

DQ

DQ

Output Routing Pool (ORP)

Output Routing Pool (ORP)

C

3

C

0

C

1

C

2

B

0

B

3

B

2

B

1

Output Routing Pool (ORP)

Output Routing Pool (ORP)

B

7

B

6

B

4

B

5

A

0

A

1

A

3

A

2

3.3V In-System Programmable

SuperFAST™ High Density PLD

Features

• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC
— 4000 PLD Gates
— 96 I/O Pins, Six Dedicated Inputs
— 96 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State

— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible

— Pinout Compatible with ispLSI 2192VE

• 3.3V LOW VOLTAGE 2096 ARCHITECTURE
— Interfaces with Standard 5V TTL Devices

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
—
—
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP™) Using

— Open-Drain Output Option for Flexible Bus Interface

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Prototyping

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global

• ispDesignEXPERT™ – LOGIC COMPILER AND COM­PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore

— PC and UNIX Platforms

*Advanced Information

Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. September 2000
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

2096ve_05 1

Machines, Address Decoders, etc.

with ispLSI 2096V Devices

fmax = 250MHz* Maximum Operating Frequency
tpd = 4.0ns* Propagation Delay

Boundary Scan Test Access Port (TAP)

Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic

Market and Improved Product Quality

Interconnectivity

Tools, Timing Simulator and ispANALYZER™

Functional Block Diagram

Description

The ispLSI 2096VE is a High Density Programmable
Logic Device containing 96 Registers, six Dedicated
Input pins, three Dedicated Clock Input pins, two dedi­cated Global OE input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 2096VE
features in-system programmability through the Bound­ary Scan Test Access Port (TAP) and is 100% IEEE

1149.1 Boundary Scan Testable. The ispLSI 2096VE
offers non-volatile reprogrammability of the logic, as well
as the interconnect to provide truly reconfigurable sys­tems.

The basic unit of logic on the ispLSI 2096VE device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. C7 (see Figure 1). There are a total of 24 GLBs in the
ispLSI 2096VE device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.

The devices also have 96 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can

Functional Block Diagram

Figure 1. ispLSI 2096VE Functional Block Diagram

I/O 95

I/O 94

I/O 93

GOE 0

GOE 1

I/O 92

I/O 91

I/O 90

I/O 89

I/O 88

I/O 87

I/O 86

I/O 85

I/O 84

I/O 83

I/O 82

Specifications ispLSI 2096VE

I/O 81

I/O 80

I/O 79

I/O 78

I/O 77

I/O 76

I/O 75

I/O 74

I/O 73

I/O 72

I/O 71

I/O 70

I/O 69

I/O 68

I/O 67

I/O 66

I/O 65

I/O 64

IN 5

IN 4

Input Bus

Output Routing Pool (ORP)

C

7

C

6

Input Bus

I/O 22

I/O 23

A

I/O 24

6

I/O 25

5

A

Output Routing Pool (ORP)

I/O 18

I/O 19

I/O 20

I/O 21

I/O 26

I/O 27

C

I/O 28

5

7

A

I/O 29

I/O 30

I/O 31

C

4

Routing

I/O 0
I/O 1
I/O 2
I/O 3

I/O 4
I/O 5
I/O 6
I/O 7

I/O 8

I/O 9
I/O 10
I/O 11

I/O 12
I/O 13
I/O 14
I/O 15

TDI/IN 0

TMS/IN 1

RESET

BSCAN

e

M

g

k

a

b

o

l

c

G

e

n

e

r

c

L

i

o

g

c

i

k

o

l

s

c

(

B

s

G

L

B

)

A0

A1

Input Bus

A2

Output Routing Pool (ORP)

A3

A

I/O 16

4

I/O 17

be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Device pins can be safely driven to 5V signal levels to
support mixed-voltage systems.

Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2096VE device contains three Megablocks.

The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.

Input Bus

Output Routing Pool (ORP)

C

3

C

C

2

C

1

0

B7

Global

B6

Pool

(GRP)

TCK/IN 3

TDO/IN 2

1

B

0

B

Output Routing Pool (ORP)

I/O 32

I/O 33

I/O 34

I/O 35

I/O 36

I/O 37

I/O 38

Input Bus

I/O 39

I/O 40

B

I/O 41

2

I/O 42

I/O 43

I/O 44

3

B

I/O 45

I/O 46

B5

B4

CLK 0

I/O 47

Input Bus

Output Routing Pool (ORP)

CLK 1

CLK 2

0917/2096VE

Y0Y1Y2

Programmable Open-Drain Outputs

In addition to the standard output configuration, the
outputs of the ispLSI 2096VE are individually program­mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro­grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.

I/O 63
I/O 62
I/O 61
I/O 60

I/O 59
I/O 58
I/O 57
I/O 56

I/O 55
I/O 54
I/O 53
I/O 52

I/O 51
I/O 50
I/O 49
I/O 48

Clocks in the ispLSI 2096VE device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock can
be generated in any GLB for its own clock.

2

Specifications ispLSI 2096VE

Absolute Maximum Ratings

1

Supply Voltage Vcc.................................. -0.5 to +5.4V

Input Voltage Applied............................... -0.5 to +5.6V

Off-State Output Voltage Applied ............ -0.5 to +5.6V

Storage Temperature................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (TJ) with Power Applied ... 150°C

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Condition

V
V

V

CC

IL
IH

SYMBOL

Supply Voltage

Input Low Voltage
Input High Voltage

PARAMETER

Commercial
Industrial

TA = 0°C to + 70°C

= -40°C to + 85°C

T

A

MIN. MAX. UNITS

3.0

3.0

V – 0.5

SS

2.0

3.6

3.6

0.8

5.25

Table 2-0005/2096VE

V
V
V
V

Capacitance (TA=25°C, f=1.0 MHz)

SYMBOL

C

1

C

2

C

3

I/O Capacitance
Clock and Global Output Enable Capacitance

PARAMETER

Erase Reprogram Specifications

PARAMETER MINIMUM MAXIMUM UNITS

Erase/Reprogram Cycles

UNITSTYPICAL TEST CONDITIONS

8Dedicated Input Capacitance
6

10

10000 – Cycles

pf
pf
pf V = 3.3V, V = 0.0V

V = 3.3V, V = 0.0V

CC

V = 3.3V, V = 0.0V

CC I/O

CC Y

IN

Table 2-0006/2096VE

Table 2-0008/2096VE

3

+ 3.3V

R

1

R

2

C

L

*

Device
Output

Test

Point

*

CL includes Test Fixture and Probe Capacitance.

0213A/2096VE

Switching Test Conditions

Specifications ispLSI 2096VE

Input Pulse Levels
Input Rise and Fall Time

Input Timing Reference Levels
Output Timing Reference Levels
Output Load

3-state levels are measured 0.5V from

GND to 3.0V

≤ 1.5ns 10% to 90%

1.5V

1.5V

See Figure 2

Table 2-0003/2096VE

Figure 2. Test Load

steady-state active level.

Output Load Conditions (see Figure 2)

TEST CONDITION R1 R2 CL

A 316Ω 348Ω 35pF

Active High

B

Active Low
Active High to Z

at V -0.5V

C

Active Low to Z
at V +0.5V

OH

OL

∞ 348Ω 35pF

316Ω 348Ω 35pF

∞ 348Ω 5pF

316Ω 348Ω 5pF

Table 2-0004/2096VE

DC Electrical Characteristics

Over Recommended Operating Conditions

SYMBOL

VOL
VOH
IIL

IIH
IIL-isp

IIL-PU
IOS

ICC

Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current

Input or I/O High Leakage Current

BSCAN Input Low Leakage Current
I/O Active Pull-Up Current

1

Output Short Circuit Current

2, 4

Operating Power Supply Current

1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test

PARAMETER

CONDITION MIN. TYP. MAX. UNITS

I = 8 mA

OL

I = -4 mA

OH

0V ≤ V ≤ V (Max.)

IN IL

(V – 0.2)V ≤ V ≤ V

CC

V ≤ V ≤ 5.25V

IN

CC

0V ≤ V ≤ V
0V ≤ V ≤ V
V = 3.3V, V = 0.5V
V = 0.0V, V = 3.0V

f = 1 MHz

IL

IN

IN IL

CC OUT

IL

CLOCK

IH

OUT

CC

IN

–

2.4

–
–
–
–
–
–

–

problems by tester ground degradation. Characterized but not 100% tested.

2. Measured using six 16-bit counters.

3. Typical values are at V = 3.3V and T = 25°C.

4. Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption

CC

CC

A

section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I .

CC

3

–
–
–
–
–
–
–
–

125

0.4

–

-10
10
10

-150

-150

-100

–

Table 2-0007A/2096VE

µA
µA
µA
µA
µA

mA
mA

V
V

4