Lattice Semiconductor Corporation ISPLSI2064VL-165LJ44, ISPLSI2064VL-165LB100, ISPLSI2064VL-135LT44, ISPLSI2064VL-135LT44I, ISPLSI2064VL-135LT100 Datasheet

ispLSI® 2064VL

Global Routing Pool

(GRP)

A0

A1

A3

Input Bus

Output Routing Pool (ORP)

B3

B2

B1

B0

Input Bus

Output Routing Pool (ORP)

A2

GLB

Logic
Array

DQ

DQ

DQ

DQ

A4

A5

A6 A7

B7

B6

B5 B4

Input Bus

Output Routing Pool (ORP)

Input Bus

Output Routing Pool (ORP)

0139A/2064VL

2.5V In-System Programmable

SuperFAST™ High Density PLD

Features

• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates

— 64 and 32 I/O Pin Versions, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible with
ispLSI 2064V and 2064VE Devices

• 2.5V LOW VOLTAGE 2064 ARCHITECTURE
— Interfaces with Standard 3.3V TTL Devices (Inputs

and I/Os are 3.3V Tolerant)
— 60 mA Typical Active Current

• HIGH-PERFORMANCE E
—

—
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE
— 2.5V In-System Programmability (ISP™) Using

— Open-Drain Output Option for Flexible Bus Interface

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Prototyping

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs

— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM­PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore

— PC and UNIX Platforms

Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. September 2000
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

2064vl_02 1

2

CMOS® TECHNOLOGY

fmax = 165MHz Maximum Operating Frequency
tpd = 5.5ns Propagation Delay

Boundary Scan Test Access Port (TAP)

Capability, Allowing Easy Implementation of Wired-OR
or Bus Arbitration Logic

Market and Improved Product Quality

Tools, Timing Simulator and ispANALYZER™

Functional Block Diagram

Description

The ispLSI 2064VL is a High Density Programmable
Logic Device available in 64 and 32 I/O-pin versions. The
device contains 64 Registers, four Dedicated Input pins,
three Dedicated Clock Input pins, two dedicated Global
OE input pins and a Global Routing Pool (GRP). The
GRP provides complete interconnectivity between all of
these elements. The ispLSI 2064VL features in-system
programmability through the Boundary Scan Test Ac­cess Port (TAP) and is 100% IEEE 1149.1 Boundary
Scan Testable. The ispLSI 2064VL offers non-volatile
reprogrammability of the logic, as well as the intercon­nect, to provide truly reconfigurable systems.

The basic unit of logic on the ispLSI 2064VL device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 2064VL device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.

Specifications ispLSI 2064VL

Functional Block Diagram

Figure 1. ispLSI 2064VL Functional Block Diagram (64-I/O and 32-I/O Versions)

GOE 1

GOE 0

Megablock

I/O 63

I/O 62

I/O 61

I/O 60

I/O 59

I/O 58

I/O 57

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

Input Bus

Output Routing Pool (ORP)

B7 B6 B5 B4

I/O 50

I/O 49

I/O 48

Generic Logic
Blocks (GLBs)

Megablock

I/O 31

I/O 30

I/O 29

Output Routing Pool (ORP)

B7 B6 B5 B4

I/O 28

Input Bus

I/O 27

I/O 26

I/O 25

I/O 24

Generic Logic
Blocks (GLBs)

I/O 0
I/O 1
I/O 2
I/O 3

I/O 4
I/O 5
I/O 6
I/O 7

I/O 8

I/O 9
I/O 10
I/O 11

I/O 12
I/O 13
I/O 14
I/O 15

TDI/IN 0

TMS/IN 1

RESET

BSCAN

A0

A1

Input Bus

A2

Output Routing Pool (ORP)

A3

Global Routing Pool

(GRP)

A4 A5 A6 A7

Output Routing Pool (ORP)

Input Bus

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

B3

B2

B1

B0

CLK 0

Y0Y1Y2

CLK 1

I/O 47
I/O 46
I/O 45
I/O 44

I/O 43
I/O 42
I/O 41
I/O 40

I/O 39

Input Bus

I/O 38
I/O 37
I/O 36

I/O 35

Output Routing Pool (ORP)

I/O 34
I/O 33
I/O 32

TCK/IN 3
TDO/IN 2

CLK 2

0139B/2064VL

The 64-I/O 2064VL contains 64 I/O cells, while the 32­I/O version contains 32 I/O cells. Each I/O cell is directly
connected to an I/O pin and can be individually pro­grammed to be a combinatorial input, output or
bi-directional I/O pin with 3-state control and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Device pins can be safely driven to 3.3V signal levels to
support mixed-voltage systems.

Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and
two or one ORPs are connected together to make a
Megablock (see Figure 1). The outputs of the eight GLBs
are connected to a set of 32 or 16 universal I/O cells by
two or one ORPs. Each ispLSI 2064VL device contains
two Megablocks.

I/O 23
I/O 22
I/O 21
I/O 20

Input Bus

I/O 19

Output Routing Pool (ORP)

I/O 18
I/O 17
I/O 16

GOE0/IN 3
TMS/IN 2

CLK 2

0139B/2064VL.32IO

TCK/Y2

TDI/IN 0

TDO/IN 1

BSCAN

I/O 0
I/O 1
I/O 2
I/O 3

I/O 4
I/O 5
I/O 6
I/O 7

A0

A1

Input Bus

A2

Output Routing Pool (ORP)

A3

Global Routing Pool

(GRP)

A4 A5 A6 A7

Output Routing Pool (ORP)

Input Bus

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

B3

B2

B1

B0

CLK 0

GOE1/Y0

CLK 1

RESET/Y1

GLB basis. The asynchronous or Product Term clock can
be generated in any GLB for its own clock.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the
outputs of the ispLSI 2064VL are individually program­mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro­grammable fuse. The default configuration is totem-pole
configuration. The open-drain/totem-pole option is se­lectable through the ispDesignEXPERT software tools.

The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.

Clocks in the ispLSI 2064VL device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a

2

Specifications ispLSI 2064VL

Absolute Maximum Ratings

Supply Voltage V

.................................................-0.5 to +4.05V

cc

1

Input Voltage Applied................................... -0.5 to +4.05V

Off-State Output Voltage Applied ................ -0.5 to +4.05V

Storage Temperature..................................... -65 to 150°C

Case Temp. with Power Applied .................... -55 to 125°C

Max. Junction Temp. (TJ) with Power Applied ............ 150°C

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Condition

V
V

V

CC

IL
IH

SYMBOL

Supply Voltage

Input Low Voltage
Input High Voltage

PARAMETER

Commercial
Industrial

TA = 0°C to + 70°C

= -40°C to + 85°C

T

A

MIN. MAX. UNITS

2.3

2.3

-0.3

1.7

2.7

2.7

0.7

3.6

Table 2-0005/2064VL

V
V
V
V

Capacitance (TA=25°C, f=1.0 MHz)

SYMBOL

C

1

C

2

C

3

I/O Capacitance
Clock and Global Output Enable Capacitance

PARAMETER

Erase Reprogram Specifications

PARAMETER MINIMUM MAXIMUM UNITS

Erase/Reprogram Cycles

UNITSTYPICAL TEST CONDITIONS

8Dedicated Input Capacitance
6

10

10,000 — Cycles

pf
pf
pf V = 2.5V, V = 0.0V

V = 2.5V, V = 0.0V

CC

V = 2.5V, V = 0.0V

CC I/O

CC Y

IN

Table 2-0006/2064VL

Table 2-0008/2064VL

3

Switching Test Conditions

V

CC

R

1

R

2

C

L

*

Device
Output

Test

Point

*C

L

includes Test Fixture and Probe Capacitance.

0213A/2064VL

Specifications ispLSI 2064VL

Input Pulse Levels
Input Rise and Fall Time
Input Timing Reference Levels

Output Timing Reference Levels
Output Load

3-state levels are measured 0.15V from
steady-state active level.

GND to V

≤ 1.5 ns 10% to 90%

See Figure 2

CC

VCC/2

/2

V

CC

Table 2-0003/2064VL

Figure 2. Test Load

Output Load Conditions (see Figure 2)

TEST CONDITION R1 R2 CL

A 250Ω 218Ω 35pF

Active High

B

Active Low
Active High to Z

at V -0.15V

C

Active Low to Z
at V +0.15V

OH

OL

∞

250Ω

∞

250Ω

218Ω 35pF

∞

35pF

218Ω 5pF

∞

Table 2-0004/2064VL

5pF

DC Electrical Characteristics

Over Recommended Operating Conditions

SYMBOL

V

OL

V

OH

5

I

IL

I

IH

I

IL-isp

I

IL-PU

I

OS

I

CC

Output Low Voltage

Output High Voltage

Input or I/O Low Leakage Current
Input or I/O High Leakage Current
BSCAN Input Pull-Up Current
I/O Active Pull-Up Current

1

Output Short Circuit Current

2, 4

Operating Power Supply Current

1. One output at a time for a maximum duration of one second. V

PARAMETER

CONDITION MIN. TYP. MAX. UNITS

IOL = 100µA
I

= 8mA

OL

= -1mA

I

OH

= -4mA

OH

0V ≤ V ≤ V (Max.)

IN IL

V

(min) ≤ VIN ≤ 3.6V

IH

0V ≤ V ≤ V

IN

IL

0V ≤ V ≤ V

IN IL

V = 2.5V, V = 0.5V

CC OUT

V = 0.0V, V = 2.5V

IL IH

f = 1 MHz

CLK

= 0.5V was selected to avoid test

OUT

—
——0.4 V

VCC - 0.2

2.0

1.8 ——VI

—
—
—
—
—

—

problems by tester ground degradation. Characterized but not 100% tested.

2. Measured using four 16-bit counters.

3. Typical values are at V

4. Maximum I

varies widely with specific device configuration and operating frequency. Refer to Power Consumption

CC

= 2.5V and TA = 25°C.

CC

section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I

CC

.

5. With no pull-up resistors.

3

—

——VIOH = -100µA
—

—
—
—
—
—

60

0.2

—

-10
10

-150

-150

-100

Table 2-0007/2064VL

V

V

µA
µA
µA
µA

mA
mA—

4

External Timing Parameters

Over Recommended Operating Conditions

Specifications ispLSI 2064VL

3

TEST

COND.

tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl

1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.

2. Standard 16-bit counter using GRP feedback.

3. Reference Switching Test Conditions section.

A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass — 7.5 — 10.0 ns
A 2 Data Propagation Delay —— ns
A 3 Clock Frequency with Internal Feedback 135 — 100 — MHz

— 4 Clock Frequency with External Feedback ——MHz
— 5 Clock Frequency, Max. Toggle ——MHz
— 6 GLB Reg. Setup Time before Clock, 4 PT Bypass ——ns
A 7 GLB Reg. Clock to Output Delay, ORP Bypass —— ns
— 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 — ns
— 9 GLB Reg. Setup Time before Clock 6.0 — ns
A 10 GLB Reg. Clock to Output Delay —— ns
— 11 GLB Reg. Hold Time after Clock 0.0 — ns
A 12 Ext. Reset Pin to Output Delay, ORP Bypass —— ns
— 13 Ext. Reset Pulse Duration 5.5 — ns

B 14 Input to Output Enable —— ns
C 15 Input to Output Disable —— ns
B 16 Global OE Output Enable —— ns
C 17 Global OE Output Disable —— ns

— 18 External Synchronous Clock Pulse Duration, High 3.5 ——ns
— 19 External Synchronous Clock Pulse Duration, Low 3.5 ——ns

DESCRIPTION#PARAMETER

1

2

1

( )

tsu2 + tco1

-165

MIN. MAX.

— 5.5

8.0

—

165 —
118

—

166

—

3.5

—

4.0

—

—

0.0

—

4.5

5.0

—

—

0.0

6.0

—

—

5.0

10.0

—

10.0

—

6.0

—

6.0

—

3.0 —

3.0 —

MIN.

95

143

5.0

-135

10.0

4.5

—
—

5.5

—

8.0

—

12.0

12.0

7.0

7.0

-100

MIN.MAX. MAX.

13.0

77

100

6.5

5.0

0.0

8.0

6.0

0.0

13.5

6.5

15.0

15.0

9.0

9.0

5.0

5.0

Table 2-0030/2064VL

UNITS

5