Lattice Semiconductor Corporation ISPLSI2032VL-180LT48, ISPLSI2032VL-180LT44, ISPLSI2032VL-180LJ44, ISPLSI2032VL-180LB49, ISPLSI2032VL-135LT48 Datasheet

ispLSI® 2032VL

Global Routing Pool

(GRP)

A0

A1

A3

Input Bus

Output Routing Pool (ORP)

A7

A6

A5

A4

Input Bus

Output Routing Pool (ORP)

A2

GLB

Logic
Array

DQ

DQ

DQ

DQ

0139Bisp/2000

2.5V In-System Programmable

SuperFAST™ High Density PLD

Features

• SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC

— 1000 PLD Gates
— 32 I/O Pins, Two Dedicated Inputs
— 32 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible

with ispLSI 2032V and 2032VE Devices

• 2.5V LOW VOLTAGE 2032 ARCHITECTURE
— Interfaces With Standard 3.3V Devices (Inputs and

I/Os are 3.3V Tolerant)

— 45 mA Typical Active Current

• HIGH PERFORMANCE E
—

fmax = 180 MHz Maximum Operating Frequency
tpd = 5.0 ns Propagation Delay

—
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE
— 2.5V In-System Programmability (ISP™) Using

Boundary Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs

— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM­PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. September 2000
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

2032vl_02 1

2

CMOS® TECHNOLOGY

Functional Block Diagram

Description

The ispLSI 2032VL is a High Density Programmable
Logic Device containing 32 Registers, 32 Universal I/O
pins, two Dedicated Input Pins, three Dedicated Clock
Input Pins, one dedicated Global OE input pin and a
Global Routing Pool (GRP). The GRP provides complete
interconnectivity between all of these elements. The
ispLSI 2032VL features in-system programmability
through the Boundary Scan Test Access Port (TAP) and
is 100% IEEE 1149.1 Boundary Scan Testable. The
ispLSI 2032VL offers non-volatile reprogrammability of
the logic, as well as the interconnect to provide truly
reconfigurable systems.

The basic unit of logic on the ispLSI 2032VL device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. A7 (see Figure 1). There are a total of eight GLBs in the
ispLSI 2032VL device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.

Functional Block Diagram

Figure 1. ispLSI 2032VL Functional Block Diagram

GOE 0

Specifications ispLSI 2032VL

I/O 0
I/O 1
I/O 2
I/O 3

I/O 4
I/O 5
I/O 6
I/O 7

I/O 8

I/O 9
I/O 10
I/O 11

I/O 12
I/O 13
I/O 14
I/O 15

TDI/IN 0

TDO/IN 1

TMS/NC

BSCAN

Note: *Y1 and RESET are multiplexed on the same pin

Input Bus

A0

A1

A2

Output Routing Pool (ORP)

A3

Global Routing Pool

The device also has 32 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, output or bi­directional I/O pin with 3-state control, and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Device pins can be safely driven to 3.3 Volt signal levels
to support mixed-voltage systems.

Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the ORPs. Each
ispLSI 2032VL device contains one Megablock.

The GRP has as its inputs the outputs from all of the GLBs
and all of the inputs from the bi-directional I/O cells. All of
these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.

I/O 31

Input Bus

0139B/2032VL

I/O 30
I/O 29
I/O 28

I/O 27
I/O 26
I/O 25
I/O 24

I/O 23
I/O 22
I/O 21
I/O 20

I/O 19
I/O 18
I/O 17
I/O 16

(GRP)

Generic Logic

Blocks (GLBs)

Y1*

TCK/Y2

Y0

A7

A6

A5

Output Routing Pool (ORP)

A4

CLK 1

CLK 2

CLK 0

Clocks in the ispLSI 2032VL device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock can
be generated in any GLB for its own clock.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the
outputs of the ispLSI 2032VL are individually program­mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro­grammable fuse. The default configuration is a totem-pole
configuration. The open-drain/totem-pole option is se­lectable through the ispDesignEXPERT software tools.

2

Specifications ispLSI 2032VL

Absolute Maximum Ratings

1

Supply Voltage Vcc................................ -0.5 to +4.05V

Input Voltage Applied............................. -0.5 to +4.05V

Off-State Output Voltage Applied .......... -0.5 to +4.05V

Storage Temperature..............................-65 to +150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (TJ) with Power Applied ... 150°C

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification

is not implied (while programming, follow the programming specifications).

DC Recommended Operating Condition

V
V

V

CC

IL
IH

SYMBOL

Supply Voltage

Input Low Voltage
Input High Voltage

PARAMETER

Commercial
Industrial

TA = 0°C to + 70°C

= -40°C to + 85°C

T

A

MIN. MAX. UNITS

2.3

2.3

-0.3

1.7

2.7

2.7

0.7

3.6

Table 2-0005/2032VL

V
V
V
V

Capacitance (TA=25°C, f=1.0 MHz)

SYMBOL

C

1

C

2

C

3

I/O Capacitance
Clock Capacitance

PARAMETER

Erase Reprogram Specifications

PARAMETER MINIMUM MAXIMUM UNITS

Erase/Reprogram Cycles

UNITSTYPICAL TEST CONDITIONS

8Dedicated Input Capacitance
6

10

10,000 – Cycles

pf
pf
pf V = 2.5V, V = 0.0V

V = 2.5V, V = 0.0V

CC

V = 2.5V, V = 0.0V

CC I/O

CC Y

IN

Table 2-0006/2032VL

Table 2-0008A/2032VL

3

Switching Test Conditions

V

CC

R

1

R

2

C

L

*

Device
Output

Test

Point

*C

L

includes Test Fixture and Probe Capacitance.

0213A/2032VL

Specifications ispLSI 2032VL

Input Pulse Levels
Input Rise and Fall Time

GND to V

≤ 1.5 ns

CC

Figure 2. Test Load

10% to 90%
Input Timing Reference Levels

Output Timing Reference Levels
Output Load

3-state levels are measured 0.15V from

V

/2

CC

/2

V

CC

See Figure 2

Table 2-0003/2032VL

steady-state active level.

Output Load Conditions (see Figure 2)

TEST CONDITION R1 R2 CL

A 250Ω 218Ω 35pF

Active High

B

Active Low
Active High to Z

at V -0.15V

C

Active Low to Z
at V +0.15V

OH

OL

∞

250Ω

∞

250Ω

218Ω 35pF

∞

35pF

218Ω 5pF

∞

Table 2-0004A/2032VL

5pF

DC Electrical Characteristics

Over Recommended Operating Conditions

SYMBOL

V

OL

V

OH

5

I

IL

I

IH

I

IL-isp

I

IL-PU

I

OS

I

CC

Output Low Voltage

Output High Voltage

Input or I/O Low Leakage Current
Input or I/O High Leakage Current
BSCAN Input Pull-Up Current
I/O Active Pull-Up Current

1

Output Short Circuit Current

2, 4

Operating Power Supply Current

1. One output at a time for a maximum duration of one second. V

PARAMETER

CONDITION MIN. TYP. MAX. UNITS

IOL = 100µA
I

= 8mA

OL

= -1mA

I

OH

= -4mA

OH

0V ≤ V ≤ V (Max.)

IN IL

V

(min) ≤ VIN ≤ 3.6V

IH

0V ≤ V ≤ V

IN

IL

0V ≤ V ≤ V

IN IL

V = 2.5V, V = 0.5V

CC OUT

V = 0.0V, V = 2.5V

IL IH

f = 1 MHz

CLK

= 0.5V was selected to avoid test

OUT

—
——0.4 V

VCC - 0.2

2.0

1.8 ——VI

—
—
—
—
—

—

problems by tester ground degradation. Characterized but not 100% tested.

2. Measured using two 16-bit counters.

3. Typical values are at V

4. Maximum I
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I

5. With no pull-up resistors.

varies widely with specific device configuration and operating frequency. Refer to Power Consumption

CC

= 2.5V and TA = 25°C.

CC

.

CC

3

—

——VIOH = -100µA
—

—
—
—
—
—

45

0.2

—

-10
10

-150

-150

-100

Table 2-0007/2032VL

V

V

µA
µA
µA
µA

mA
mA—

4