Lattice Semiconductor Corporation ISPLSI1048C-50LG-883 Datasheet
ispLSI® 1048C/883
In-System Programmable High Density PLD
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— 8000 PLD Gates
— 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output
Enables
— 288 Registers
— High-Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E
— fmax = 50 MHz Maximum Operating Frequency
—
tpd = 22 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E
2
— 100% Tested at Time of Manufacture
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
2
CMOS® TECHNOLOGY
CMOS Technology
Functional Block Diagram
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
A0
A1
A2
A3
Global Routing Pool (GRP) GLB
A4
A5
Output Routing Pool
A6
A7
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool
Output Routing Pool
E7 E6 E5 E4 E3 E2 E1 E0
DQ
DQ
Logic
Array
DQ
DQ
C0 C1 C2 C3 C4 C5 C6 C7
Output Routing Pool
D7
D6
D5
D4
D3
D2
Output Routing Pool
D1
D0
CLK
0139G1A-isp
Description
The ispLSI 1048C/883 is a High-Density Programmable
Logic Device processed in full compliance to MIL-STD-
883. This military grade device contains 288 Registers,
96 Universal I/O pins, 12 Dedicated Input pins, two
Global Output Enables (GOE), four Dedicated Clock
Input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 1048C/883 features 5-Volt insystem programming and in-system diagnostic
capabilities. It is the first device which offers non-volatile
reprogrammability of the logic, and the interconnect to
provide truly reconfigurable systems. Compared to the
ispLSI 1048, the ispLSI 1048C/883 offers two additional
dedicated inputs and two new Global Output Enable pins.
The basic unit of logic on the ispLSI 1048C/883 device is
the Generic Logic Block (GLB). The GLBs are labeled A0,
A1 .. F7 in figure 1. There are a total of 48 GLBs in the
ispLSI 1048C/883 devices. Each GLB has 18 inputs, a
programmable AND/OR/XOR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. September 2000
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
1048CMIL_01
1
Specifications ispLSI 1048C/883
Functional Block Diagram
Figure 1. ispLSI 1048C/883 Functional Block Diagram
RESET
GOE0
GOE1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
SDI/IN 0
MODE/IN 1
ispEN
Generic
Logic Blocks
Input Bus
Output Routing Pool (ORP)
Megablock
(GLBs)
A1
A2
A3
A4
A5
A6
A7
IN2
I/O94I/O95I/O93I/O92I/O91I/O90I/O89I/O88I/O87I/O86I/O85I/O84I/O83I/O82I/O81I/O
Input Bus
Output Routing Pool (ORP)
F7 F6 F5 F4 F3 F2 F1 F0
A0
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool (ORP)
Input Bus
SDO/
I/O17I/O16I/O18I/O19I/O20I/O21I/O22I/O23I/O24I/O25I/O26I/O27I/O28I/O29I/O30I/O
IN3
80
31
IN
IN
11
10
Global
Routing
Pool
(GRP)
SCLK/
IN 5IN4
I/O78I/O79I/O77I/O76I/O75I/O74I/O73I/O72I/O71I/O70I/O69I/O68I/O67I/O66I/O65I/O
Input Bus
Output Routing Pool (ORP)
E7 E6 E5 E4 E3 E2 E1 E0
C0 C1 C2 C3 C4 C5 C6 C7
Output Routing Pool (ORP)
Input Bus
I/O33I/O32I/O34I/O35I/O36I/O37I/O38I/O39I/O40I/O41I/O42I/O43I/O44I/O45I/O46I/O
IN
IN
9
64
8
IN 7
IN 6
lnput Bus
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
D7
D6
D5
D4
D3
D2
Output Routing Pool (ORP)
D1
D0
CLK 0
CLK 1
Clock
Network
Y0Y1Y2Y
CLK 2
IOCLK 0
IOCLK 1
3
0139F(2)-48B-isp
Distribution
47
The device also has a 96 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
registered input, latched input, output or bi-directional
I/O pin with 3-state control. Additionally, all outputs have
selectable polarity, active high or active low. The signal
voltage levels are TTL-compatible, and the output drivers
can source 4 mA or sink 8 mA.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock as
shown in figure 1. The outputs of the eight GLBs are
connected to a set of 16 universal I/O cells by the ORP.
Each ispLSI 1048C/883 device contains six Megablocks.
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1048C/883 device are selected
using the Clock Distribution Network. Four dedicated
clock pins (Y0, Y1, Y2 and Y3) are brought into the
distribution network, and five clock outputs (CLK 0, CLK
1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route
clocks to the GLBs and I/O cells. The Clock Distribution
Network can also be driven from a special clock GLB (D0
on the ispLSI 1048C/883 device). The logic of this GLB
allows the user to create an internal clock from a combination of internal signals.
2
Specifications ispLSI 1048C/883
SYMBOL PARAMETER MAXIMUM
1
UNITS TEST CONDITIONS
C
1
10 pf V
CC
=5.0V, VIN=2.0V
C
2
I/O and Clock Capacitance 10 pf VCC=5.0V, V
I/O
, VY=2.0V
1. Characterized but not 100% tested.
Table 2- 0006mil
Dedicated Input Capacitance
Absolute Maximum Ratings
1
Supply Voltage Vcc...................................-0.5 to +7.0V
Input Voltage Applied........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
PARAMETERSYMBOL MIN. MAX. UNITS
V
V
V
CC
IL
IH
Supply Voltage
Input Low Voltage
Input High Voltage
Military/883 T
= -55°C to +125°C
C
4.5
0
2.0
5.5
0.8
Vcc + 1
V
V
V
0005A mil.eps
Capacitance (TA=25oC, f=1.0 MHz)
Data Retention Specifications
PARAMETER
Data Retention
Erase/Reprogram Cycles
MINIMUM MAXIMUM UNITS
20
10000
—
—
Years
Cycles
Table 2- 0008B
3
Switching Test Conditions
+ 5V
R
1
R
2
C
L
*
Device
Output
Test
Point
*
CL includes Test Fixture and Probe Capacitance.
-
Specifications ispLSI 1048C/883
Input Pulse Levels GND to 3.0V
Input Rise and Fall Time ≤ 3ns 10% to 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See figure 2
3-state levels are measured 0.5V from steady-state
active level.
-
Output Load Conditions (see figure 2)
Test Condition R1 R2 CL
A470Ω 390Ω 35pF
B Active High 390Ω 35pF
Active Low 470Ω 390Ω 35pF
Active High to Z 390Ω 5pF
Cat V
- 0.5V
OH
Active Low to Z 470Ω 390Ω 5pF
+ 0.5V
at V
OL
∞
∞
Table 2- 0004A
Figure 2. Test Load
DC Electrical Characteristics
Over Recommended Operating Conditions
–
–
–
–
–
–
–
165
3
UNITSTYP.
0.4
–
-10
10
-150
-150
-200
260
0007A-48C mil
SYMBOL
VOL
VOH
IIL
IIH
IIL-isp
IIL-PU
1
IOS
2,4
ICC
Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
isp Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
PARAMETER
IOL =8 mA
=-4 mA
I
OH
0V ≤ VIN ≤ VIL (MAX.)
3.5V ≤ V
0V ≤ VIN ≤ VIL (MAX.)
0V ≤ VIN ≤ V
VCC = 5V, V
= 0.5V, V
V
IL
f
TOGGLE
1. One output at a time for a maximum duration of one second. V
degradation. Characterized but not 100% tested.
2. Measured using twelve 16-bit counters.
3. Typical v alues are at V
4. Maximum I
tion of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum
.
I
CC
= 5V and TA = 25oC.
varies widely with specific device configuration and operating frequency . Refer to the Power Consumption sec
CC
CC
CONDITION
≤ V
IN
IL
OUT
IH
= 1 MHz
MIN. MAX.
–
2.4
–
CC
–
–
–
= 0.5V
= 3.0V
= 0.5V was selected to avoid test problems by tester ground
out
–
–
V
V
µA
µA
µA
µA
mA
mA
4
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