Lattice Semiconductor Corporation ispLSI1032-80LT, ispLSI1032-80LJ, ispLSI1032-60LTI, ispLSI1032-60LJI, ispLSI1032-60LJ Datasheet

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ispLSI® 1032

In-System Programmable High Density PLD

Features

• HIGH-DENSITY PROGRAMMABLE LOGIC — High Speed Global Interconnect

— 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Fast Random Logic — Security Cell Prevents Unauthorized Copying

• HIGH PERFORMANCE E —

fmax = 90 MHz Maximum Operating Frequency

— fmax = 60 MHz for Industrial and Military/883 Devices —

tpd = 12 ns Propagation Delay

— TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile E — 100% Tested

• IN-SYSTEM PROGRAMMABLE — In-System Programmable™ (ISP™) 5-Volt Only — Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEX-

IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Four Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Flexible Pin Placement — Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

USE ispLSI 1032E FOR NEW

CMOS® TECHNOLOGY

CMOS Technology

COMMERCIAL & INDUSTRIAL

Functional Block Diagram

Output Routing Pool

D7 D6 D5 D4 D3 D2 D1 D0

Logic Array

GLB

A1 A2 A3 A4 A5

Output Routing Pool

Global Routing Pool (GRP)

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

Description

The ispLSI 1032 is a High-Density Programmable Logic Device containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1032 features 5-Volt in-system programming and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly

DESIGNS

reconfigurable systems. The basic unit of logic on the ispLSI 1032 device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. D7 (see figure 1). There are a total of 32 GLBs in the ispLSI 1032 device. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.

C7 C6 C5 C4 C3 C2 C1

Output Routing Pool

CLK

Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. March 1999 Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com

1032_07

Functional Block Diagram

Figure 1. ispLSI 1032 Functional Block Diagram

Specifications ispLSI 1032

RESET

I/O 0 I/O 1 I/O 2 I/O 3

I/O 4 I/O 5 I/O 6 I/O 7

I/O 8

I/O 9 I/O 10 I/O 11

I/O 12 I/O 13 I/O 14 I/O 15

SDI/IN 0

MODE/IN 1

ispEN

Input Bus

Megablock

SDO/IN 2

SCLK/IN 3

I/O62I/O63I/O61I/O60I/O59I/O58I/O57I/O56I/O55I/O54I/O53I/O52I/O51I/O50I/O49I/O

Generic

Logic Blocks

(GLBs)

D7 D6 D5 D4 D3 D2 D1 D0

Output Routing Pool (ORP)

B0 B1 B2 B3 B4 B5 B6 B7

I/O17I/O16I/O18I/O19I/O20I/O21I/O22I/O23I/O24I/O25I/O26I/O27I/O28I/O29I/O30I/O

Input Bus

Output Routing Pool (ORP)

Global

Routing

Pool

(GRP)

Output Routing Pool (ORP)

Input Bus

IN7IN

IN 5 IN 4

lnput Bus

0139(1)-32-isp

I/O 47 I/O 46 I/O 45 I/O 44

I/O 43 I/O 42

I/O 41 I/O 40

I/O 39 I/O 38 I/O 37 I/O 36

I/O 35 I/O 34 I/O 33 I/O 32

Distribution

Network

Y0Y1Y2Y

Output Routing Pool (ORP)

CLK 0

Clock

CLK 1 CLK 2 IOCLK 0 IOCLK 1

The device also has 64 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. Additionally, all outputs are polarity selectable, active high or active low. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA.

Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. The I/O cells within the Megablock also share a common Output Enable (OE) signal. The ispLSI 1032 device contains four of these Megablocks.

The GRP has as its inputs the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew.

Clocks in the ispLSI 1032 device are selected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (C0 on the ispLSI 1032 device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device.

Specifications ispLSI 1032

Absolute Maximum Ratings

Supply Voltage Vcc.................................. -0.5 to +7.0V

Input Voltage Applied........................-2.5 to VCC +1.0V

Off-State Output Voltage Applied .....-2.5 to VCC +1.0V

Storage Temperature................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (TJ) with Power Applied ... 150°C

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).

DC Recommended Operating Conditions

PARAMETERSYMBOL MIN. MAX. UNITS

5.25

5.5

0.8

Commercial TA = 0°C to +70°C Supply Voltage

Industrial T

Military/883 T

Input Low Voltage

= -40°C to +85°C

= -55°C to +125°C

4.75

4.5

4.5 0

Input High Voltage

Capacitance (TA=25oC, f=1.0 MHz)

SYMBOL PARAMETER MAXIMUM

Guaranteed but not 100% tested.

Commercial/Industrial 8 pf VCC=5.0V, VIN=2.0V Dedicated Input Capacitance

Military 10 pf V I/O and Clock Capacitance 10 pf VCC=5.0V, V

Data Retention Specifications

PARAMETER

Data Retention Erase/Reprogram Cycles

MINIMUM MAXIMUM UNITS

10000

2.0

UNITS TEST CONDITIONS

— —

Vcc + 1

=5.0V, VIN=2.0V

Table 2- 0005Aisp w/mil.eps

, VY=2.0V

I/O

Table 2- 0006

Years

Cycles

Table 2- 0008B

Switching Test Conditions

Specifications ispLSI 1032

Input Pulse Levels GND to 3.0V Input Rise and Fall Time ≤ 3ns 10% to 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load See figure 2

3-state levels are measured 0.5V from steady-state active level.

Output Load Conditions (see figure 2)

Test Condition R1 R2 CL

A 470Ω 390Ω 35pF B Active High 390Ω 35pF

Active Low 470Ω 390Ω 35pF Active High to Z 390Ω 5pF

Cat V

- 0.5V

Active Low to Z 470Ω 390Ω 5pF

+ 0.5V

at V

∞

Figure 2. Test Load

+ 5V

Device Output

CL includes Test Fixture and Probe Capacitance.

Test

Point

DC Electrical Characteristics

Over Recommended Operating Conditions

– – – – – – –

130 135

MAX.TYP.

0.4

–

-10 10

-150

-200 190 220

UNITS

V V

µA µA µA µA

mA mA mA

Table 2- 0007A-32-isp

SYMBOL

IL-isp

IL-PU

2,4

PARAMETER CONDITION

Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current isp Input Low Leakage Current I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current

IOL =8 mA

=-4 mA

0V ≤ V

3.5V ≤ V

≤ VIL (MAX.)

≤ V

0V ≤ VIN ≤ VIL (MAX.) 0V ≤ V VCC = 5V, V V f

≤ V

= 0.5V

OUT

= 0.5V, V

= 1 MHz Industrial/Military

TOGGLE

= 3.0V Commercial

MIN.

–

2.4

– – – – – – –

1. One output at a time for a maximum duration of one second.

2. Measured using eight 16-bit counters.

3. Typical values are at V

4. Maximum I

varies widely with specific device configuration and operating frequency . Refer to the Power Consumption sec-

= 5V and TA = 25oC.

tion of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum

External Timing Parameters

Over Recommended Operating Conditions

Specifications ispLSI 1032

PARAMETER #

pd1

pd2

max (Int.)

max (Ext.)

max (Tog.)

su1

co1

su2

co2

rw1

dis

su5

1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-Bit counter using GRP feedback.

4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.

5. Reference Switching Test Conditions section.

TEST

COND.

DESCRIPTION

Data Propagation Delay, 4PT bypass, ORP bypass

Data Propagation Delay, Worst Case Path

Clock Frequency with Internal Feedback

–

Clock Frequency with External Feedback

–

Clock Frequency, Max Toggle

–

GLB Reg. Setup Time before Clock, 4PT bypass

GLB Reg. Clock to Output Delay, ORP bypass

–

GLB Reg.

–

GLB Reg. Setup Time before Clock

–

GLB Reg. Clock to Output Delay

–

GLB Reg. Hold Time after Clock

Ext. Reset Pin to Output Delay

–

Ext. Reset Pulse Duration

Input to Output Enable

Input to Output Disable

–

Ext. Sync. Clock Pulse Duration, High

–

Ext. Sync. Clock Pulse Duration, Low

–

I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)

–

I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)

( )

Hold Time after Clock, 4 PT bypass

tsu2 + tco1

-90

MIN. MAX.

– –

90.9

58.8 125

–

0 9

–

USE 1032E-100

– –

4 4 2

6.5

MIN. MAX.

12 17

– – –

100

–

– –

–

FOR NEW DESIGNS

– – – –

6.5

-80 -60

MIN. MAX.

–

USE 1032E-70

–

FOR NEW DESIGNS

–

USE 1032E-70

– –

6 6

2.5

8.5

Table 2-0030-32/90,80,60C

UNITS

–

MHz

–

MHz

–

MHz

–

22.5

–

FOR NEW DESIGNS

–

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