Lattice Semiconductor Corporation ISPGDX240VA-9B388I, ISPGDX240VA-7B388I, ISPGDX240VA-7B388, ISPGDX240VA-4B388 Datasheet

ispGDX

240VA

• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY

— Advanced Architecture Addresses Programmable

PCB Interconnect, Bus Interface Integration and

Jumper/Switch Replacement — “Any Input to Any Output” Routing — Fixed HIGH or LOW Output Option for Jumper/DIP

Switch Emulation — Space-Saving PQFP and BGA Packaging — Dedicated IEEE 1149.1-Compliant Boundary Scan

Test

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 3.3V Core Power Supply

— 4.5ns Input-to-Output/4.5ns Clock-to-Output Delay — 200MHz Maximum Clock Frequency — TTL/3.3V/2.5V Compatible Input Thresholds and

Output Levels (Individually Programmable) — Low-Power: 16.5mA Quiescent Icc — 24mA IOL Drive with Programmable Slew Rate

Control Option — PCI Compatible Drive Capability — Schmitt Trigger Inputs for Noise Immunity — Electrically Erasable and Reprogrammable — Non-Volatile E2CMOS Technology

• ispGDXVA™ OFFERS THE FOLLOWING ADVANTAGES — 3.3V In-System Programmable Using Boundary Scan

Test Access Port (TAP)

— Change Interconnects in Seconds

• FLEXIBLE ARCHITECTURE — Combinatorial/Latched/Registered Inputs or Outputs

— Individual I/O Tri-state Control with Polarity Control — Dedicated Clock/Clock Enable Input Pins (four) or

Programmable Clocks/Clock Enables from I/O Pins (60) — Single Level 4:1 Dynamic Path Selection (Tpd = 4.5ns) — Programmable Wide-MUX Cascade Feature

Supports up to 16:1 MUX — Programmable Pull-ups, Bus Hold Latch and Open

Drain on I/O Pins — Outputs Tri-state During Power-up (“Live Insertion”

Friendly)

• DESIGN SUPPORT THROUGH LATTICE’S ispGDX DEVELOPMENT SOFTWARE

— MS Windows or NT / PC-Based or Sun O/S — Easy Text-Based Design Entry — Automatic Signal Routing — Program up to 100 ISP Devices Concurrently — Simulator Netlist Generation for Easy Board-Level

Simulation

ADVANCED

In-System Programmable

3.3V Generic Digital Crosspoint

Functional Block DiagramFeatures

ISP

Control

I/O Pins C

I/O Pins A

Boundary

Scan

Control

I/O

Cells

I/O Pins D

Global Routing

Pool

(GRP)

I/O Pins B

I/O

Cells

Description

The ispGDXVA architecture provides a family of fast, flexible programmable devices to address a variety of system-level digital signal routing and interface requirements including:

• Multi-Port Multiprocessor Interfaces

• Wide Data and Address Bus Multiplexing (e.g. 16:1 High-Speed Bus MUX)

• Programmable Control Signal Routing (e.g. Interrupts, DMAREQs, etc.)

• Board-Level PCB Signal Routing for Prototyping or Programmable Bus Interfaces

The devices feature fast operation, with input-to-output signal delays (Tpd) of 4.5ns and clock-to-output delays of

4.5ns. The architecture of the devices consists of a series of

programmable I/O cells interconnected by a Global Routing Pool (GRP). All I/O pin inputs enter the GRP directly or are registered or latched so they can be routed to the required I/O outputs. I/O pin inputs are defined as four sets (A,B,C,D) which have access to the four MUX inputs

Copyright © 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. September 2000 Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

gdx240va_02

Description (Continued)

Specifications ispGDX240VA

found in each I/O cell. Each output has individual, programmable I/O tri-state control (OE), output latch clock (CLK), clock enable (CLKEN), and two multiplexer control (MUX0 and MUX1) inputs. Polarity for these signals is programmable for each I/O cell. The MUX0 and MUX1 inputs control a fast 4:1 MUX, allowing dynamic selection of up to four signal sources for a given output. A wider 16:1 MUX can be implemented with the MUX expander feature of each I/O and a propagation delay increase of

2.0ns. OE, CLK, CLKEN, and MUX0 and MUX1 inputs can be driven directly from selected sets of I/O pins. Optional dedicated clock input pins give minimum clockto-output delays. CLK and CLKEN share the same set of I/O pins. CLKEN disables the register clock when CLKEN = 0.

Through in-system programming, connections between I/O pins and architectural features (latched or registered inputs or outputs, output enable control, etc.) can be defined. In keeping with its data path application focus, the ispGDXVA devices contain no programmable logic arrays. All input pins include Schmitt trigger buffers for noise immunity. These connections are programmed into the device using non-volatile E Non-volatile technology means the device configuration is saved even when the power is removed from the device.

CMOS technology.

In addition, there are no pin-to-pin routing constraints for

any

1:1 or 1:n signal routing. That is,

as an input can drive one or more I/O pins configured as outputs.

The device pins also have the ability to set outputs to fixed HIGH or LOW logic levels (Jumper or DIP Switch mode). Device outputs are specified for 24mA sink and 12mA source current (at JEDEC LVTTL levels) and can be tied together in parallel for greater drive. On the ispGDXVA, each I/O pin is individually programmable for

3.3V or 2.5V output levels as described later. Programmable output slew rate control can be defined independently for each I/O pin to reduce overall ground bounce and switching noise.

All I/O pins are equipped with IEEE1149.1-compliant Boundary Scan Test circuitry for enhanced testability. In addition, in-system programming is supported through the Test Access Port via a special set of private commands.

The ispGDXVA I/Os are designed to withstand “live insertion” system environments. The I/O buffers are disabled during power-up and power-down cycles. When designing for “live insertion,” absolute maximum rating conditions for the Vcc and I/O pins must still be met.

I/O pin configured

Table 1. ispGDXV/VA Family Members

I/O Pins 160 I/O-OE Inputs* 40 I/O-CLK / CLKEN Inputs* 40 I/O-MUXsel1 Inputs* 40 I/O-MUXsel2 Inputs* 40 Dedicated Clock Pins** 4

EPEN 1 TOE BSCAN Interface 4

RESET

Pin Count/Package 208-Pin PQFP

* The CLK/CLK_EN, OE, MUX0 and MUX1 terminals on each I/O cell can each be assigned to

25% of the I/Os.

** Global clock pins Y0, Y1, Y2 and Y3 are multiplexed with CLKEN0, CLKEN1, CLKEN2 and

CLKEN3 respectively in all devices.

ADVANCED

ispGDXV/VA Device

ispGDX80VA ispGDX240VA

80 20 20 20 20

2 1

1 4 1

100-Pin TQFP

ispGDX160V/VA

208-Ball fpBGA

272-Ball BGA

240

60 60 60 60

4 1

1 4 1

388-Ball fpBGA

Architecture

Specifications ispGDX240VA

The ispGDXVA architecture is different from traditional PLD architectures, in keeping with its unique application focus. The block diagram is shown below. The program-

The various I/O pin sets are also shown in the block diagram below. The A, B, C, and D I/O pins are grouped

together with one group per side. mable interconnect consists of a single Global Routing Pool (GRP). Unlike ispLSI devices, there are no programmable logic arrays on the device. Control signals for OEs, Clocks/Clock Enables and MUX Controls must come from designated sets of I/O pins. The polarity of these signals can be independently programmed in each I/O cell.

Each I/O cell drives a unique pin. The OE control for each I/O pin is independent and may be driven via the GRP by one of the designated I/O pins (I/O-OE set). The I/O-OE set consists of 25% of the total I/O pins. Boundary Scan test is supported by dedicated registers at each I/O pin. In-system programming is accomplished through the standard Boundary Scan protocol.

I/O Architecture

Each I/O cell contains a 4:1 dynamic MUX controlled by

two select lines as well as a 4x4 crossbar switch con-

trolled by software for increased routing flexiability (Figure

1). The four data inputs to the MUX (called M0, M1, M2,

and M3) come from I/O signals in the GRP and/or

adjacent I/O cells. Each MUX data input can access one

quarter of the total I/Os. For example, in a 240-I/O

ispGDXVA, each data input can connect to one of 60 I/O

pins. MUX0 and MUX1 can be driven by designated I/O

pins called MUXsel1 and MUXsel2. Each MUXsel input

covers 25% of the total I/O pins (e.g. 60 out of 240). MUX0

and MUX1 can be driven from either MUXsel1 or MUXsel2.

Figure 1. ispGDXVA I/O Cell and GRP Detail (240 I/O Device)

Logic “1”

Logic “0”

I/OCell 0

240 I/O Inputs

I/O Cell 239

I/O Cell 1

•

I/O Cell 118

I/O Cell 119

120 I/O Cells

240 Input GRP

Inputs Vertical

Outputs Horizontal

I/O Cell 238

•

To 2 Adjacent

I/O Cells above

To 2 Adjacent

I/O Cells below

•

Bypass Option

CLK

CLK_EN

Reset

Prog.

Bus Hold

Pull-up

Latch

(VCCIO)

Prog. Open Drain

2.5V/3.3V Output

Prog. Slew Rate

I/O Pin

E2CMOS

Programmable

Interconnect

I/O Group A I/O Group B I/O Group C I/O Group D

From MUX Outputs

of 2 Adjacent I/O Cells

N+2

N+1

N-1

N-2

From MUX Outputs

of 2 Adjacent I/O Cells

4x4

Crossbar

Switch

4-to-1 MUX

M0 M1 M2 M3

MUX1MUX0

ADVANCED

Boundary Scan Cell

I/O Cell N

•

I/O Cell 121

• • • • • •

I/O Cell 120

120 I/O Cells

ispGDXVA architecture enhancements over ispGDX (5V)

Y0-Y3 Global

Clocks /

Clock_Enables

Global

Reset

Specifications ispGDX240VA

I/O MUX Operation

MUX1 MUX0 Data Input Selected

00 M0 01 M1 11 M2 10 M3

Flexible mapping of MUXselx to MUXx allows the user to change the MUX select assignment after the ispGDXVA device has been soldered to the board. Figure 1 shows that the I/O cell can accept (by programming the appropriate fuses) inputs from the MUX outputs of four adjacent I/O cells, two above and two below. This enables cascading of the MUXes to enable wider (up to 16:1) MUX implementations.

The I/O cell also includes a programmable flow-through latch or register that can be placed in the input or output path and bypassed for combinatorial outputs. As shown in Figure 1, when the input control MUX of the register/ latch selects the “A” path, the register/latch gets its inputs from the 4:1 MUX and drives the I/O output. When selecting the “B” path, the register/latch is directly driven by the I/O input while its output feeds the GRP. The programmable polarity Clock to the latch or register can be connected to any I/O in the I/O-CLK/CLKEN set (onequarter of total I/Os) or to one of the dedicated clock input pins (Yx). The programmable polarity Clock Enable input to the register can be programmed to connect to any of the I/O-CLK/CLKEN input pin set or to the global clock enable inputs (CLKENx). Use of the dedicated clock inputs gives minimum clock-to-output delays and minimizes delay variation with fanout. Combinatorial output mode may be implemented by a dedicated architecture bit and bypass MUX. I/O cell output polarity can be programmed as active high or active low.

ADVANCED

MUX Expander Using Adjacent I/O Cells

allow adjacent I/O cell outputs to be directly connected

without passing through the global routing pool. The

relationship between the [N+i] adjacent cells and A, B, C

and D inputs will vary depending on where the I/O cell is

located on the physical die. The I/O cells can be grouped

into “normal” and “reflected” I/O cells or I/O “hemi-

spheres.” These are defined as:

Device Normal I/O Cells Reflected I/O Cells

ispGDX80VA

ispGDX160V/VA

ispGDX240VA B29-B0, A59-A0,

Table 2 shows the relationship between adjacent I/O

cells as well as their relationship to direct MUX inputs.

Note that the MUX expansion is circular and that I/O cell

B30, for example, draws on I/Os B29 and B28, as well as

B31 and B32, even though they are in different hemi-

spheres of the physical die. Table 2 shows some typical

cases and all boundary cases. All other cells can be

extrapolated from the pattern shown in the table.

Figure 2. I/O Hemisphere Configuration of

ispGDX240VA

B9-B0, A19-A0,

B19-B0, A39-A0,

I/O cell 0 I/O cell 239

D59

D19-D10

D39-D20

D59-D30

D30 D29

B10-B19, C0-C19,

D0-D9

B20-B39, C0-C39,

D0-D19

B30-B59, C0-C59,

D0-D29

C59C0

The ispGDXVA allows adjacent I/O cell MUXes to be cascaded to form wider input MUXes (up to 16 x 1) without incurring an additional full Tpd penalty. However, there are certain dependencies on the locality of the adjacent MUXes when used along with direct MUX inputs.

Adjacent I/O Cells

Expansion inputs MUXOUT[n-2], MUXOUT[n-1], MUXOUT[n+1], and MUXOUT[n+2] are fuse-selectable for each I/O cell MUX. These expansion inputs share the same path as the standard A, B, C and D MUX inputs, and

I/O cell index increases in this direction

A59

B29 B30

I/O cell 119

B59

I/O cell 120

Direct and Expander Input Routing

Table 2 also illustrates the routing of MUX direct inputs

that are accessible when using adjacent I/O cells as

inputs. Take I/O cell D33 as an example, which is also

shown in Figure 3.

I/O cell index increases in this direction

Specifications ispGDX240VA

Figure 3. Adjacent I/O Cells vs. Direct Input Path for ispGDX240VA, I/O D33

ispGDX240VA I/O Cell

I/O Group A D31 MUX Out I/O Group B D32 MUX Out

I/O Group C D34 MUX Out

I/O Group D D35 MUX Out

4 x 4

Crossbar

Switch

.m0 .m1 .m2 .m3

S0S1

D33

It can be seen from Figure 3 that if the D11 adjacent I/O cell is used, the I/O group “A” input is no longer available as a direct MUX input.

The ispGDXVA can implement MUXes up to 16 bits wide in a single level of logic, but care must be taken when combining adjacent I/O cell outputs with direct MUX inputs. Any particular combination of adjacent I/O cells as MUX inputs will dictate what I/O groups (A, B, C or D) can be routed to the remaining inputs. By properly choosing the adjacent I/O cells, all of the MUX inputs can be utilized.

Special Features

Slew Rate Control

All output buffers contain a programmable slew rate

control that provides software-selectable slew rate op-

tions.

Open Drain Control

All output buffers provide a programmable Open-Drain

option which allows the user to drive system level reset,

interrupt and enable/disable lines directly without the

need for an off-chip Open-Drain or Open-Collector buffer.

Wire-OR logic functions can be performed at the printed

circuit board level.

Pull-up Resistor

All pins have a programmable active pull-up. A typical

resistor value for the pull-up ranges from 50kΩ to 80kΩ.

Output Latch (Bus Hold)

All pins have a programmable circuit that weakly holds

the previously driven state when all drivers connected to

the pin (including the pin's output driver as well as any

other devices connected to the pin by external bus) are

tristated.

Table 2. Adjacent I/O Cells (Mapping of ispGDX240VA)

Data C/

MUXOUT

Reflected

I/O Cells

Normal

I/O Cells

B30 B31 B32 B33 D26 D27 D28 D29 D30 D31 D32 D33 B26 B27 B28 B29

Data A/

MUXOUT

B32 B33 B34 B35 D28 D29 D30 D31 D28 D29 D30 D31 B24 B25 B26 B27

Data B/

MUXOUT

B31 B32 B33 B34 D27

ADVANCED

D28 D29 D30 D29 D30 D31 D32 B25 B26 B27 B28

B29 B30 B31 B32 D25 D26 D27 D28 D31 D32 D33 D34 B27 B28 B29 B30

Data D/

MUXOUT

B28 B29 B30 B31 D24 D25 D26 D27 D32 D33 D34 D35 B28 B29 B30 B31

User-Programmable I/Os

The ispGDX240VA features user-programmable

I/Os supporting either 3.3V or 2.5V output voltage level

options. The ispGDX240VA uses a VCCIO pin to provide

the 2.5V reference voltage when used.

PCI Compatible Drive Capability

The ispGDX240VA supports PCI compatible drive capa-

bility for all I/Os.

Applications

Specifications ispGDX240VA

The ispGDXVA Family architecture has been developed to deliver an in-system programmable signal routing solution with high speed and high flexibility. The devices are targeted for three similar but distinct classes of endsystem applications:

Programmable, Random Signal Interconnect (PRSI)

This class includes PCB-level programmable signal routing and may be used to provide arbitrary signal swapping between chips. It opens up the possibilities of programmable system hardware. It is characterized by the need to provide a large number of 1:1 pin connections which are statically configured, i.e., the pin-to-pin paths do not need to change dynamically in response to control inputs.

Programmable Data Path (PDP)

This application area includes system data path transceiver, MUX and latch functions. With today’s 32- and 64-bit microprocessor buses, but standard data path glue components still relegated primarily to eight bits, PCBs are frequently crammed with a dozen or more data path glue chips that use valuable real estate. Many of these applications consist of “on-board” bus and memory interfaces that do not require the very high drive of standard glue functions but can benefit from higher integration. Therefore, there is a need for a flexible means to integrate these on-board data path functions in an analogous way to programmable logic’s solution to control logic integration. Lattice’s CPLDs make an ideal control logic complement to the ispGDXVA in-system programmable data path devices as shown below.

Figure 4. ispGDXVA Complements Lattice CPLDs

Address

Inputs

(from µP)

Control

Inputs

(from µP)

ADVANCED

Data Path

Bus #1

Programmable Switch Replacement (PSR)

Includes solid-state replacement and integration of me-

chanical DIP Switch and jumper functions. Through

in-system programming, pins of the ispGDXVA devices

can be driven to HIGH or LOW logic levels to emulate the

traditional device outputs. PSR functions do not require

any input pin connections.

These applications actually require somewhat different

silicon features. PRSI functions require that the device

support arbitrary signal routing on-chip between any two

pins with no routing restrictions. The routing connections

are static (determined at programming time) and each

input-to-output path operates independently. As a result,

there is little need for dynamic signal controls (OE,

clocks, etc.). Because the ispGDXVA device will inter-

face with control logic outputs from other components

(such as ispLSI or ispMACH) on the board (which fre-

quently change late in the design process as control logic

is finalized), there must be no restrictions on pin-to-pin

signal routing for this type of application.

PDP functions, on the other hand, require the ability to

dynamically switch signal routing (MUXing) as well as

latch and tri-state output signals. As a result, the pro-

grammable interconnect is used to define

routes that are then selected dynamically by control

signals from an external MPU or control logic. These

functions are usually formulated early in the conceptual

design of a product. The data path requirements are

driven by the microprocessor, bus and memory architec-

ture defined for the system. This part of the design is the

earliest portion of the system design frozen, and will not

usually change late in the design because the result

would be total system and PCB redesign. As a result, the

ability to accommodate

routing is not a strong requirement as long as the designer

has the ability to define his functions with a reasonable

degree of freedom initially.

arbitrary

any pin-to-any pin re-

possible

signal

ispMACH

System

Clock(s)

ispLSI/

Device

Control

Outputs

Buffers / RegistersState Machines

ispGDXVA

Device

Buffers / RegistersDecoders

Data Path

Bus #2

ISP/JTAG

Interface

Configuration

(Switch) Outputs

As a result, the ispGDXVA architecture has been defined

to support PSR and PRSI applications (including bidirec-

tional paths) with no restrictions, while PDP applications

(using dynamic MUXing) are supported with a minimal

number of restrictions as described below. In this way,

speed and cost can be optimized and the devices can still

support the system designer’s needs.

The following diagrams illustrate several ispGDXVA ap-

plications.

Applications (Continued)

Specifications ispGDX240VA

Figure 5. Address Demultiplex/Data Buffering

XCVR

Control Bus

MUXed Address Data Bus

I/OA I/OB

OEA OEB

Address

Latch

CLK

Buffered Data

To Memory/ Peripherals

Address

Figure 6. Data Bus Byte Swapper

XCVR

I/OA

I/OB

OEA OEB

XCVR

I/OA I/OB

OEA OEB

D0-7

XCVR

I/OA I/OB

OEA OEB

XCVR

I/OA I/OB

OEA OEB

Control Bus

D0-7

Data Bus A

D8-15 D8-15

Data Bus B

Designing with the ispGDXVA

As mentioned earlier, this architecture satisfies the PRSI

class of applications without restrictions: any I/O pin as a

single input or bidirectional can drive any other I/O pin as

output.

For the case of PDP applications, the designer does have

to take into consideration the limitations on pins that can

be used as control (MUX0, MUX1, OE, CLK) or data

(MUXA-D) inputs. The restrictions on control inputs are

not likely to cause any major design issues because the

input possibilities span 25% of the total pins.

The MUXA-D input partitioning requires that designers

consciously assign pinouts so that MUX inputs are in the

appropriate, disjoint groups. For example, since the

MUXA group includes I/O A0-39 (240 I/O device), it is not

possible to use I/O A0 and I/O A9 in the same MUX

function. As previously discussed, data path functions

will be assigned early in the design process and these

restrictions are reasonable in order to optimize speed

and cost.

User Electronic Signature

The ispGDXVA Family includes dedicated User Elec-

tronic Signature (UES) E2CMOS storage to allow users

to code design-specific information into the devices to

identify particular manufacturing dates, code revisions,

or the like. The UES information is accessible through

the boundary scan programming port via a specific com-

mand. This information can be read even when the

security cell is programmed.

Figure 7. Four-Port Memory Interface

Bus 4

Bus 3

Bus 2

Bus 1

Note: All OE and SEL lines driven by external arbiter logic (not shown).

ADVANCED

4-to-1

16-Bit MUX

Bidirectional

Port #1 OE1

Port #2 OE2

Port #3 OE3

Port #4 OE4

Memory

Port

OEM

SEL0

SEL1

To Memory

Security

The ispGDXVA Family includes a security feature that

prevents reading the device program once set. Even

when set, it does not inhibit reading the UES or device ID

code. It can be erased only via a device bulk erase.

Specifications ispGDX240VA

Absolute Maximum Ratings

Supply Voltage Vcc................................. -0.5 to +5.4V

Input Voltage Applied............................... -0.5 to +5.6V

Off-State Output Voltage Applied ............ -0.5 to +5.6V

Storage Temperature................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (TJ) with Power Applied ... 150 °C

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional

operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).

2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.

1,2

DC Recommended Operating Conditions

MIN. MAX. UNITS

3.00

3.00 3.60 V

2.3

3.60

Table 2-0005/gdxva

V V

CCIO

SYMBOL

PARAMETER

Supply Voltage

I/O Reference Voltage

Commercial Industrial

= 0°C to +70°C

= -40°C to +85°C

Capacitance (TA=25oC, f=1.0 MHz)

SYMBOL

I/O Capacitance Dedicated Clock Capacitance

PARAMETER PACKAGE TYPE

TQFP

UNITSTYPICAL TEST CONDITIONS

7TQFP 8

pf pf

V = 3.3V, V = 2.0V

CC Y

I/O

Table 2-0006/gdxva

Erase/Reprogram Specifications

PARAMETER MINIMUM MAXIMUM UNITS

Erase/Reprogram Cycles 10,000 — Cycles

ADVANCED

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