Lattice Semiconductor Corporation ISPGDS22-7P, ISPGDS22-7J, ISPGDS18-7P, ISPGDS14-7P, ISPGDS14-7J Datasheet
ispGDS22/18/14
Features
• HIGH-SPEED SWITCH MA TRIX
— 7.5 ns Maximum Propagation Delay
— Typical Icc = 25 mA
— UltraMOS
• FLEXIBLE I/O MACROCELL
— Any I/O Pin Can be Input, Output, or Fixed
TTL High or Low
— Programmable Output Polarity
— Multiple Outputs Can be Driven by One Input
• IN-SYSTEM PROGRAMMABLE (5-VOL T ONLY)
— Programming Time of Less Than One Second
— 4-Wire Programming Interface
— Minimum 10,000 Program/Erase Cycles
2
CELL TECHNOLOGY
•E
— Non-Volatile Reprogrammable Cells
— 100% Tested/100% Y ields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• APPLICATIONS INCLUDE:
— Software-Driven Hardware Configuration
— Multiple DIP Switch Replacement
— Software Configuration of Add-In Boards
— Configurable Addressing of I/O Boards
— Multiple Clock Source Selection
— Cross-Matrix Switch
• ELECTRONIC SIGNA TURE FOR IDENTIFICATION
®
Advanced CMOS Technology
in-system programmable
Generic Digital Switch
Functional Block Diagram (ispGDS22)
I/O Cell
A0
I/O Cell
A1
I/O Cell
A2
I/O Cell
A3
I/O Cell
A4
A5
Bank A
A6
A7
A8
A9
A10
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
Switch
Matrix
PROGRAMMABLE
SWITCH MATRIX
I/O Cell
I/O Cell
I/O Cell
I/O Cell
B9B8B7
B10
Closed only when C0=1 and C1=0
4:1 MUX
Vcc
0 1
1 0
1 1
0 0
C2
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
B6B5B4B3B2B1B0
C1
Bank B
C0
TM
I/O Cell
Description
2
The Lattice Semiconductor ispGDS™ family is an ideal solution
for reconfiguring system signal routing or replacing DIP switches
used for feature selection. With today’s demands for customer
ease of use, there is a need for hardware which is easily
reconfigured electronically without dismantling the system. The
ispGDS devices address this challenge by replacing conventional
switches with a software configurable solution. Since each I/O pin
can be set to an independent logic level, the ispGDS devices can
replace most DIP switch functions with about half the pin count,
and without the need for additional pull-up resistors. In addition
to DIP switch replacement, the ispGDS devices are useful as
signal routing cross-matrix switches. This is the only non-volatile
device on the market which can provide this flexibility .
With a maximum tpd of 7.5ns, and a typical active Icc of only 25
mA, these devices provide maximum performance at very low
power levels. The ispGDS devices may be programmed in-system, using 5 volt only signals, through a simple 4-wire programming interface. The ispGDS devices are manufactured using
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
Lattice Semiconductor’s advanced non-volatile E
which combines CMOS with Electrically Erasable (E
technology . High speed erase times (<100ms) allow the devices
to be reprogrammed quickly and efficiently .
Each I/O macrocell can be configured as an input, an inverting
or non-inverting output, or a fixed TTL high or low output. Any
I/O pin can be driven by any other I/O pin in the opposite bank.
A single input can drive one or more outputs in the opposite bank,
allowing a signal (such as a clock) to be distributed to multiple destinations on the board, under software control. The I/Os accept
and drive TTL voltage levels.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
Lattice Semiconductor is able to deliver 100% field programmability and functionality of all Lattice Semiconductor
addition, 10,000 erase/write cycles and data retention in excess
of 20 years are specified.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. July 1997
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268--8037; http://www.latticesemi.com
ispgds_02
CMOS process
2
) floating gate
products. In
Specifications ispGDS
ispGDS Ordering Information
Commercial Grade Specifications
Matrix Size I/O Pins Tpd (ns) Isb (mA) Icc (mA) Ordering # Package
11 x 11 22 7.5 25 40
9 x 9 18 7.5 25 40 ispGDS18-7P 24-Pin Plastic DIP
7 x 7 14 7.5 25 40
Part Number Description
ispGDS22-7P 28-Pin Plastic DIP
ispGDS22-7J 28-Lead PLCC
ispGDS14-7P 20-Pin Plastic DIP
ispGDS14-7J 20-Lead PLCC
ispGDS22
ispGDS18
ispGDS14
Device Name
Speed (ns)
XXXXXXXX XX X X
_
Package
Blank = CommercialGrade
P = Plastic DIP
J = PLCC
2
K
Pin Configuration
Specifications ispGDS
A0
A1
A2
SDI
A3
A4
Vcc
A5
A6
A7
MODE
A8
A9
A10
28-Pin DIP
128
B0
B1
B2
SDO
B3
ispGDS
21
B4
B5
GND
B6
B7
SCL
B8
B9
B10
22
7
14 15
A0
A1
A2
SDI
A3
Vcc
A4
A5
MODE
A6
A7
A8
24-Pin DIP 20-Pin DIP
1
ispGDS
18
6
12
24
18
13
B0
B1
B2
SDO
B3
B4
GND
B5
SCLK
B6
B7
B8
SDI
Vcc
MODE
A0
A1
A2
A3
A4
A5
A6
1
ispGDS
5
14
10
20
15
11
B0
B1
B2
SDO
B3
GND
SCLK
B4
B5
B6
A3
A4
Vcc
A5
A6
A7
MODE
28-Pin PLCC 20-Pin PLCC
SDIA2A1
5
7
ispGDS22
9
11
12 14 16 18
A8
A9
A0
B0
B1
B2
2
28426
25
SDO
B3
B4
23
B5
GND
21
B6
19
B7
B9
A10
B10
B8
SCLK
4
SDI
Vcc
ispGDS14
6
A3
MODE
8
A4
3
A0A1A2
2
10
B6A6A5 B5 B4
B0
B1
20
18
B2
SDO
16
B3
GND
SCLK
14
12
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