Lattice Semiconductor Corporation GAL6001B-30LP, GAL6001B-30LJ Datasheet

GAL6001

High Performance E2CMOS FPLA

Generic Array Logic™

Features

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 30ns Maximum Propagation Delay
— 27MHz Maximum Frequency
— 12ns Maximum Clock to Output Delay
— TTL Compatible 16mA Outputs
— UltraMOS

• LOW POWER CMOS
— 90mA Typical Icc

2

CELL TECHNOLOGY

• E
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Y ields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention

• UNPRECEDENTED FUNCTIONAL DENSITY
— 78 x 64 x 36 FPLA Architecture
— 10 Output Logic Macrocells
— 8 Buried Logic Macrocells
— 20 Input and I/O Logic Macrocells

• HIGH-LEVEL DESIGN FLEXIBILITY
— Asynchronous or Synchronous Clocking
— Separate State Register and Input Clock Pins
— Functional Superset of Existing 24-pin PAL

and FPLA Devices

®

Advanced CMOS Technology

®

Functional Block Diagram

ICLK

INPUT

CLOCK

2

INPUTS

2-11

11

{

ILMC

OUTPUT
ENABLE

RESET

D

E

0

7

BLMC

AND

OR

D

E

Macrocell Names

ILMC INPUT LOGIC MACROCELL
IOLMC I/O LOGIC MACROCELL
BLMC BURIED LOGIC MACROCELL
OLMC OUTPUT LOGIC MACROCELL

14

23

OLMC

OCLK

14

23

IOLMC

OUTPUTS

{

14 - 23

OUTPUT

CLOCK

• APPLICATIONS INCLUDE:
— Sequencers

Pin Names

— State Machine Control
— Multiple PLD Device Integration

Description

- I

I

0

INPUT I/O/Q BIDIRECTIONAL

10

ICLK INPUT CLOCK V

POWER (+5)

CC

OCLK OUTPUT CLOCK GND GROUND

Using a high performance E2CMOS technology, Lattice
Semiconductor has produced a next-generation programmable
logic device, the GAL6001. Having an FPLA architecture, known
for its superior flexibility in state-machine design, the GAL6001
offers a high degree of functional integration and flexibility in a 24­pin, 300-mil package.

The GAL6001 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In
addition, there are 10 Input Logic Macrocells (ILMC) and 10
I/O Logic Macrocells (IOLMC). T wo clock inputs are provided for
independent control of the input and output macrocells.

Advanced features that simplify programming and reduce test time,
coupled with E

2

CMOS reprogrammable cells, enable 100% AC, DC,
programmability , and functionality testing of each GAL6001 during
manufacture. As a result, Lattice Semiconductor delivers 100% field
programmability and functionality of all GAL products. In addition,
100 erase/write cycles and data retention in excess of 20 years are
specified.

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. July 1997
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

6001_02

Pin Configuration

PLCC

NC

I/ICLK

I

I

228

4

5

I
I
I

7

NC

1

GAL6001

I

9

T op View

I

11

I

12 14 16 18

I

I

GND

NC

Vcc

OCLK

I/O/Q

I/O/Q

DIP

1

I/ICLK

I

GND

I
I

GAL

I

6001

6

I
I

I
I
I

I

12

I/O/Q

26

25

I/O/Q
I/O/Q

23

I/O/Q
NC

21

I/O/Q
I/O/Q

19

I/O/Q

I/O/Q

Vcc

24

I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q

18

I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
OCLK

13

GAL6001 Ordering Information

Commercial Grade Specifications

)sn(dpT)zHM(xamF)Am(ccI#gniredrOegakcaP

0372051PL03-B1006LAGPIDcitsalPniP-42

051JL03-B1006LAGCCLPdaeL-82

Part Number Description

Specifications GAL6001

GAL6001B

Device Name

Speed (ns)

PowerL = Low Power

XXXXXXXX XX X X X

_

Grade

Package

Blank = Commercial

P = Plastic DIP
J = PLCC

2

Specifications GAL6001

Input Logic Macrocell (ILMC) and I/O Logic Macrocell (IOLMC)

The GAL6001 features two configurable input sections. The ILMC
section corresponds to the dedicated input pins (2-11) and the
IOLMC to the I/O pins (14-23). Each input section is configurable
as a block for asynchronous, latched, or registered inputs. Pin 1
(ICLK) is used as an enable input for latched macrocells or as a
clock input for registered macrocells. Configurable input blocks

provide system designers with unparalleled design flexibility . With
the GAL6001, external registers and latches are not necessary .

Both the ILMC and the IOLMC are block configurable. However,
the ILMC can be configured independently of the IOLMC. The three
valid macrocell configurations are shown in the macrocell equivalent
diagrams on the following pages.

Output Logic Macrocell (OLMC) and Buried Logic Macrocell (BLMC)

The outputs of the OR array feed two groups of macrocells. One
group of eight macrocells is buried; its outputs feed back directly
into the AND array rather than to device pins. These cells are called
the Buried Logic Macrocells (BLMC), and are useful for building
state machines. The second group of macrocells consists of 10
cells whose outputs, in addition to feeding back into the AND ar­ray, are available at the device pins. Cells in this group are known
as Output Logic Macrocells (OLMC).

The Output and Buried Logic Macrocells are configurable on a
macrocell by macrocell basis. Buried and Output Logic Macrocells
may be set to one of three configurations: combinatorial, D-type
register with sum term (asynchronous) clock, or D/E-type register.
Output macrocells always have I/O capability, with directional control
provided by the 10 output enable (OE) product terms. Additionally,
the polarity of each OLMC output is selected through the “D” XOR.
Polarity selection is available for BLMCs, since both the true and
complemented forms of their outputs are available in the AND array .
Polarity of all “E” sum terms is selected through the “E” XOR.

When the macrocell is configured as a D/E type register, it is clocked
from the common OCLK and the register clock enable input is con­trolled by the associated “E” sum term. This configuration is useful
for building counters and state-machines with state hold functions.

When the macrocell is configured as a D-type register with a sum
term clock, the register is always enabled and its “E” sum term is
routed directly to the clock input. This permits asynchronous pro­grammable clocking, selected on a register-by-register basis.

Registers in both the Output and Buried Logic Macrocells feature
a common RESET product term. This active high product term
allows the registers to be asynchronously reset. Registers are reset
to a logic zero. If connected to an output pin, a logic one will oc­cur because of the inverting output buffer .

There are two possible feedback paths from each OLMC. The first
path is directly from the OLMC (this feedback is before the output
buffer and always present). When the OLMC is used as an out­put, the second feedback path is through the IOLMC. With this dual
feedback arrangement, the OLMC can be permanently buried (the
associated OLMC pin is an input), or dynamically buried with the
use of the output enable product term.

The D/E registers used in this device offer the designer the ultimate
in flexibility and utility. The D/E register architecture can emulate
RS-, JK-, and T-type registers with the same ef ficiency as a dedi­cated RS-, JK-, or T -register.

The three macrocell configurations are shown in the macrocell
equivalent diagrams on the following pages.

3

Y

ILMC and IOLMC Configurations

ICLK

LATCH

E

D

Specifications GAL6001

Q

MUX

0 0

INPUT
or I/O

REG.

10

Q

D

ILMC/IOLMC

Generic Logic Block Diagram

ILMC (Input Logic Macrocell)
JEDEC Fuse Numbers

INVALID

0 1

10

1 0

1 1

LATCH ISYN

IOLMC (I/O Logic Macrocell)
JEDEC Fuse Numbers

AND
ARRA

ISYN LATCH

8218 8219

ISYN LATCH

8220 8221

4

OLMC and BLMC Configurations

RESET

Specifications GAL6001

OE
PRODUCT
TERM

AND

ARRAY

IOLMC

OLMC ONLY

XORD(i)

D

Vcc

XORE(i)

E

CKS(i)

OCLK

OLMC (Output Logic Macrocell)

JEDEC Fuse Numbers

MUX

1

0

OSYN(i)

MUX

0

R

D

Q

E

1

MUX

0

1

OLMC/BLMC

Generic Logic Block Diagram

I/O

OLMC ONLY

BLMC (Buried Logic Macrocell)

JEDEC Fuse Numbers

OLMC OCLK OSYN XORE XORD

0 8178 8179 8180 8181
1 8182 8183 8184 8185
2 8186 8187 8188 8189
3 8190 8191 8192 8193
4 8194 8195 8196 8197
5 8198 8199 8200 8201
6 8202 8203 8204 8205
7 8206 8207 8208 8209
8 8210 8211 8212 8213
9 8214 8215 8216 8217

BLMC OCLK OSYN XORE

7 8175 8176 8177
6 8172 8173 8174
5 8169 8170 8171
4 8166 8167 8168
3 8163 8164 8165
2 8160 8161 8162
1 8157 8158 8159
0 8154 8155 8156

5