Lattice Semiconductor Corporation GAL20XV10B-20LP, GAL20XV10B-20LJ, GAL20XV10B-15LP, GAL20XV10B-15LJ, GAL20XV10B-10LP Datasheet

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GAL20XV10

High-Speed E2CMOS PLD

Generic Array Logic™

Features

• HIGH PERFORMANCE E2CMOS ® TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax = 100 MHz — 7 ns Maximum from Clock Input to Data Output — TTL Compatible 16 mA Outputs — UltraMOS® Advanced CMOS Technology

• 50% to 75% REDUCTION IN POWER FROM BIPOLAR — 90mA Maximum Icc — 75mA Typical Icc

• ACTIVE PULL-UPS ON ALL PINS

• E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100 ms) — 20 Year Data Retention

• TEN OUTPUT LOGIC MACROCELLS — XOR Gate Capability on all Outputs — Full Function and Parametric Compatibility with

PAL12L10, 20L10, 20X10, 20X8, 20X4

— Registered or Combinatorial with Polarity

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

• APPLICATIONS INCLUDE: — High Speed Counters — Graphics Processing — Comparators

• ELECTRONIC SIGNA TURE FOR IDENTIFICATION

Functional Block Diagram

I/CLK

(40 X 40)

AND-ARRAY

PROGRAMMABLE

OLMC

I/O/Q

Description

The GAL20XV10 combines a high performance CMOS process with electrically erasable (E2) floating gate technology to provide

Pin Configuration

I/OE

the highest speed Exclusive-OR PLD available in the market. At

I I I I I

I I

I I I

DIP

GAL

20XV10

Vcc

I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q

I/OE

90mA maximum Icc (75mA typical Icc), the GAL20XV10 provides a substantial savings in power when compared to bipolar counterparts. E2CMOS technology offers high speed (<100ms) erase

PLCC

I/CLK

times providing the ability to reprogram, reconfigure or test the devices quickly and efficiently .

The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL20XV10 are the PAL® architectures listed in the macrocell description section of this document. The GAL20XV10 is capable of emulating these PAL architectures with full function and parametric compatibility.

Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacturing. As a result, Lattice

I I I

GAL20XV10

9 I I

T op View

14 16 18

I/CLK

GND

I/O/Q

Vcc

I/O/Q I/O/Q

I/O/Q NC I/O/Q

I/O/Q

I/OE

I/O/Q

Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. July 1997 Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com

20xv10_02

GND

GAL20XV10 Ordering Information

Commercial Grade Specifications

)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP

016709PL01-B01VX02LAGPIDcitsalPniP-42

JL01-B01VX02LAGCCLPdaeL-82

518809PL51-B01VX02LAGPIDcitsalPniP-42

JL51-B01VX02LAGCCLPdaeL-82

02010109PL02-B01VX02LAGPIDcitsalPniP-42

JL02-B01VX02LAGCCLPdaeL-82

Part Number Description

Specifications GAL20XV10

GAL20XV10B

Device Name

Speed (ns)

PowerL = Low Power

XXXXXXXX XX X X X

Grade

Package

Blank = Commercial

P = Plastic DIP J = PLCC

Output Logic Macrocell (OLMC)

Specifications GAL20XV10

The following discussion pertains to configuring the Output Logic Macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user.

The GAL20XV10 has two global architecture configurations that allow it to emulate P AL architectures. The Input mode emulates combinatorial PAL devices, with the I/CLK and I/OE pins used as inputs. The Feedback mode emulates registered P AL devices with the I/CLK pin used as the register clock and the I/OE pin as an output enable for all registers. The following is a list of P AL architectures that the GAL20XV10 can emulate. It also shows the global architecture mode used to emulate the P AL architecture.

P AL Architectures Emulated by

GAL20XV10

PAL12L10 PAL20L10 PAL20X10 PAL20X8 PAL20X4

INPUT MODE

The Input mode architecture is defined when the global architecture bit SYN = 1. In this mode, the I/CLK pin becomes an input to the AND array and also provides the clock source for all registers. The I/OE pin becomes an input into the AND array and provides the output enable control for any macrocell configured as an Exclusive-OR function. Feedback into the AND array is provided from macrocells 2 through 9 only. In this mode, macrocells 1 and 10 have no feedback into the AND array.

FEEDBACK MODE

The Feedback mode architecture is defined when the global architecture bit SYN = 0. In this mode the I/CLK pin becomes a dedicated clock source for all registers. The I/OE pin is a dedicated output enable control for any macrocell configured as an Exclusive-OR function. The I/CLK and I/OE pins are not available to the AND array in this mode. Feedback into the AND array is provided on all macrocells 1 through 10.

FEATURES

Each Output Logic Macrocell has four possible logic function configurations controlled by architecture control bits AC0 and AC1. Four product terms are fed into each macrocell.

GAL20XV10 Global

OLMC Mode

Input Mode

Input Mode Feedback Mode Feedback Mode Feedback Mode

Exclusive-OR macrocells. In Feedback mode, the state of the register is available to the AND array via an internal feedback path on all macrocells. In Input mode, the state of the register is available to the AND array via an internal feedback path on macrocells 2 through 9 only , macrocells 1 and 10 have no feedback into the AND array.

REGISTERED CONFIGURATION

The Macrocell is set to Registered configuration when AC0 = 1 and AC1 = 0. Three of the four product terms are used as sum-ofproduct terms for the D input of the register. The inverting output buffer is enabled by the fourth product term. The output is enabled while this product term is true. The XOR bit controls the polarity of the output. The register is clocked by the low-to-high transition of the I/CLK. In Feedback mode, the state of the register is available to the AND array via an internal feedback path on all macrocells. In Input mode, the state of the register is available to the AND array via an internal feedback path on macrocells 2 through 9 only, macrocells 1 and 10 have no feedback into the AND array .

XOR COMBINA TORIAL CONFIGURATION

The Macrocell is set to the Exclusive-OR Combinatorial configuration when AC0 = 0 and AC1 = 1. The four product terms are segmented into two OR-sums of two product terms each, which are then combined by an Exclusive-OR gate and fed to an output buffer. The inverting output buffer is enabled by the I/OE pin, which is an active low output enable that is common to all XOR macrocells. In Feedback mode, the state of the I/O pin is available to the AND array via an internal feedback path on all macrocells. In Input mode, the state of the I/O pin is available to the AND array via an input buf fer path on macrocells 2 through 9 only , macrocells 1 and 10 have no input into the AND array.

COMBINAT ORIAL CONFIGURATION

The Macrocell is set to Combinatorial mode when AC0 = 1 and AC1 = 1. Three of the four product terms are used as sum-ofproduct terms for the combinatorial output. The XOR bit controls the polarity of the output. The inverting output buffer is enabled by the fourth product term. The output is enabled while this product term is true. In Feedback mode, the state of the I/O pin is available to the AND array via an internal feedback path on all macrocells. In Input mode, the state of the I/O pin is available to the AND array via an input buffer path on macrocells 2 through 9 only , macrocells 1 and 10 have no input into the AND array.

XOR REGISTERED CONFIGURA TION

The Macrocell is set to the Exclusive-OR Registered configuration when AC0 = 0 and AC1 = 0. The four product terms are segmented into two OR-sums of two product terms each, which are then combined by an Exclusive-OR gate and fed into a D-type register. The register is clocked by the low-to-high transition of the I/CLK pin. The inverting output buffer is enabled by the I/OE pin, which is an active low output enable common to all

Input Mode

CLK

XOR

Specifications GAL20XV10

XOR Registered Configuration

- SYN = 1.

- AC0 = 0.

Registered Configuration

- AC1 = 0.

- OLMC 1 and OLMC10 do not have the feedback path.

- Pin 1(2) can be CLK and/or Input.

- Pin 13(16) can be OE and/or Input.

- SYN = 1.

- AC0 = 1.

- AC1 = 0.

- XOR = 1 defines Active Low Output.

- XOR = 0 defines Active High Output.

- OLMC 1 and OLMC10 do not have the feedback path.

- Pin 1(2) can be CLK and/or Input.

- OE controlled by product term.

XOR

XOR Combinatorial Configuration

- SYN = 1.

- AC0 = 0.

- AC1 = 1.

- OLMC 1 and OLMC10 do not have the feedback path.

- Pin 13(16) can be OE and/or Input.

Combinatorial Configuration

- SYN = 1.

- AC0 = 1.

- AC1 = 1.

- XOR = 1 defines Active Low Output.

- XOR = 0 defines Active High Output.

- OLMC 1 and OLMC10 do not have the feedback path.

- OE controlled by product term.

Input Mode Logic Diagram

1(2)

120

2(3)

160 280

3(4)

Specifications GAL20XV10

DIP (PLCC) Package Pinouts

2812 16 20 24 32 36048

OLMC

XOR - 1600 AC0 - 1610 AC1 - 1620

OLMC

XOR - 1601 AC0 - 1611 AC1 - 1621

23(27)

22(26)

4(5)

5(6)

6(7)

7(9)

8(10)

9(11)

320 440

480 600

640 760

800 920

960

1080

1120 1240

OLMC

XOR - 1602 AC0 - 1612 AC1 - 1622

OLMC

XOR - 1603 AC0 - 1613 AC1 - 1623

OLMC

XOR - 1604 AC0 - 1614 AC1 - 1624

OLMC

XOR - 1605 AC0 - 1615 AC1 - 1625

OLMC

XOR - 1606 AC0 - 1616 AC1 - 1626

OLMC

XOR - 1607 AC0 - 1617 AC1 - 1627

21(25)

20(24)

19(23)

18(21)

17(20)

16(19)

10(12)

11(13)

1280 1400

1440 1560

40-USER ELECTRONIC SIGNA TURE FUSES

1631, 1632, .... .... 1669, 1670

Byte4 Byte3 .... .... Byte1 Byte0

OLMC

XOR - 1608 AC0 - 1618 AC1 - 1628

OLMC

XOR - 1609 AC0 - 1619 AC1 - 1629

15(18)

14(17)

13(16)

SYN - 1630

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