Lattice Semiconductor Corporation GAL20V8ZD-15QP, GAL20V8ZD-15QJ, GAL20V8ZD-12QP, GAL20V8ZD-12QJ, GAL20V8Z-15QP Datasheet

GAL20V8Z

K

I

I
I/O/Q
I/O/Q
I/O/Q
I/O/Q

I/O/Q
I/O/Q

I/O/Q
I/O/Q
I
I/OE

I/CLK

I
I

I/DPP

I

Vcc

I
I

I
I
I

GND

1

12

13

24

18

6

2
3
4
5

7

8
9
10
11 14

15

16

17

19

20

21

22

23

GAL20V8ZD

Zero Power E2CMOS PLD

Features

• ZERO POWER E2CMOS TECHNOLOGY

• HIGH PERFORMANCE E

•E

• EIGHT OUTPUT LOGIC MACROCELLS

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

• APPLICATIONS INCLUDE:

• ELECTRONIC SIGNA TURE FOR IDENTIFICATION

µA Standby Current

— 100
— Input Transition Detection on GAL20V8Z
— Dedicated Power-down Pin on GAL20V8ZD
— Input and Output Latching During Power Down

2

CMOS TECHNOLOGY
— 12 ns Maximum Propagation Delay
— Fmax = 83.3 MHz
— 8 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Output Drive
— UltraMOS

2

CELL TECHNOLOGY

®

Advanced CMOS Technology

— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Y ields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention

— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Architecturally Similar to Standard GAL20V8

— 100% Functional Testability

— Battery Powered Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing

Functional Block Diagram

I/CLK

I

I

I/DPP

I

I

(64 X 40)

I

AND-ARRAY

PROGRAMMABLE

I

I

I

I

8

8

8

8

8

8

8

8

IMUX

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

IMUX

I

CLK

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

OE

I
I/OE

Description

The GAL20V8Z and GAL20V8ZD, at 100 µA standby current and

Pin Configuration

DIP

12ns propagation delay provides the highest speed and lowest
power combination PLD available in the market. The
GAL20V8Z/ZD is manufactured using Lattice Semiconductor's ad­vanced zero power E

2

CMOS process, which combines CMOS with

Electrically Erasable (E2) floating gate technology .

I/DPP

NC

5

I
I

7

I

9

I
I

11

The GAL20V8Z uses Input Transition Detection (ITD) to put the
device in standby mode and is capable of emulating the full func­tionality of the standard GAL20V8. The GAL20V8ZD utilizes a
dedicated power-down pin (DPP) to put the device in standby mode.
It has 19 inputs available to the AND array.

Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function­ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. December 1997
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

20v8zzd_03

1

PLCC

I

4

NC

I

I/CL

228

Vcc

I

GAL20V8Z

GAL20V8ZD

T op View

14 16

12 18

I

I

GND

NC

I

I/OE

I/O/Q

26

25

I/O/Q
I/O/Q

23

I/O/Q
NC

I/O/Q

21

I/O/Q
I/O/Q

19

I/O/Q

GAL

20V8Z

20V8ZD

Specifications GAL20V8Z

GAL20V8ZD

GAL20V8Z/ZD Ordering Information

GAL20V8Z: Commercial Grade Specifications

Tpd (ns) T su (ns) T co (ns) Icc (mA) ISB (µA) Ordering # Package

12 10 8 55 100 GAL20V8Z-12QP 24-Pin Plastic DIP

55 100 GAL20V8Z-12QJ 28-Lead PLCC

15 15 10 55 100 GAL20V8Z-15QP 24-Pin Plastic DIP

55 100 GAL20V8Z-15QJ 28-Lead PLCC

GAL20V8ZD: Commercial Grade Specifications

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) ISB (µA) Ordering # Package

12 10 8 55 100 GAL20V8ZD-12QP 24-Pin Plastic DIP

55 100 GAL20V8ZD-12QJ 28-Lead PLCC

15 15 10 55 100 GAL20V8ZD-15QP 24-Pin Plastic DIP

Part Number Description

Device Name

GAL20V8Z (Zero Power ITD)

GAL20V8ZD (Zero Power DPP)

Speed (ns)

Active Power

Q = Quarter Power

55 100 GAL20V8ZD-15QJ 28-Lead PLCC

XXXXXXXX XX X X X

_

Grade

Blank = Commercial

Package

P = Plastic DIP
J = PLCC

2

Output Logic Macrocell (OLMC)

Specifications GAL20V8Z

GAL20V8ZD

The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom­plished by development software/hardware and is completely trans­parent to the user.

There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
is illustrated in the following pages. T wo global bits, SYN and AC0,

Compiler Support for OLMC

Software compilers support the three different global OLMC modes
as different device types. Most compilers also have the ability to
automatically select the device type, generally based on the register
usage and output enable (OE) usage. Register usage on the device
forces the software to choose the registered mode. All combina­torial outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose
the simple mode only when all outputs are dedicated combinatorial
without OE control. For further details, refer to the compiler soft­ware manuals.

When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.

In registered mode pin 1(2) and pin 13(16) are permanently con-
figured as clock and output enable, respectively. These pins cannot
be configured as dedicated inputs in the registered mode.

control the mode configuration for all macrocells. The XOR bit of
each macrocell controls the polarity of the output in any of the three
modes, while the AC1 bit of each of the macrocells controls the in­put/output configuration. These two global and 16 individual archi­tecture bits define all possible configurations in a GAL20V8Z/ZD.
The information given on these architecture bits is only to give a
better understanding of the device. Compiler software will trans­parently set these architecture bits from the pin definitions, so the
user should not need to directly manipulate these architecture bits.

In complex mode pin 1(2) and pin 13(16) become dedicated in-
puts and use the feedback paths of pin 22(26) and pin 15(18) re­spectively . Because of this feedback path usage, pin 22(26) and
pin 15(18) do not have the feedback option in this mode.

In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
18(21) and 19(23)) will not have the feedback option as these pins
are always configured as dedicated combinatorial output.

When using the standard GAL20V8 JEDEC fuse pattern generated
by the logic compilers for the GAL20V8ZD, special attention must
be given to pin 4(5) (DPP) to make sure that it is not used as one
of the functional inputs.

3

Registered Mode

Specifications GAL20V8Z

GAL20V8ZD

In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.

Architecture configurations available in this mode are similar to the
common 20R8 and 20RP4 devices with various permutations of
polarity , I/O and register placement.

All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/Os are possible in this mode.
Dedicated input or output functions can be implemented as sub­sets of the I/O function.

CLK

DQ

XOR

OE

Q

Registered outputs have eight product terms per output. I/Os have
seven product terms per output.

Pin 4(5) is used as dedicated power-down pin on GAL20V8ZD. It
cannot be used as functional input.

The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product T erm Disable (PTD) fuses, are shown
on the logic diagram on the following page.

Registered Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this output configuration.

- Pin 1(2) controls common CLK for the registered
outputs.

- Pin 13(16) controls common OE for the registered
outputs.

- Pin 1(2) & Pin 13(16) are permanently configured as
CLK & OE for registered output configuration.

Combinatorial Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

- AC1=1 defines this output configuration.

- Pin 1(2) & Pin 13(16) are permanently configured as

CLK & OE for registered output configuration.

4

Registered Mode Logic Diagram

Specifications GAL20V8Z

GAL20V8ZD

DIP (PLCC) Package Pinouts

*

1(2)

2(3)

3(4)

4(5)

5(6)

6(7)

7(9)

0000

0280

0320

0600

0640

0920

0960

1240

1280

1560

28

24

201612840

32

2640

36

PTD

23(27)

OLMC

22(26)

XOR-2560
AC1-2632

OLMC

21(25)

XOR-2561
AC1-2633

OLMC

XOR-2562
AC1-2634

OLMC

XOR-2563
AC1-2635

OLMC

XOR-2564
AC1-2636

20(24)

19(23)

18(21)

8(10)

9(11)

10(12)
11(13)

1600

1880

1920

2200

2240

2520

64-USER ELECTRONIC SIGNA TURE FUSES

2568, 2569, .... .... 2630, 2631

Byte7 Byte6 .... .... Byte1 Byte0

MSB LSB

2703

OLMC

17(20)

XOR-2565
AC1-2637

OLMC

16(19)

XOR-2566
AC1-2638

OLMC

15(18)

XOR-2567
AC1-2639

14(17)

OE

13(16)

SYN-2704
AC0-2705

* Note: Input not available on GAL20V8ZD

5

Complex Mode

Specifications GAL20V8Z

GAL20V8ZD

In the Complex mode, macrocells are configured as output only or
I/O functions.

Architecture configurations available in this mode are similar to the
common 20L8 and 20P8 devices with programmable polarity in
each macrocell.

Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 15(18) & 22(26)) do not have input capability .
Designs requiring eight I/Os can be implemented in the Registered
mode.

XOR

All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1(2) and
13(16) are always available as data inputs into the AND array.

Pin 4(5) is used as dedicated power-down pin on GAL20V8ZD. It
cannot be used as functional input.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.

Combinatorial I/O Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1 has no effect on this mode.

- Pin 16(19) through Pin 21(25) are configured to this
function.

Combinatorial Output Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

- XOR=1 defines Active High Output.

- AC1 has no effect on this mode.

- Pin 15(18) and Pin 22(26) are configured to this
function.

6