Lattice Semiconductor Corporation GAL20LV8ZD-25QJ, GAL20LV8ZD-15QJ Datasheet

GAL20LV8ZD

Low V oltage, Zero Power E2CMOS PLD

Generic Array Logic™

Features

• 3.3V LOW VOL TAGE, ZERO POWER OPERATION — JEDEC Compatible 3.3V Interface Standard — Interfaces with Standard 5V TTL Devices

µA Typical Standby Current (100µA Max.)

—50 — 45mA Typical Active Current (55mA Max.) — Dedicated Power-down Pin

• HIGH PERFORMANCE E — TTL Compatible Balanced 8 mA Output Drive — 15 ns Maximum Propagation Delay — Fmax = 62.5 MHz — 10 ns Maximum from Clock Input to Data Output — UltraMOS

CELL TECHNOLOGY

•E

Advanced CMOS Technology

— Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Y ields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention

• EIGHT OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs — Programmable Output Polarity

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS — 100% Functional Testability

• APPLICATIONS INCLUDE: — Glue Logic for 3.3V Systems — Ideal for Mixed 3.3V and 5V Systems

• ELECTRONIC SIGNA TURE FOR IDENTIFICATION

CMOS TECHNOLOGY

Functional Block Diagram

I/CLK

DPP

(64 X 40)

AND-ARRAY

PROGRAMMABLE

IMUX

OLMC

IMUX

CLK

I/O/Q

I I/OE

Description

The GAL20LV8ZD, at 100 µA standby current and 15ns propagation delay provides the highest speed low-voltage PLD available in the market. The GAL20LV8ZD is manufactured using Lattice Semiconductor's advanced 3.3V E bines CMOS with Electrically Erasable (E2) floating gate technology.

The GAL20L V8ZD utilizes a dedicated power-down pin (DPP) to put the device into standby mode. It has 19 inputs available to the AND array and is capable of interfacing with both 3.3V and standard 5V devices.

Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

CMOS process, which com-

Pin Configuration

DPP

GAL20LV8ZD

9 I I

12 14 16 18

PLCC

I/CLK

228

T op V iew

GND

Vcc

I/OE

I/O/Q

I/O/Q I/O/Q

I/O/Q NC

I/O/Q I/O/Q

I/O/Q

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. December 1997 Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

20lv8zd_03

Specifications GAL20LV8ZD

GAL20LV8ZD Ordering Information

Commercial Grade Specifications

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Isb (µA) Ordering # Package

15 12 10 55 100 GAL20LV8ZD-15QJ 28-Lead PLCC 25 15 15 55 100 GAL20LV8ZD-25QJ 28-Lead PLCC

Part Number Description

GAL20LV8ZD (Zero Power DPP)

Device Name

Speed (ns)

Active Power

Q = Quarter Power

XXXXXXXX XX X X X

Grade

Blank = Commercial

Package

J = PLCC

Output Logic Macrocell (OLMC)

Specifications GAL20LV8ZD

The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user.

There are three global OLMC configuration modes possible: simple, complex, and registered. Details of each of these modes is illustrated in the following pages. T wo global bits, SYN and AC0, control the mode configuration for all macrocells. The XOR bit of

Compiler Support for OLMC

Software compilers support the three different global OLMC modes as different device types. Most compilers also have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. For further details, refer to the compiler software manuals.

When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode.

In registered mode pin 2 and pin 16 are permanently configured as clock and output enable, respectively . These pins cannot be configured as dedicated inputs in the registered mode.

each macrocell controls the polarity of the output in any of the three modes, while the AC1 bit of each of the macrocells controls the input/output configuration. These two global and 16 individual architecture bits define all possible configurations in a GAL20L V8ZD. The information given on these architecture bits is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits.

In complex mode pin 2 and pin 16 become dedicated inputs and use the feedback paths of pin 26 and pin 18 respectively . Because of this feedback path usage, pin 26 and pin 18 do not have the feedback option in this mode.

In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins ( pins 21 and 23) will not have the feedback option as these pins are always configured as dedicated combinatorial output.

When using the standard GAL20V8 JEDEC fuse pattern generated by the logic compilers for the GAL20L V8ZD, special attention must be given to pin 5 (DPP) to make sure that it is not used as one of the functional inputs.

Registered Mode

Specifications GAL20LV8ZD

In the Registered mode, macrocells are configured as dedicated registered outputs or as I/O functions.

Architecture configurations available in this mode are similar to the common 20R8 and 20RP4 devices with various permutations of polarity , I/O and register placement.

All registered macrocells share common clock and output enable control pins. Any macrocell can be configured as registered or I/ O. Up to eight registers or up to eight I/Os are possible in this mode. Dedicated input or output functions can be implemented as subsets of the I/O function.

CLK

XOR

Registered outputs have eight product terms per output. I/Os have seven product terms per output.

Pin 5 is used as dedicated power-down pin on GAL20LV8ZD. It cannot be used as functional input.

The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product T erm Disable (PTD) fuses, are shown on the logic diagram on the following page.

Registered Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this output configuration.

- Pin 2 controls common CLK for the registered outputs.

- Pin 16 controls common OE for the registered outputs.

- Pin 2 & Pin 16 are permanently configured as CLK & OE for registered output configuration.

Combinatorial Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

- AC1=1 defines this output configuration.

- Pin 2 & Pin 16 are permanently configured as

CLK & OE for registered output configuration.

Registered Mode Logic Diagram

Specifications GAL20LV8ZD

PLCC Package Pinout

201612840

0000

0280

0320

2640

PTD

OLMC

XOR-2560 AC1-2632

OLMC

0600

Power

Management

Control

0640

0920

0960

1240

1280

1560

XOR-2561 AC1-2633

OLMC

XOR-2562 AC1-2634

OLMC

XOR-2563 AC1-2635

OLMC

XOR-2564 AC1-2636

12 13

MSB LSB

1600

1880

1920

2200

2240

2520

2703

64-USER ELECTRONIC SIGNATURE FUSES

2568, 2569, .... .... 2630, 2631

Byte7 Byte6 .... .... Byte1 Byte0

OLMC

XOR-2565 AC1-2637

OLMC

XOR-2566 AC1-2638

OLMC

XOR-2567 AC1-2639

SYN-2704 AC0-2705

17 16

Complex Mode

Specifications GAL20LV8ZD

In the Complex mode, macrocells are configured as output only or I/O functions.

Architecture configurations available in this mode are similar to the common 20L8 and 20P8 devices with programmable polarity in each macrocell.

Up to six I/Os are possible in this mode. Dedicated inputs or outputs can be implemented as subsets of the I/O function. The two outer most macrocells (pins 18 & 26) do not have input capability . Designs requiring eight I/Os can be implemented in the Registered mode.

XOR

All macrocells have seven product terms per output. One product term is used for programmable output enable control. Pins 2 and 16 are always available as data inputs into the AND array.

Pin 5 is used as dedicated power-down pin on GAL20L V8ZD. It cannot be used as functional input.

The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page.

Combinatorial I/O Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1 has no effect on this mode.

- Pin 19 through Pin 25 are configured to this function.

Combinatorial Output Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

- AC1 has no effect on this mode.

- Pin 18 and Pin 26 are configured to this function.

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