Lattice Semiconductor Corporation GAL20LV8D-5LJ, GAL20LV8D-3LJ, GAL20LV8D-7LJ Datasheet

New 5V

Tolerant

Inputs on
20LV8D

GAL20LV8

Low V oltage E2CMOS PLD

Generic Array Logic™

Features

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 3.5 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 2.5 ns Maximum from Clock Input to Data Output
— UltraMOS
— TTL-Compatible Balanced 8mA Output Drive

• 3.3V LOW VOL TAGE 20V8 ARCHITECTURE
— JEDEC-Compatible 3.3V Interface Standard
— 5V Compatible Inputs

• ACTIVE PULL-UPS ON ALL PINS

2

CELL TECHNOLOGY

•E
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Y ields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention

• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability

• APPLICATIONS INCLUDE:
— Glue Logic for 3.3V Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade

• ELECTRONIC SIGNA TURE FOR IDENTIFICATION

®

Advanced CMOS Technology

Functional Block Diagram

I/CLK

I

I

I

I

I

(64 X 40)

I

AND-ARRAY

PROGRAMMABLE

I

I

I

I

8

8

8

8

8

8

8

8

IMUX

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

IMUX

I

CLK

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

OE

I
I/OE

Description

The GAL20LV8D, at 3.5 ns maximum propagation delay time,
provides the highest speed performance available in the PLD
market. The GAL20LV8D is manufactured using Lattice
Semiconductor's advanced 3.3V E2CMOS process, which com­bines CMOS with Electrically Erasable (E

2

) floating gate technology.
High speed erase times (<100ms) allow the devices to be repro­grammed quickly and efficiently .

The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configura­tions possible with the GAL20L V8D are the P AL

architectures listed
in the table of the macrocell description section. GAL20LV8D
devices are capable of emulating any of these P AL architectures
with full function/fuse map compatibility .

Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function­ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.

Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. March 2000
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

20lv8_05

Pin Configuration

I
I
I

NC

I
I
I

11

1

PLCC

I/CLK

I

I

4

5

7

GAL20LV8D

9

12 14 16 18

I

I

NC

Vcc

228

Top V iew

NC

GND

I/OE

I/O/Q

I

26

25

I/O/Q
I/O/Q

23

I/O/Q
NC

21

I/O/Q
I/O/Q

19

I/O/Q

I

I/O/Q

Specifications GAL20LV8

GAL20LV8D Ordering Information

Commercial Grade Specifications

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package

3.5 3 2.5
5 4 3 70 GAL20LV8D-5LJ 28-Lead PLCC

7.5 5 5

70

70 GAL20LV8D-7LJ

Part Number Description

GAL20LV8D-3LJ 28-Lead PLCC

28-Lead PLCC

GAL20LV8D

Device Name

Speed (ns)

PowerL = Low Power

XXXXXXXX XX X X X

_

Grade

Package

Blank = Commercial

J = PLCC

2

Output Logic Macrocell (OLMC)

The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom­plished by development software/hardware and is completely trans­parent to the user.

There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
is illustrated in the following pages. T wo global bits, SYN and AC0,
control the mode configuration for all macrocells. The XOR bit of
each macrocell controls the polarity of the output in any of the three
modes, while the AC1 bit of each of the macrocells controls the in­put/output configuration. These two global and 16 individual archi­tecture bits define all possible configurations in a GAL20LV8D . The
information given on these architecture bits is only to give a bet­ter understanding of the device. Compiler software will transpar­ently set these architecture bits from the pin definitions, so the user
should not need to directly manipulate these architecture bits.

The following is a list of the P AL architectures that the GAL20L V8D
can emulate. It also shows the OLMC mode under which the
devices emulate the PAL architecture.

Specifications GAL20LV8

PAL Architectures GAL20LV8D

Emulated by GAL20L V8D Global OLMC Mode

20R8 Registered
20R6 Registered

20R4 Registered
20RP8 Registered
20RP6 Registered
20RP4 Registered

20L8 Complex

20H8 Complex

20P8 Complex

14L8 Simple

16L6 Simple

18L4 Simple

20L2 Simple

14H8 Simple

16H6 Simple

18H4 Simple

20H2 Simple

14P8 Simple

16P6 Simple

18P4 Simple

20P2 Simple

Compiler Support for OLMC

Software compilers support the three different global OLMC modes
as different device types. These device types are listed in the table
below. Most compilers have the ability to automatically select the
device type, generally based on the register usage and output
enable (OE) usage. Register usage on the device forces the soft­ware to choose the registered mode. All combinatorial outputs with
OE controlled by the product term will force the software to choose
the complex mode. The software will choose the simple mode only
when all outputs are dedicated combinatorial without OE control.
The different device types listed in the table can be used to override
the automatic device selection by the software. For further details,
refer to the compiler software manuals.

When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 2 and pin 16 are permanently configured

Registered Complex Simple Auto Mode Select

ABEL P20V8R P20V8C P20V8AS P20V8
CUPL G20V8MS G20V8MA G20V8AS G20V8
LOG/iC GAL20V8_R GAL20V8_C7 GAL20V8_C8 GAL20V8
OrCAD-PLD "Registered"
PLDesigner P20V8R

1

2

"Complex"

P20V8C

TANGO-PLD G20V8R G20V8C G20V8AS

as clock and output enable, respectively . These pins cannot be con­figured as dedicated inputs in the registered mode.

In complex mode pin 2 and pin 16 become dedicated inputs and
use the feedback paths of pin 26 and pin 18 respectively . Because
of this feedback path usage, pin 26 and pin 18 do not have the
feedback option in this mode.

In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
21 and 23) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.

1

2

"Simple"
P20V8C

1
2

3

GAL20V8A

P20V8A

G20V8

1) Used with Configuration keyword.

2) Prior to Version 2.0 support.

3) Supported on Version 1.20 or later.

3

Registered Mode

Specifications GAL20LV8

In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.

Architecture configurations available in this mode are similar to the
common 20R8 and 20RP4 devices with various permutations of
polarity , I/O and register placement.

All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/Os are possible in this mode.

CLK

DQ

XOR

OE

Q

Dedicated input or output functions can be implemented as sub­sets of the I/O function.

Registered outputs have eight product terms per output. I/Os have
seven product terms per output.

The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product T erm Disable (PTD) fuses, are shown
on the logic diagram on the following page.

Registered Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this output configuration.

- Pin 2 controls common CLK for the registered outputs.

- Pin 16 controls common OE for the registered outputs.

- Pin 2 & Pin 16 are permanently configured as CLK &
OE for registered output configuration.

Combinatorial Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1 defines this output configuration.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

- Pin 2 & Pin 16 are permanently configured as CLK &
OE for registered output configuration.

4

Registered Mode Logic Diagram

Specifications GAL20LV8

PLCC Package Pinout

2

41612802024283236

3

0000

0280

4

0320

0600

5

0640

0920

6

0960

1240

7

1280

1560

9

PTD

2640

OLMC

XOR-2560
AC1-2632

OLMC

XOR-2561
AC1-2633

OLMC

XOR-2562
AC1-2634

OLMC

XOR-2563
AC1-2635

OLMC

XOR-2564
AC1-2636

27

26

25

24

23

21

10

11

12

13

64-USER ELECTRONIC SIGNATURE FUSES

2568, 2569, .... .... 2630, 2631

Byte7 Byte6 .... .... Byte1 Byte0

MSB LSB

1600

1880

1920

2200

2240

2520

2703

OLMC

XOR-2565
AC1-2637

OLMC

XOR-2566
AC1-2638

OLMC

XOR-2567
AC1-2639

SYN-2704
AC0-2705

OE

20

19

18

17

16

5

Complex Mode

Specifications GAL20LV8

In the Complex mode, macrocells are configured as output only or
I/O functions.

Architecture configurations available in this mode are similar to the
common 20L8 and 20P8 devices with programmable polarity in
each macrocell.

Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 18 & 26) do not have input capability . De-

XOR

signs requiring eight I/Os can be implemented in the Registered
mode.

All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 2 and
16 are always available as data inputs into the AND array.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.

Combinatorial I/O Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1.

- Pin 19 through Pin 25 are configured to this function.

Combinatorial Output Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

- XOR=1 defines Active High Output.

- AC1=1.

- Pin 18 and Pin 26 are configured to this function.

6