Lattice Semiconductor Corporation GAL16VP8B-25LP, GAL16VP8B-25LJ Datasheet
GAL16VP8
1
10
11
20
I/CLK
I
I
I
I
I
I
I
I
GND
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
5
15
I
I
I
I
I
I
II
CLK
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/CLK
OE
8
8
8
8
8
8
8
8
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
PROGRAMMABLE
AND-ARRAY
(64 X 32)
I
I/OE
High-Speed E2CMOS PLD
Generic Array Logic™
Features
• HIGH DRIVE E2CMOS® GAL® DEVICE
— TTL Compatible 64 mA Output Drive
— 15 ns Maximum Propagation Delay
— Fmax = 80 MHz
— 10 ns Maximum from Clock Input to Data Output
— UltraMOS
• ENHANCED INPUT AND OUTPUT FEATURES
— Schmitt Trigger Inputs
— Programmable Open-Drain or Totem-Pole Outputs
— Active Pull-Ups on All Inputs and I/O pins
2
CELL TECHNOLOGY
• E
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Architecturally Compatible with Standard GAL16V8
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— Ideal for Bus Control & Bus Arbitration Logic
— Bus Address Decode Logic
— Memory Address, Data and Control Circuits
— DMA Control
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
®
Advanced CMOS Technology
Functional Block Diagram
Description
The GAL16VP8, with 64 mA drive capability and 15 ns maximum
propagation delay time is ideal for Bus and Memory control applications. The GAL16VP8 is manufactured using Lattice
Semiconductor's advanced E2CMOS process which combines
CMOS with Electrically Erasable (E
2
) floating gate technology. High
speed erase times (<100ms) allow the devices to be reprogrammed
quickly and efficiently .
System bus and memory interfaces require control logic before
driving the bus or memory interface signals. The GAL16VP8
combines the familiar GAL16V8 architecture with bus drivers as
its outputs. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The 64mA output drive eliminates the need for
additional devices to provide bus driving capability .
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. December 1997
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
16vp8_03
Pin Configuration
PLCC
I/CLKII
2
4
I
Vcc
GAL16VP8
I
6
I
I
1
T op View
8
911
I I/O/QII/O/Q I/O/Q
I/OE
DIP
I/O/Q
20
18
I/O/Q
I/O/Q
16
I/O/Q
GND
I/O/Q
14
13
GAL
16VP8
Specifications GAL16VP8
Blank = Commercial
Grade
Package
PowerL = Low Power
Speed (ns)
XXXXXXXX XX X X X
Device Name
_
P = Plastic DIP
J = PLCC
GAL16VP8B
GAL16VP8 Ordering Information
Commercial Grade Specifications
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package
15 8 10 115 GAL16VP8B-15LP 20-Pin Plastic DIP
115 GAL16VP8B-15LJ 20-Lead PLCC
25 10 15 115 GAL16VP8B-25LP 20-Pin Plastic DIP
115 GAL16VP8B-25LJ 20-Lead PLCC
Part Number Description
2
Output Logic Macrocell (OLMC)
Specifications GAL16VP8
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user.
There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
is illustrated in the following pages. T wo global bits, SYN and AC0,
control the mode configuration for all macrocells. The XOR bit of
Compiler Support for OLMC
Software compilers support the three different global OLMC modes
as different device types. Most compilers also have the ability to
automatically select the device type, generally based on the register
usage and output enable (OE) usage. Register usage on the device
forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose
the simple mode only when all outputs are dedicated combinatorial
without OE control. For further details, refer to the compiler software manuals.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 1 and pin 10 are permanently configured
as clock and output enable, respectively . These pins cannot be configured as dedicated inputs in the registered mode.
each macrocell controls the polarity of the output in any of the three
modes, while the AC1 and AC2 bit of each of the macrocells controls
the input/output and totem-pole/open-drain configuration. These
two global and 24 individual architecture bits define all possible configurations in a GAL16VP8. The information given on these architecture bits is only to give a better understanding of the device.
Compiler software will transparently set these architecture bits from
the pin definitions, so the user should not need to directly manipulate
these architecture bits.
In complex mode pin 1 and pin 10 become dedicated inputs and
use the feedback paths of pin19 and pin 1 1 respectively . Because
of this feedback path usage, pin19 and pin 11 do not have the
feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
14 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
In addition to the architecture configurations, the logic compiler
software also supports configuration of either totem-pole or opendrain outputs. The actual architecture bit configuration, again, is
transparent to the user with the default configuration being the
standard totem-pole output.
3
Registered Mode
Specifications GAL16VP8
In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.
All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/Os are possible in this mode.
Dedicated input or output functions can be implemented as subsets of the I/O function.
CLK
DQ
XOR
OE
Q
Registered outputs have eight product terms per output. I/Os have
seven product terms per output.
The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are
shown on the logic diagram on the following page.
Registered Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 1 controls common CLK for the registered outputs.
- Pin 10 controls common OE for the registered outputs.
- Pin 1 & Pin 10 are permanently configured as CLK & OE
for registered output configuration.
Combinatorial Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 1 & Pin 10 are permanently configured as CLK & OE
for registered output configuration.
4
Registered Mode Logic Diagram
Specifications GAL16VP8
DIP and PLCC Package Pinouts
1
0000
0224
0256
0480
2
0512
0736
3
0768
0992
4
2128
2824201612840
PTD
20
OLMC
XOR-2048
AC1-2120
AC2-2194
19
OLMC
XOR-2049
AC1-2121
AC2-2195
18
OLMC
XOR-2050
AC1-2122
AC2-2196
17
OLMC
XOR-2051
AC1-2123
AC2-2197
16
6
7
8
9
MSB LSB
1024
1248
1280
1504
1536
1760
1792
2016
2191
64-USER ELECTRONIC SIGNATURE FUSES
2056, 2055, .... .... 21 18, 2119
Byte7 Byte6 .... .... Byte1 Byte0
OLMC
XOR-2052
AC1-2124
AC2-2198
OLMC
XOR-2053
AC1-2125
AC2-2199
OLMC
XOR-2054
AC1-2126
AC2-2200
OLMC
XOR-2055
AC1-2127
AC2-2201
SYN-2192
AC0-2193
OE
14
13
12
11
10
5
Complex Mode
Specifications GAL16VP8
In the Complex mode, macrocells are configured as output only or
I/O functions.
Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 1 1 & 19) do not have input capability. Designs requiring eight I/Os can be implemented in the Registered
mode.
XOR
All macrocells have seven product terms per output. One product term is used for programmable output enable control. Pins 1
and 10 are always available as data inputs into the AND array.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
Combinatorial I/O Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no ef fect on this mode.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 12 through Pin 18 are configured to this function.
Combinatorial Output Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
- XOR=1 defines Active High Output.
- AC1 has no ef fect on this mode.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 1 1 and Pin 19 are configured to this function.
6
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