Lattice Semiconductor Corporation GAL16V8D-15LPI, GAL16V8D-15LP, GAL16V8D-15LJI, GAL16V8D-15LJ, GAL16V8D-10QP Datasheet

GAL16V8

1

10

11

20

I/CLK

I

I

I

I

I

I

I

I

GND

Vcc

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/OE

5

15

High Performance E2CMOS PLD

Generic Array Logic™

Features

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY

Functional Block Diagram

I/CLK

CLK

— 3.5 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 3.0 ns Maximum from Clock Input to Data Output
— UltraMOS

®

Advanced CMOS Technology

• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
— 75mA T yp Icc on Low Power Device
— 45mA T yp Icc on Quarter Power Device

• ACTIVE PULL-UPS ON ALL PINS

2

CELL TECHNOLOGY

• E
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)

I

I

I

I

8

8

8

8

OLMC

OLMC

OLMC

OLMC

— 20 Year Data Retention

OLMC

• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Also Emulates 20-pin PAL

®

Devices with Full

Function/Fuse Map/Parametric Compatibility

I

(64 X 32)

AND-ARRAY

I

PROGRAMMABLE

8

8

OLMC

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

OLMC

— 100% Functional Testability

• APPLICATIONS INCLUDE:

I

8

— DMA Control

OLMC

— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade

I

8

• ELECTRONIC SIGNA TURE FOR IDENTIFICATION

Pin Configuration

4

6

8

9

I GND

I
I

I
I

I
I

I
I

PLCC

I/CLKII

Vcc

2

20

GAL16V8

T op View

11 13

I/O/Q I/O/Q

I/OE

SOIC

1

20I/CLK

GAL

16V8

5

Top

View

10

11

I/O/Q

18

I/O/Q

I/O/Q

16

I/O/Q

I/O/Q

I/O/Q

14

GAL

16V8

Vcc
I/O/Q
I/O/Q
I/O/Q

I/O/Q
I/O/Q

15

I/O/Q
I/O/Q
I/O/Q
I/OE

Description

The GAL16V8, at 3.5 ns maximum propagation delay time, com­bines a high performance CMOS process with Electrically Eras-

2

able (E

) floating gate technology to provide the highest speed
performance available in the PLD market. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and ef­ficiently.

The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configura­tions possible with the GAL16V8 are the PAL

architectures listed
in the table of the macrocell description section. GAL16V8 devices
are capable of emulating any of these PAL architectures with full
function/fuse map/parametric compatibility.

Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function­ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.

Copyright © 2001 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. May 2001
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

16v8_08

I

I

I

I

I

GND

1

OE

DIP

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/OE

GAL16V8 Ordering Information

Commercial Grade Specifications

)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP

5.35.20.3511JL3-D8V61LAGCCLPdaeL-02

534 511

5.775

01017

51210155PQ51-D8V61LAGPIDcitsalPniP-02

52512155PQ52-D8V61LAGPIDcitsalPniP-02

1518V61LAG7-DLP
1518V61LAG7-DJL
1518V61LAG7-DLS -02niPCIOS

55PQ01-D8V61LAGPIDcitsalPniP-02
55JQ01-D8V61LAGCCLPdaeL-02

511
511
511

55JQ51-D8V61LAGCCLPdaeL-02
09PL51-D8V61LAGPIDcitsalPniP-02
09
09

55JQ52-D8V61LAGCCLPdaeL-02
09PL52-D8V61LAGPIDcitsalPniP-02
09
09

8V61LAG5-DJL

8V61LAG01-DPL
8V61LAG01-DJL
8V61LAG01-DLS niP-02CIOS

L51-D8V61LAGJ daeL-02CCLP
L51-D8V61LAGS

L52-D8V61LAGJ
L52-D8V61LAGS -02niPCIOS

Specifications GAL16V8

CCLPdaeL-02

PIDcitsalPniP-02

CCLPdaeL-02

PIDcitsalPniP-02

CCLPdaeL-02

CIOSniP-02

CCLPdaeL-02

Industrial Grade Specifications

)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP

5.775031
031

01017 031

031

512101031IPL51-D8V61LAGPIDcitsalPniP-02

031IJL51-D8V61LAGCCLPdaeL-02

02311156IPQ02-D8V61LAGPIDcitsalPniP-02

56IJQ02-D8V61LAGCCLPdaeL-02

52512156IPQ52-D8V61LAGPIDcitsalPniP-02

56IJQ52-D8V61LAGCCLPdaeL-02

031IPL52-D8V61LAGPIDcitsalPniP-02
031IJL52-D8V61LAGCCLPdaeL-02

8V61LAG7-DIPL
8V61LAG7-DIJL
8V61LAG01-DIPL
8V61LAG01-DIJL

Part Number Description

XXXXXXXX XX X X X

GAL16V8D

Device Name

Speed (ns)

PIDcitsalPniP-02

CCLPdaeL-02

PIDcitsalPniP-02

CCLPdaeL-02

_

Grade

Blank = Commercial
I = Industrial

Q = Quarter Power

PowerL = Low Power

Package

P = Plastic DIP
J = PLCC
S = SOIC

2

Output Logic Macrocell (OLMC)

The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom­plished by development software/hardware and is completely trans­parent to the user.

There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
are illustrated in the following pages. Two global bits, SYN and
AC0, control the mode configuration for all macrocells. The XOR
bit of each macrocell controls the polarity of the output in any of the
three modes, while the AC1 bit of each of the macrocells controls
the input/output configuration. These two global and 16 individ­ual architecture bits define all possible configurations in a GAL16V8
. The information given on these architecture bits is only to give
a better understanding of the device. Compiler software will trans­parently set these architecture bits from the pin definitions, so the
user should not need to directly manipulate these architecture bits.

The following is a list of the PAL architectures that the GAL16V8
can emulate. It also shows the OLMC mode under which the
GAL16V8 emulates the PAL architecture.

Specifications GAL16V8

PAL Architectures GAL16V8

Emulated by GAL16V8 Global OLMC Mode

16R8 Registered
16R6 Registered

16R4 Registered
16RP8 Registered
16RP6 Registered
16RP4 Registered

16L8 Complex

16H8 Complex

16P8 Complex

10L8 Simple

12L6 Simple

14L4 Simple

16L2 Simple

10H8 Simple

12H6 Simple

14H4 Simple

16H2 Simple

10P8 Simple

12P6 Simple

14P4 Simple

16P2 Simple

Compiler Support for OLMC

Software compilers support the three different global OLMC modes
as different device types. These device types are listed in the table
below. Most compilers have the ability to automatically select the
device type, generally based on the register usage and output
enable (OE) usage. Register usage on the device forces the soft­ware to choose the registered mode. All combinatorial outputs with
OE controlled by the product term will force the software to choose
the complex mode. The software will choose the simple mode only
when all outputs are dedicated combinatorial without OE control.
The different device types listed in the table can be used to override
the automatic device selection by the software. For further details,
refer to the compiler software manuals.

When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 1 and pin 1 1 are permanently configured

Registered Complex Simple Auto Mode Select

ABEL P16V8R P16V8C P16V8AS P16V8
CUPL G16V8MS G16V8MA G16V8AS G16V8
LOG/iC GAL16V8_R GAL16V8_C7 GAL16V8_C8 GAL16V8
OrCAD-PLD "Registered"
PLDesigner P16V8R

1

2

"Complex"

P16V8C

TANGO-PLD G16V8R G16V8C G16V8AS

as clock and output enable, respectively . These pins cannot be con­figured as dedicated inputs in the registered mode.

In complex mode pin 1 and pin 1 1 become dedicated inputs and
use the feedback paths of pin 19 and pin 12 respectively. Because
of this feedback path usage, pin 19 and pin 12 do not have the
feedback option in this mode.

In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
15 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.

1

2

"Simple"
P16V8C

1

2

3

GAL16V8A

P16V8A

G16V8

1) Used with Configuration keyword.

2) Prior to Version 2.0 support.

3) Supported on Version 1.20 or later .

3

Registered Mode

Specifications GAL16V8

In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.

Architecture configurations available in this mode are similar to the
common 16R8 and 16RP4 devices with various permutations of
polarity , I/O and register placement.

All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/O's are possible in this mode.

CLK

DQ

XOR

Q

Dedicated input or output functions can be implemented as sub­sets of the I/O function.

Registered outputs have eight product terms per output. I/O's have
seven product terms per output.

The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product T erm Disable (PTD) fuses, are shown
on the logic diagram on the following page.

Registered Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this output configuration.

- Pin 1 controls common CLK for the registered outputs.

- Pin 11 controls common OE for the registered outputs.

- Pin 1 & Pin 11 are permanently configured as CLK &
OE for registered output configuration.

OE

Combinatorial Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically .

- AC1=1 defines this output configuration.

- Pin 1 & Pin 11 are permanently configured as CLK &
OE for registered output configuration.

4

Registered Mode Logic Diagram

Specifications GAL16V8

DIP & PLCC Package Pinouts

1

201612840

24

0000

0224

2

0256

0480

3

0512

0736

4

0768

0992

5

1024

1248

6

2128

28

PTD

OLMC

19

XOR-2048
AC1-2120

OLMC

18

XOR-2049
AC1-2121

OLMC

17

XOR-2050
AC1-2122

OLMC

16

XOR-2051
AC1-2123

OLMC

15

XOR-2052
AC1-2124

1280

OLMC

1504

7

1536

XOR-2053
AC1-2125

OLMC

1760

8

1792

XOR-2054
AC1-2126

OLMC

2016

9

2191

XOR-2055
AC1-2127

OE

14

13

12

11

SYN-2192
AC0-2193

5

Complex Mode

Specifications GAL16V8

In the Complex mode, macrocells are configured as output only or
I/O functions.

Architecture configurations available in this mode are similar to the
common 16L8 and 16P8 devices with programmable polarity in
each macrocell.

Up to six I/O's are possible in this mode. Dedicated inputs or
outputs can be implemented as subsets of the I/O function. The
two outer most macrocells (pins 12 & 19) do not have input capa-

XOR

bility. Designs requiring eight I/O's can be implemented in the
Registered mode.

All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1 and
1 1 are always available as data inputs into the AND array.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.

Combinatorial I/O Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1.

- Pin 13 through Pin 18 are configured to this function.

Combinatorial Output Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically .

- XOR=1 defines Active High Output.

- AC1=1.

- Pin 12 and Pin 19 are configured to this function.

6

Complex Mode Logic Diagram

Specifications GAL16V8

DIP & PLCC Package Pinouts

1

24

201612840

0000

0224

2

0256

0480

3

0512

0736

4

0768

0992

5

1024

1248

6

2128

PTD

28

OLMC

19

XOR-2048
AC1-2120

OLMC

18

XOR-2049
AC1-2121

OLMC

17

XOR-2050
AC1-2122

OLMC

16

XOR-2051
AC1-2123

OLMC

15

XOR-2052
AC1-2124

1280

OLMC

1504

7

1536

XOR-2053
AC1-2125

OLMC

1760

8

1792

XOR-2054
AC1-2126

OLMC

2016

9

XOR-2055
AC1-2127

14

13

12

11

2191

SYN-2192
AC0-2193

7

Simple Mode

Specifications GAL16V8

In the Simple mode, macrocells are configured as dedicated inputs
or as dedicated, always active, combinatorial outputs.

Architecture configurations available in this mode are similar to the
common 10L8 and 12P6 devices with many permutations of ge­neric output polarity or input choices.

All outputs in the simple mode have a maximum of eight product
terms that can control the logic. In addition, each output has pro­grammable polarity.

Vcc

XOR

Vcc

XOR

Pins 1 and 11 are always available as data inputs into the AND
array . The center two macrocells (pins 15 & 16) cannot be used
as input or I/O pins, and are only available as dedicated outputs.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram.

Combinatorial Output with Feedback Configuration
for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this configuration.

- All OLMC except pins 15 & 16 can be configured to
this function.

Combinatorial Output Configuration for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this configuration.

- Pins 15 & 16 are permanently configured to this
function.

Dedicated Input Configuration for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1 defines this configuration.

- All OLMC except pins 15 & 16 can be configured to
this function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically .

8

Simple Mode Logic Diagram

Specifications GAL16V8

DIP & PLCC Package Pinouts

1

24

201612840

0000

0224

2128

28

PTD

OLMC

XOR-2048
AC1-2120

19

2

0256

0480

OLMC

XOR-2049
AC1-2121

18

3

0512

0736

OLMC

XOR-2050
AC1-2122

17

4

0768

0992

OLMC

XOR-2051
AC1-2123

16

5

1024

1248

OLMC

XOR-2052
AC1-2124

15

6

1280

1504

OLMC

XOR-2053
AC1-2125

14

7

1536

1760

OLMC

XOR-2054
AC1-2126

13

8

1792

2016

9

2191

OLMC

XOR-2055
AC1-2127

12

11

SYN-2192
AC0-2193

9

Specifications GAL16V8D

Absolute Maximum Ratings

Supply voltage VCC...................................... –0.5 to +7V

Input voltage applied .......................... –2.5 to VCC +1.0V

Off-state output voltage applied ......... –2.5 to VCC +1.0V

Storage Temperature ................................ –65 to 150°C

Ambient T emperature with

Power Applied........................................–55 to 125°C

1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

(1)

Recommended Operating Conditions

Commercial Devices:

Ambient T emperature (TA) ...............................0 to 75°C

Supply voltage (VCC)

with Respect to Ground ..................... +4.75 to +5.25V

Industrial Devices:

Ambient T emperature (TA) ...........................–40 to 85°C

Supply voltage (VCC)

with Respect to Ground ..................... +4.50 to +5.50V

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.3MAX. UNITS

VIL Input Low Voltage Vss – 0.5 — 0.8 V

VIH Input High Voltage 2.0 — Vcc+1 V

1

IIL

Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 µA

IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC ——10µA

VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V

VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V

IOL Low Level Output Current L-3/-5 & -7 (Ind. PLCC) — — 16 mA

L-7 (Except Ind. PLCC)/-10/-15/-25 — — 24 mA
Q-10/-15/-20/-25

IOH High Level Output Current — — –3.2 mA

2

IOS

Output Short Circuit Current VCC = 5V VOUT = 0.5V TA= 25°C –30 — –150 mA

COMMERCIAL

ICC Operating Power VIL = 0.5V VIH = 3.0V L -3/-5/-7/-10 — 75 115 mA

Supply Current f

toggle = 15MHz Outputs Open L-15/-25 — 75 90 mA

Q-10/-15/-25 — 45 55 mA

INDUSTRIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L -7/-10/-15/-25 — 75 130 mA

Supply Current f

1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.

2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester

ground degradation. Characterized but not 100% tested.

3) T ypical values are at Vcc = 5V and TA = 25 °C

toggle = 15MHz Outputs Open Q -20/-25 — 45 65 mA

10

AC Switching Characteristics

Specifications GAL16V8D

Over Recommended Operating Conditions

TEST

COND1.

DESCRIPTION

COM

-3

MIN. MAX.

COM

-5

MIN. MAX.

COM / IND

-7

MIN. MAX.

UNITSPARAMETER

tpd A Input or I/O to Comb. Output 1 3.5 1 5 1 7.5 ns
tco A Clock to Output Delay 1 3 1 4 1 5 ns

2

tcf

— Clock to Feedback Delay — 2.5 — 3 — 3 ns

tsu — Setup T ime, Input or Feedback before Clock↑ 2.5 — 3 — 5 — ns

th — Hold Time, Input or Feedback after Clock↑ 0—0—0—ns

A Maximum Clock Frequency with 182 — 142.8 — 100 — MHz

External Feedback, 1/(tsu + tco)

3

fmax

twh — Clock Pulse Duration, High 2

twl — Clock Pulse Duration, Low 2

A Maximum Clock Frequency with 200 — 166 — 125 — MHz

Internal Feedback, 1/(tsu + tcf)

A Maximum Clock Frequency with 250 — 166 — 125 — MHz

No Feedback

4

—3 4—4—ns

4

—3 4—4—ns

ten B Input or I/O to Output Enabled — 4.5 1 6 1 9 ns

B OE to Output Enabled — 4.5 1 6 1 6 ns

tdis C Input or I/O to Output Disabled — 4.5 1 5 1 9 ns

C OE to Output Disabled — 4.5 1 5 1 6 ns

1) Refer to Switching Test Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.

3) Refer to fmax Descriptions section. Characterized but not 100% tested.

4) Characterized but not 100% tested.

Capacitance (TA = 25°C, f = 1.0 MHz)

SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS

C

I

C

I/O

*Characterized but not 100% tested.

Input Capacitance 8 pF VCC = 5.0V , VI = 2.0V

I/O Capacitance 8 pF VCC = 5.0V , V

I/O

= 2.0V

11

Specifications GAL16V8

Specifications GAL16V8D

AC Switching Characteristics

Over Recommended Operating Conditions

COM / IND COM / IND IND COM / IND

PARAM.

TEST

COND

DESCRIPTION

1

.

-10

MIN. MAX.

-15

MIN. MAX.

-20

MIN. MAX.

-25

MIN. MAX.

UNITS

tpd A Input or I/O to Comb. Output 3 10 3 15 3 20 3 25 ns
tco A Clock to Output Delay 2 7 2 10 2 11 2 12 ns

2

tcf

— Clock to Feedback Delay — 6 — 8 — 9 — 10 ns

tsu — Setup Time, Input or Fdbk before Clk↑ 7.5 — 12 — 13 — 15 — ns

th — Hold Time, Input or Fdbk after Clk↑ 0— 0— 0— 0— ns

A Maximum Clock Frequency with 66.7 — 45.5 — 41.6 — 37 — MHz

External Feedback, 1/(tsu + tco)

3

fmax

A Maximum Clock Frequency with 71.4 — 50 — 45.4 — 40 — MHz

Internal Feedback, 1/(tsu + tcf)

A Maximum Clock Frequency with 83.3 — 62.5 — 50 — 41.6 — MHz

No Feedback

twh — Clock Pulse Duration, High 6 — 8 — 10 — 12 — ns

twl — Clock Pulse Duration, Low 6 — 8 — 10 — 12 — ns

ten B Input or I/O to Output Enabled 1 10 — 15 — 18 — 20 ns

t B OE to Output Enabled 1 10 — 15 — 18 — 20 ns

tdis C Input or I/O to Output Disabled 1 10 — 15 — 18 — 20 ns

t C OE to Output Disabled 1 10 — 15 — 18 — 20 ns

1) Refer to Switching Test Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.

3) Refer to fmax Descriptions section. Characterized but not 100% tested.

Capacitance (TA = 25°C, f = 1.0 MHz)

SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS

C

I

C

I/O

*Characterized but not 100% tested.

Input Capacitance 8 pF VCC = 5.0V , VI = 2.0V

I/O Capacitance 8 pF VCC = 5.0V , V

= 2.0V

I/O

12

(

)

Switching Waveforms

Specifications GAL16V8

INPUT or
I/O FEEDBACK

COMBINATIONAL
OUTPUT

INPUT or
I/O FEEDBACK

dis

t

COMBINATIONAL
OUTPUT

Input or I/O to Output Enable/Disable

VALID INPUT

t

pd

en

t

INPUT or
I/O FEEDBACK

CLK

REGISTERED
OUTPUT

OE

REGISTERED
OUTPUT

VALID INPUT

su

t

(external fdbk)

h

t

t

co

1/

f

max

Registered OutputCombinatorial Output

dis

t

OEOE

OE to Output Enable/Disable

OEOE

en

t

CLK

wh

t

1/fmax

w/o fb

wl

t

CLK

REGISTERED
FEEDBACK

1/fmax (internal fdbk)

cf

t

su

t

Clock Width

fmax with Feedback

13

fmax Descriptions

Specifications GAL16V8

CLK

LOGIC
ARRAY

t

su

REGISTER

t

co

fmax with External Feedback 1/(tsu+tco)

Note: fmax with external feedback is calculated from measured
tsu and tco.

CLK

LOGIC
ARRAY

t

su + th

REGISTER

fmax with No Feedback

Note: fmax with no feedback may be less than 1/(twh + twl). This

is to allow for a clock duty cycle of other than 50%.

Switching Test Conditions

CLK

LOGIC
ARRAY

REGISTER

t

cf

t

pd

fmax with Internal Feedback 1/(tsu+tcf)

Note: tcf is a calculated value, derived by subtracting tsu from

the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.

Input Pulse Levels

Input Rise

GAL16V8D-10
(and slower)

GND to 3.0V

2 – 3ns 10% – 90%

and Fall Times

GAL16V8D-3/-5/-7

Input Timing Reference Levels
Output Timing Reference Levels

Output Load

3-state levels are measured 0.5V from

1.5ns 10% – 90%

1.5V

1.5V

See figure at right

Table 2-0003/16V8

steady-state active level.

GAL16V8D (except -3) Output Load Conditions (see figure
above)

T est Condition R1 R2 CL

A 200Ω 390Ω 50pF
B Active High ∞ 390Ω 50pF

Active Low 200Ω 390Ω 50pF

C Active High ∞ 390Ω 5pF

Active Low 200Ω 390Ω 5pF

+5V

R

1

FROM OUTPUT (O/Q)
UNDER TEST

R

2

*C

INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

L

C *

L

TEST POINT

14

Switching Test Conditions (Continued)

Specifications GAL16V8

GAL16V8D-3 Output Load Conditions (see figure at right)
T est Condition R1 CL

A50Ω 35pF
B High Z to Active High at 1.9V 50Ω 35pF

High Z to Active Low at 1.0V 50Ω 35pF

C Active High to High Z at 1.9V 50Ω 35pF

Active Low to High Z at 1.0V 50Ω 35pF

Electronic Signature

An electronic signature is provided in every GAL16V8 device. It
contains 64 bits of reprogrammable memory that can contain user
defined data. Some uses include user ID codes, revision numbers,
or inventory control. The signature data is always available to the
user independent of the state of the security cell.

NOTE: The electronic signature is included in checksum calcula­tions. Changing the electronic signature will alter the checksum.

Security Cell

A security cell is provided in the GAL16V8 devices to prevent un­authorized copying of the array patterns. Once programmed, this
cell prevents further read access to the functional bits in the device.
This cell can only be erased by re-programming the device, so the
original configuration can never be examined once this cell is pro­grammed. The Electronic Signature is always available to the user,
regardless of the state of this control cell.

Latch-Up Protection

GAL16V8 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias minimizes the
potential of latch-up caused by negative input undershoots. Ad­ditionally, outputs are designed with n-channel pull-ups instead of
the traditional p-channel pull-ups in order to eliminate latch-up due
to output overshoots.

Device Programming

+1.45V

FROM OUTPUT (O/Q)
UNDER TEST

TEST POINT

0

= 50Ω, CL = 35pF*

Z

R

1

*CL includes test fixture and probe capacitance.

Output Register Preload

When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system
operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). T o
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.

GAL16V8 devices include circuitry that allows each registered
output to be synchronously set either high or low. Thus, any present
state condition can be forced for test sequencing. If necessary,
approved GAL programmers capable of executing text vectors
perform output register preload automatically.

Input Buffers

GAL16V8 devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
devices.

The GAL16V8 input and I/O pins have built-in active pull-ups. As
a result, unused inputs and I/O's will float to a TTL "high" (logical
"1"). Lattice Semiconductor recommends that all unused inputs
and tri-stated I/O pins be connected to another active input, VCC,
or Ground. Doing this will tend to improve noise immunity and re­duce ICC for the device.

GAL devices are programmed using a Lattice Semiconductor­approved Logic Programmer, available from a number of manu­facturers. Complete programming of the device takes only a few
seconds. Erasing of the device is transparent to the user, and is
done automatically as part of the programming cycle.

15

T ypical Input Pull-up Characteristic

0

-20

-40

Input Current (uA)

-60
0

1.0 2.0 3.0 4.0 5.0

Input Voltage (V olts)

Power-Up Reset

Vcc

CLK

INTERNAL REGISTER

Q - OUTPUT

Vcc (min.)

Specifications GAL16V8

t

su

t

wl

t

pr

Internal Register
Reset to Logic "0"

FEEDBACK/EXTERNAL

OUTPUT REGISTER

Circuitry within the GAL16V8 provides a reset signal to all reg­isters during power-up. All internal registers will have their Q

outputs set low after a specified time (
the state on the registered output pins (if they are enabled) will

always be high on power-up, regardless of the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. Be­cause of the asynchronous nature of system power-up, some

Input/Output Equivalent Schematics

INPUT/OUTPUT EQUIV ALENT SCHEMATICS

tpr , 1µs MAX). As a result,

PIN

Vcc

Active Pull-up
Circuit

Vcc

Vref

Vcc

ESD
Protection
Circuit

Device P in
Reset to Logic "1"

conditions must be met to provide a valid power-up reset of the
device. First, the VCC rise must be monotonic. Second, the clock
input must be at static TTL level as shown in the diagram during

power up. The registers will reset within a maximum of
As in normal system operation, avoid clocking the device until all

input and feedback path setup times have been met. The clock
must also meet the minimum pulse width requirements.

tpr time.

PIN

Feedback

Active Pull-up
Circuit

Tri-State

Vcc

Vref

Control

PIN

ESD
Protection
Circuit

Typ. V ref = 3.2V

T ypical Input

Data
Output

Typ. V ref = 3.2V

16

PIN

Feedback
(To Input Buffer)

Typical Output

Specifications GAL16V8

GAL16V8D-3/-5/-7 (IND PLCC): Typical AC and DC Characteristic Diagrams

N

1.2

1.1

0.9

Normalized Tpd

0.8

ormalized Tpd vs Vcc

PT H->L

PT L->H

1

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Normalized Tpd vs Temp

1.3

1.2

1.1

0.9

Normalized Tpd

0.8

0.7

PT H->L

PT L->H

1

-55 -25 0 25 50 75 100 125

Temperature (deg. C)

Normalized Tco vs Vcc

1.2

1.1

1

0.9

Normalized Tco

0.8

4.50 4.75 5.00 5.25 5.50

RISE

Supply Voltage (V)

Normalized Tco vs Temp

1.3

1.2

1.1

1

0.9

Normalized Tco

0.8

0.7

-55 -25 0 2 5 50 75 100 125

RISE

FALL

Temperature (deg. C)

FALL

Normalized Tsu vs Vcc

1.2

1.1

1

0.9

Normalized Tsu

0.8

4.50 4.75 5.00 5.25 5.50

PT H->L

PT L->H

Supply Voltage (V)

Normalized Tsu vs Temp

1.3

1.2

1.1

0.9

Normalized Tsu

0.8

0.7

PTH->L

PT L->H

1

-55-250 255075100125

Temperature (deg. C)

Delta Tpd vs # of Outputs

Switching

0

-0.1

-0.2

-0.3

Delta Tpd (ns)

-0.4
12345678

RISE

Number of Outputs Switching

Delta Tpd vs Output Loading

14
12
10

Delta Tpd (ns)

8
6
4
2
0

-2

RISE

FALL

0 50 100 150 200 250 3 00

Output Loading (pF)

FALL

Delta Tco vs # of Outputs

Switching

0

-0.1

-0.2

-0.3

Delta Tco (ns)

-0.4
12345678

Number of Outputs Switching

Delta Tco vs Output Loading

14
12
10

Delta Tco (ns)

8
6
4
2
0

-2

RISE

FALL

0 50 100 150 200 250 3 00

Output Loading (pF)

RISE

FALL

17

Specifications GAL16V8

GAL16V8D-3/-5/-7 (IND PLCC): Typical AC and DC Characteristic Diagrams

1

0.75

0.5

Vol (V)

Vol vs Iol

0.25

0

0 10203040

Iol (mA)

Normalized Icc vs Vcc

1.2

1.1

1

0.9

Normalized Icc

0.8

4.50 4. 75 5.00 5.25 5.50

Supply Voltage (V)

Voh vs Ioh

5

4

3

2

Voh (V)

1

0

0 1020304050

Ioh (mA)

Normalized Icc vs Temp

1.3

1.2

1.1

1

Normalized Icc

0.9

0.8

-55 -25 0 25 50 75 100 125

Temperature (deg. C)

3.25

3

Voh (V)

2.75

2.5
01234

Ioh (mA)

Normalized Icc vs Freq.

Voh vs Ioh

1.2

1.15

1.1

1.05

1

Normalized Icc

0.95

0.9
0255075100

Frequency (MHz)

Delta Icc vs Vin (1 input)

10

8

6

4

Delta Icc (mA)

2

0

00.511.522.533.54

Vin (V)

Input Clamp (Vik)

0
10
20
30
40
50

Iik (mA)

60
70
80
90

-2 -1.5 -1 -0.5 0

Vik (V)

18

Specifications GAL16V8

GAL16V8D-7 (Except IND PLCC)/-10L: Typical AC and DC Characteristic Diagrams

Normalized Tpd vs Vcc

1.15

1.1

1.05

1

Normalized Tpd

0.95

0.9

4.5 4.75 5 5.25 5.5

Supply Voltage (V)

Normalized Tpd vs Temp

1.3

1.2

1.1

1

0.9

Normalized Tpd

0.8

RISE
FALL

-55 -25 0 25 50 75 100 125

Temperature (deg. C)

RISE
FALL

Normalized Tco vs Vcc

1.15

1.1

1.05

1

Normalized Tco

0.95

0.9

4.5 4.75 5 5.25 5.5

Supply Voltage (V)

Normalized Tco vs Temp

1.3

1.2

1.1

1

0.9

Normalized Tco

0.8

-55 -25 0 25 50 75 100 125

RISE
FALL

Temperature (deg. C)

RISE
FALL

Normalized Tsu vs Vcc

1.2

1.1

1

0.9

Normalized Tsu

0.8

4.5 4.75 5 5.25 5.5

RISE
FALL

Supply Voltage (V)

Normalized Tsu vs Temp

1.3

1.2

1.1

1

Normalized Tsu

0.9

0.8

-55-25 0255075100125

RISE
FALL

Temperature (deg. C)

Delta Tpd vs # of Outputs Switching

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

Delta Tpd (ns)

-0.8

-0.9

-1
12345678

RISE
FALL

Number of Outputs Switching

Delta Tpd vs Output Loading

12

RISE
FALL

0 50 100 150 200 250 300

Delta Tpd (ns)

8

4

0

-4

Output Loading (pF)

Delta Tco vs # of Outputs Switching

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

Delta Tco (ns)

-0.8

-0.9

-1
12345678

RISE
FALL

Number of Outputs Switching

Delta Tco vs Output Loading

12

8

4

0

Delta Tco (ns)

-4
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

19

Specifications GAL16V8

GAL16V8D-7 (Except IND PLCC)/-10L: Typical AC and DC Characteristic Diagrams

Vol vs Iol

0.5

0.4

0.3

0.2

Vol (V)

0.1

0

1 6 11 16 21 26

Iol (mA)

Normalized Icc vs Vcc

1.1

1

0.9

Normalized Icc

0.8
3 3.15 3.3 3. 45 3.6

Supply Voltage (V)

Voh vs Ioh

4

3

2

Voh (V)

1

0

0 5 10 15 20 25

Ioh (mA)

Normalized Icc vs Temp

1.2

1.1

1

0.9

Normalized Icc

0.8

-55-25 0 255088100125

Temperature (deg. C)

Voh vs Ioh

4

3.5

Voh (V)

3

2.5

0.00 1. 00 2.00 3.00 4.00 5.00

Ioh (mA)

Normalized Icc vs Freq

1.15

1.1

1.05

1

Normalized Icc

0.95
115255075100

Frequency (MHz)

Delta Icc vs Vin (1 input)

9
8
7
6
5
4
3

Delta Icc (mA)

2
1
0

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Vin (V)

0
10
20
30
40
50

Iik (mA)

60
70
80
90

-3 -2.5 -2 -1.5 -1 -0.5 0

Vik (V)

Input Clamp (Vik)

20

Specifications GAL16V8

GAL16V8D-10Q (and Slower): Typical AC and DC Characteristic Diagrams

Normalized Tpd vs Vcc

1.2

1.1

1

0.9

Normalized Tpd

0.8

4.50 4.75 5.00 5.25 5.50

PT H->L
PT L->H

Supply Voltage (V)

Normalized Tpd vs Temp

1.3

1.2

1.1

0.9

Normalized Tpd

0.8

0.7

PT H->L
PT L->H

1

-55 -25 0 25 50 75 100 125

Temperature (deg. C)

Normalized Tco vs Vcc

1.2

RISE

1.1

1

0.9

Normalized Tco

0.8

4.50 4.75 5.00 5.25 5.50

FALL

Supply Voltage (V)

Normalized Tco vs Temp

1.3

1.2

1.1

1

0.9

Normalized Tco

0.8

0.7

-55 -25 0 25 50 75 100 125

RISE
FALL

Temperature (deg. C)

Normalized Tsu vs Vcc

1.2

1.1

1

0.9

Normalized Tsu

0.8

4.50 4.75 5.00 5.25 5.50

PT H->L
PT L->H

Supply Voltage (V)

Normalized Tsu vs Temp

1.3

1.2

1.1

0.9

Normalized Tsu

0.8

0.7

PT H->L
PT L->H

1

-55 -25 0 25 50 75 100 125

Temperature (deg. C)

Delta Tpd vs # of Outputs

0

-0.2

-0.4

-0.6

-0.8

Delta Tpd (ns)

-1

-1.2
12345678

Switching

RISE
FALL

Number of Outputs Switching

Delta Tpd vs Output Loading

12
10

8
6
4
2
0

Delta Tpd (ns)

-2

-4

-6
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

Delta Tco vs # of Outputs

0

-0.2

-0.4

-0.6

-0.8

Delta Tco (ns)

-1

-1.2
12345678

Switching

RISE
FALL

Number of Outputs Switching

Delta Tco vs Output Loading

12
10

8
6
4
2
0

Delta Tco (ns)

-2

-4
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

21

Specifications GAL16V8

GAL16V8D-10Q (and Slower): Typical AC and DC Characteristic Diagrams

Vol vs Iol

0.6

0.4

Vol (V)

0.2

0

0 10203040

Iol (mA)

Normalized Icc vs Vcc

1.2

1.1

1

0.9

Normalized Icc

0.8

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Voh vs Ioh

5

4

3

2

Voh (V)

1

0

0 1020304050

Ioh (mA)

Normalized Icc vs Temp

1.3

1.2

1.1

1

0.9

Normalized Icc

0.8

0.7

-55 -25 0 25 50 75 100 125

Temperature (deg. C)

Voh vs Ioh

4

3.8

3.6

3.4

Voh (V)

3.2

3

01234

Ioh (mA)

Normalized Icc vs Freq.

1.4

1.3

1.2

1.1

1

Normalized Icc

0.9

0.8
0 25 50 75 100

Frequency (MHz)

Delta Icc vs Vin (1 input)

8

6

4

2

Delta Icc (mA)

0

0 0.5 1 1.5 2 2.5 3 3.5 4

Vin (V)

Input Clamp (Vik)

0

10

20

30

Iik (mA)

40

50

60

-2 -1.5 -1 -0.5 0

Vik (V)

22