Lattice Semiconductor Corporation GAL16V8D-15LPI, GAL16V8D-15LP, GAL16V8D-15LJI, GAL16V8D-15LJ, GAL16V8D-10QP Datasheet
...
GAL16V8
1
10
11
20
I/CLK
I
I
I
I
I
I
I
I
GND
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
5
15
High Performance E2CMOS PLD
Generic Array Logic™
Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
Functional Block Diagram
I/CLK
CLK
— 3.5 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 3.0 ns Maximum from Clock Input to Data Output
— UltraMOS
®
Advanced CMOS Technology
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
— 75mA T yp Icc on Low Power Device
— 45mA T yp Icc on Quarter Power Device
• ACTIVE PULL-UPS ON ALL PINS
2
CELL TECHNOLOGY
• E
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
I
I
I
I
8
8
8
8
OLMC
OLMC
OLMC
OLMC
— 20 Year Data Retention
OLMC
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Also Emulates 20-pin PAL
®
Devices with Full
Function/Fuse Map/Parametric Compatibility
I
(64 X 32)
AND-ARRAY
I
PROGRAMMABLE
8
8
OLMC
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
OLMC
— 100% Functional Testability
• APPLICATIONS INCLUDE:
I
8
— DMA Control
OLMC
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
I
8
• ELECTRONIC SIGNA TURE FOR IDENTIFICATION
Pin Configuration
4
6
8
9
I GND
I
I
I
I
I
I
I
I
PLCC
I/CLKII
Vcc
2
20
GAL16V8
T op View
11 13
I/O/Q I/O/Q
I/OE
SOIC
1
20I/CLK
GAL
16V8
5
Top
View
10
11
I/O/Q
18
I/O/Q
I/O/Q
16
I/O/Q
I/O/Q
I/O/Q
14
GAL
16V8
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
15
I/O/Q
I/O/Q
I/O/Q
I/OE
Description
The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Eras-
2
able (E
) floating gate technology to provide the highest speed
performance available in the PLD market. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configurations possible with the GAL16V8 are the PAL
architectures listed
in the table of the macrocell description section. GAL16V8 devices
are capable of emulating any of these PAL architectures with full
function/fuse map/parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Copyright © 2001 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. May 2001
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
16v8_08
I
I
I
I
I
GND
1
OE
DIP
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
GAL16V8 Ordering Information
Commercial Grade Specifications
)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP
5.35.20.3511JL3-D8V61LAGCCLPdaeL-02
534 511
5.775
01017
51210155PQ51-D8V61LAGPIDcitsalPniP-02
52512155PQ52-D8V61LAGPIDcitsalPniP-02
1518V61LAG7-DLP
1518V61LAG7-DJL
1518V61LAG7-DLS -02niPCIOS
55PQ01-D8V61LAGPIDcitsalPniP-02
55JQ01-D8V61LAGCCLPdaeL-02
511
511
511
55JQ51-D8V61LAGCCLPdaeL-02
09PL51-D8V61LAGPIDcitsalPniP-02
09
09
55JQ52-D8V61LAGCCLPdaeL-02
09PL52-D8V61LAGPIDcitsalPniP-02
09
09
8V61LAG5-DJL
8V61LAG01-DPL
8V61LAG01-DJL
8V61LAG01-DLS niP-02CIOS
L51-D8V61LAGJ daeL-02CCLP
L51-D8V61LAGS
L52-D8V61LAGJ
L52-D8V61LAGS -02niPCIOS
Specifications GAL16V8
CCLPdaeL-02
PIDcitsalPniP-02
CCLPdaeL-02
PIDcitsalPniP-02
CCLPdaeL-02
CIOSniP-02
CCLPdaeL-02
Industrial Grade Specifications
)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP
5.775031
031
01017 031
031
512101031IPL51-D8V61LAGPIDcitsalPniP-02
031IJL51-D8V61LAGCCLPdaeL-02
02311156IPQ02-D8V61LAGPIDcitsalPniP-02
56IJQ02-D8V61LAGCCLPdaeL-02
52512156IPQ52-D8V61LAGPIDcitsalPniP-02
56IJQ52-D8V61LAGCCLPdaeL-02
031IPL52-D8V61LAGPIDcitsalPniP-02
031IJL52-D8V61LAGCCLPdaeL-02
8V61LAG7-DIPL
8V61LAG7-DIJL
8V61LAG01-DIPL
8V61LAG01-DIJL
Part Number Description
XXXXXXXX XX X X X
GAL16V8D
Device Name
Speed (ns)
PIDcitsalPniP-02
CCLPdaeL-02
PIDcitsalPniP-02
CCLPdaeL-02
_
Grade
Blank = Commercial
I = Industrial
Q = Quarter Power
PowerL = Low Power
Package
P = Plastic DIP
J = PLCC
S = SOIC
2
Output Logic Macrocell (OLMC)
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user.
There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
are illustrated in the following pages. Two global bits, SYN and
AC0, control the mode configuration for all macrocells. The XOR
bit of each macrocell controls the polarity of the output in any of the
three modes, while the AC1 bit of each of the macrocells controls
the input/output configuration. These two global and 16 individual architecture bits define all possible configurations in a GAL16V8
. The information given on these architecture bits is only to give
a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the
user should not need to directly manipulate these architecture bits.
The following is a list of the PAL architectures that the GAL16V8
can emulate. It also shows the OLMC mode under which the
GAL16V8 emulates the PAL architecture.
Specifications GAL16V8
PAL Architectures GAL16V8
Emulated by GAL16V8 Global OLMC Mode
16R8 Registered
16R6 Registered
16R4 Registered
16RP8 Registered
16RP6 Registered
16RP4 Registered
16L8 Complex
16H8 Complex
16P8 Complex
10L8 Simple
12L6 Simple
14L4 Simple
16L2 Simple
10H8 Simple
12H6 Simple
14H4 Simple
16H2 Simple
10P8 Simple
12P6 Simple
14P4 Simple
16P2 Simple
Compiler Support for OLMC
Software compilers support the three different global OLMC modes
as different device types. These device types are listed in the table
below. Most compilers have the ability to automatically select the
device type, generally based on the register usage and output
enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with
OE controlled by the product term will force the software to choose
the complex mode. The software will choose the simple mode only
when all outputs are dedicated combinatorial without OE control.
The different device types listed in the table can be used to override
the automatic device selection by the software. For further details,
refer to the compiler software manuals.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 1 and pin 1 1 are permanently configured
Registered Complex Simple Auto Mode Select
ABEL P16V8R P16V8C P16V8AS P16V8
CUPL G16V8MS G16V8MA G16V8AS G16V8
LOG/iC GAL16V8_R GAL16V8_C7 GAL16V8_C8 GAL16V8
OrCAD-PLD "Registered"
PLDesigner P16V8R
1
2
"Complex"
P16V8C
TANGO-PLD G16V8R G16V8C G16V8AS
as clock and output enable, respectively . These pins cannot be configured as dedicated inputs in the registered mode.
In complex mode pin 1 and pin 1 1 become dedicated inputs and
use the feedback paths of pin 19 and pin 12 respectively. Because
of this feedback path usage, pin 19 and pin 12 do not have the
feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
15 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
1
2
"Simple"
P16V8C
1
2
3
GAL16V8A
P16V8A
G16V8
1) Used with Configuration keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later .
3
Registered Mode
Specifications GAL16V8
In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.
Architecture configurations available in this mode are similar to the
common 16R8 and 16RP4 devices with various permutations of
polarity , I/O and register placement.
All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/O's are possible in this mode.
CLK
DQ
XOR
Q
Dedicated input or output functions can be implemented as subsets of the I/O function.
Registered outputs have eight product terms per output. I/O's have
seven product terms per output.
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product T erm Disable (PTD) fuses, are shown
on the logic diagram on the following page.
Registered Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 11 controls common OE for the registered outputs.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE for registered output configuration.
OE
Combinatorial Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically .
- AC1=1 defines this output configuration.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE for registered output configuration.
4
Registered Mode Logic Diagram
Specifications GAL16V8
DIP & PLCC Package Pinouts
1
201612840
24
0000
0224
2
0256
0480
3
0512
0736
4
0768
0992
5
1024
1248
6
2128
28
PTD
OLMC
19
XOR-2048
AC1-2120
OLMC
18
XOR-2049
AC1-2121
OLMC
17
XOR-2050
AC1-2122
OLMC
16
XOR-2051
AC1-2123
OLMC
15
XOR-2052
AC1-2124
1280
OLMC
1504
7
1536
XOR-2053
AC1-2125
OLMC
1760
8
1792
XOR-2054
AC1-2126
OLMC
2016
9
2191
XOR-2055
AC1-2127
OE
14
13
12
11
SYN-2192
AC0-2193
5
Complex Mode
Specifications GAL16V8
In the Complex mode, macrocells are configured as output only or
I/O functions.
Architecture configurations available in this mode are similar to the
common 16L8 and 16P8 devices with programmable polarity in
each macrocell.
Up to six I/O's are possible in this mode. Dedicated inputs or
outputs can be implemented as subsets of the I/O function. The
two outer most macrocells (pins 12 & 19) do not have input capa-
XOR
bility. Designs requiring eight I/O's can be implemented in the
Registered mode.
All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1 and
1 1 are always available as data inputs into the AND array.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
Combinatorial I/O Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 13 through Pin 18 are configured to this function.
Combinatorial Output Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically .
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 12 and Pin 19 are configured to this function.
6
Complex Mode Logic Diagram
Specifications GAL16V8
DIP & PLCC Package Pinouts
1
24
201612840
0000
0224
2
0256
0480
3
0512
0736
4
0768
0992
5
1024
1248
6
2128
PTD
28
OLMC
19
XOR-2048
AC1-2120
OLMC
18
XOR-2049
AC1-2121
OLMC
17
XOR-2050
AC1-2122
OLMC
16
XOR-2051
AC1-2123
OLMC
15
XOR-2052
AC1-2124
1280
OLMC
1504
7
1536
XOR-2053
AC1-2125
OLMC
1760
8
1792
XOR-2054
AC1-2126
OLMC
2016
9
XOR-2055
AC1-2127
14
13
12
11
2191
SYN-2192
AC0-2193
7
Loading...