Lattice ORCA ORT42G5 Technical Note

Evaluating the ORCA ORT42G5 with the

High-Speed SERDES Board

April 2004 Technical Note TN1069

Introduction

Contained in this package is information that will assist you in evaluating and verifying your ORCA® ORT42G5
designs using the Lattice High-Speed SERDES Board and the ORCAstra system bus control panel (available for
download from the Lattice web site at www.latticesemi.com/products/devtools/software/orcastra/index.cfm).

The Lattice High-Speed SERDES board supports a number of testing and evaluation setups for both the OR T42G5
and the ORSO42G5 . This document covers some common types of evaluation testing that can be performed on
the ORT42G5 device in raw (non-8b/10b) and 8b/10b modes. The tests include transmitter eye diagram measure­ment, 8b/10b near-end loop-back and SERDES-only (non 8b/10b), 8b/10b and aligned 8b/10b far-end loop-back.
All of the described evaluation setups will use the ort42g5v10ceval.bit bitstream. This bitstream should be included
with the package that you have downloaded from the Lattice web site at www.latticesemi.com/products/dev­tools/hardware/ort42g5-board/index.cfm. A unique ORCAstra macro is used to configure the device for each test.

PC and Evaluation Board Setup

This document assumes the ORCAstra application and bitstream programming software (ispVM®) are installed on
the user’s PC. It also assumes the baseline board configuration listed below. (The user is also encouraged to
experiment with other configurations.)

• All jumpers should be in their default position and default programming in the ispPAC®-POWR1208 as
described in the Evaluation Board User Manual. This will apply power in the recommended sequence and
provide 3.3V V

• ispDOWNLOAD® cable (pDS4102-DL2A) connected to the parallel port of the PC and to the ispVM connec­tor on the board (J30). The pDS4102-DL2A is included with the Lattice High Speed SERDES Board. Alter­nately, a HW-USB-1A ispDOWNLOAD cable can be used.)

• ORCAstra connected to the parallel or USB port on the PC and the ORCAstra Interface DB-25 or USB con­nector on the board (J108).

• External differential clock connected to the External System Clock SMA connectors (J87/J88 and J84/J85).

• External power should be provided from the Molex cable and power module.

to all banks.

DDIO

In addition, the following design-specific jumpers must be added. Note that references to “up” or “down” positions
on switches SW14-Cx are made with the assumption that the Lattice logo is to the right side when looking at the
board:

•Jumper pins 13 and 14 on J100 – This connects the global FPGA design’s active low input reset to switch
SW14-C4. Make sure SW14-C4 remains in the “down” position to disable the reset for the duration of the
evaluation.

•Jumper pins 16 and 17 on J100 – This connects the input “clear_errors_n” signal to switch SW14-C3. Flip­ping SW14-C3 from the “down” to the “up” position clears the “prbserror”(D9-1) and “pkterror”(D12-1) LEDS
described below.

•Jumper pins 19 and 20 on J100 – This connects the “farendlbad” input signal to switch SW14-C2. When
SW14-C2 is in the “down” position, channel AD is in far end loop-back mode.

•Jumper pins 22 and 23 on J100 – This connects the “farendlbac” input signal to switch SW14-C1. When
SW14-C1 is in the “down” position, channel AC is in far end loop-back mode.

•Jumper pins 2 and 3 on J100 – This connects the 27-1 PRBS error checker signal to the D9-1 LED. The
design can be programmed to check 27-1 PRBS data on either of channels AC or AD in the FPGA. D9-1 will
glow and remain lit anytime PRBS errors are detected. To clear D9-1, SW14-C3 needs to be flipped from
the “down” to the “up” position.

•Jumper pins 26 and 27 on J100 – This connects the 8b/10 packet error checker signal to the D12-1 LED.
The design can be programmed to check a predefined 8b/10 pack et data (generated on the tr ansmit side of

www.latticesemi.com

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tn1069_01

Evaluating the ORCA ORT42G5 with the

Lattice Semiconductor High-Speed SERDES Board

AC and AD) on either of channels AC or AD in the FPGA. D12-1 will glow and remain lit anytime packet
errors are detected. To clear D12-1, SW14-C3 needs to be flipped from the “down” to the “up” position.

Recommended Reading

•ORT42G5/ORT82G5 Data Sheet

• ORCA Series 4 FPGA Data Sheet

• ispVM System Software Data Sheet

• ispDOWNLOAD Cable Data Sheet

• High-Speed SERDES Briefcase Board User Manual

• ORCAstra System Bus Control Panel User Manual

Loop-back Description

Two types of high-speed loop-back are discussed in this User’s Manual: Near-end Loop-back and Far-end Loop­back. Near-end Loop-back (NELB) is defined as the data path from the FPGA Transmit into the SERDES and back
through the SERDES to the FPGA Receive as shown in Figure 1. The actual loop-back connection is made inter­nally at the interfaces to transmit and receive CML buffers of the ORT42G5 device.

Figure 1. Near-end Loop-back

ORT42G5

Serial Data

FPGA SERDES

32-bit Data

Reference Clock

Far-end Loop-back (FELB) is defined as the data path from the SERDES input, to the parallel data and back out
the SERDES as shown in Figure 2. Three different internal FELB path options are discussed, SERDES-only,
8b/10b and aligned 8b/10b.

Figure 2. Far-end Loop-back

ORT42G5

32-bit Data

FPGA Data SourceSERDES

Serial Data

Reference Clock

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Evaluating the ORCA ORT42G5 with the

Lattice Semiconductor High-Speed SERDES Board

ORT42G5V10CEVAL Bitstream

The ort42g5v10ceval.bit design has been created as a base for all the described evaluation setups for the
ORT42G5 device. As shown in Figure 3, the design takes advantage of the four SERDES channels available on
the board. The or t42g5v10ceval bitstream and the ORCAstra macros used in the tests should be included in the
package you have downloaded from www

Figure 3. ort42g5v10ceval Design

.latticesemi.com/products/devtools/hardware/ort42g5-board/index.cfm.

ORT42G5

PKTERROR

CLEAR_ERRORS_N

PRBSERROR

FARENDLBAx

RCK78

TCK78

8b/10b

PKT

or

7

-1

2

PRBS

ORCAstra

8b/10b

PKT
CHK

27-1

PRBS

CHK

sysBUS USI

40-bit data,

MRWDAx

40-bit data,

MRWDBx

FIFO

1

1

FPGA ASIC

TSYSCLKAx
TCK78A

RWCKBx

TSYSCLKBx
TCK78B

FIFO

Rx 8b/10b

RWCKAx

Tx 8b/10b

Rx 8b/10b

Tx 8b/10b

Rx SERDES

AC/AD

Tx SERDES

Rx SERDES

BC/BD

Tx SERDES

REFCLK_A

HDIN_Ax

HDOUT_Ax

REFCLK_B

HDIN_Bx

HDOUT_Bx

Data

Generator/

Analyzer

7

Either a PRBS 2

-1 or predefined 8b/10b generator in the FPGA logic can supply the transmit data source for all
tests. Channels AC and AD can be used in a transmit-only mode to observe the transmit eye diagram, or can be
used for loop-back testing.

Channels AC and AD use the FIFO in the Embedded Core for clock domain crossing. Dual channel alignment can
be performed on these two channels. The FIFO can also be b ypassed. In this case, the source of TCK78A needs to
be set in register 30A00 depending on whether channel AC or AD is being looked at.

In channels BC and BD, the clock domain crosses the FIFO in the FPGA logic. These channels can be used in the
SERDES-only mode or the 8b/10b mode.

Transmit Eye Diagram

One of the most fundamental evaluations that can be performed with the High-Speed SERDES Board is observa­tion and measurement of the data eye generated by the device. The ORT42G5 device’s major mode will produce
an 8b/10b encoded or PRBS 2
tests. Other data pattern eye diagrams can be measured using far-end loop-back setups discussed later in this
document.

7

-1 data eye. The same experimental setup can be used for near-end loop-back

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Evaluating the ORCA ORT42G5 with the

Lattice Semiconductor High-Speed SERDES Board

In this example, either channel AC or AD can be used to evaluate a data eye. In 8b/10b, both channels use the
8b/10b Transmit encoding block. IN PRBS 2

7

-1 mode, the 8b/10b transmit encoder is by-passed. The data eye can

then be observed on the AC or AD HDOUT CML pins.

Transmit Eye Diagram Setup Requirements

You will need the following to complete this evaluation:

•ORT42G5 board configured as described earlier.

•ort42g5v10ceval.bit bitstream and bitstream programming devices (ispDOWNLOAD cable and ispVM run­ning on a PC).

• ORCAstra GUI application in the ORT42G5 view (from the Options Menu)

• ORCAstra configuration file: 8b10b.fp1 for 8b/10b, raw_ac.fp1 for PRBS

• ORCAstra macro file: pktAC.fpm for 8b/10b, prbsAC for PRBS

• Scope to view data eye and high speed SMA cables (50
scope.

• Clock source capable of driving a CML input clock (77.76-155.52MHz) and SMA cables from the clock
source to the Lattice High Speed SERDES Board and to the trigger input of the scope. (Note: The eye mea­surements could alternately be made using a Serial Data Analyzer. In that case no trigger connection is
required.)

• 5V DC wall power supply.

• 1.5V DC supply for the bias tees.

A typical setup is shown in Figure 4.

Figure 4. Transmit Eye Diagram Setup

Ω

up to 3.0Gb/s) with bias tees at the input to the

5V DC 4A

Power Supply

ispDOWNLOAD

Cable

High-Speed SERDES Board

ORT42G5

DUT

HDOUTP_Bx
HDOUTN_Bx

REFCLKP_B

ORCAstra

Interface Cable

Computer

REFCLKN_B

-

+

Agilent 81130A

Clock Source

(or equivalent)

Agilent 86100B DCA

(or equivalent)

Picosecond

5575A

Bias Tee

High = 500mV

Low = 0V

155MHz

Agilent 816112

20GHz

Electrical

Module

(or equivalent)

Trigger In

Picosecond

5575A

Bias Tee

1.5V DC 0.5A

Power Supply

Note: Do not use
stand-alone bias tees
on channels (AA and BA).
Those channels have a
built-in bias tee.

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