Lattice ORCA ORSO42G5 Technical Note
Evaluating the ORCA ORSO42G5 with the
High-Speed SERDES Board
April 2004 Technical Note TN1070
Introduction
Contained in this package is information that will assist you in evaluating and verifying your ORCA® ORSO42G5
designs using the Lattice High-Speed SERDES Board and the ORCAstra system bus control panel (available for
download from the Lattice web site at www.latticesemi.com/products/devtools/software/orcastra/index.cfm).
The Lattice High-Speed SERDES Board supports a number of testing and evaluation setups for both the
ORT42G5 and the ORSO42G5. This document will cover some common types of evaluation testing that can be
performed on the ORSO42G5 device in SERDES-only and SONET modes. The tests include transmitter eye diagram measurement, SONET Near-end Loop-back and SERDES-only, SONET and Aligned SONET Far-end Loopback. All of the described evaluation setups use the orso4_felb6.bit bitstream. This bitstream is included with the
package you have downloaded from the Lattice web site at www.latticesemi.com/products/devtools/hardware/orso42g5-board/index.cfm. A unique ORCAstra macro is used to configure the device for each test.
PC and Evaluation Board Setup
This document assumes the ORCAstra application and bitstream programming software (ispVM®) are installed on
the user’s PC. It also assumes the baseline board configuration listed below. (The user is also encouraged to
experiment with other configurations.)
• All jumpers should be in their default position and default programming in the ispPAC®-POWR1208 as
described in the Evaluation Board User Manual. This will apply power in the recommended sequence and
provide 3.3V V
• ispDOWNLOAD® cable (pDS4102-DL2) connected to the parallel port of the PC and to the ispVM connector on the board (J30). The pDS4102-DL2 is included with the Lattice High-Speed SERDES Board. Alternately, a HW-USB-1A ispDOWNLOAD cable can be used.)
• ORCAstra connected to the parallel or USB port on the PC and the ORCAstra Interface DB-25 or USB connector on the board (J108).
• External differential clock connected to the External System Clock SMA connectors (J87/J88 and J84/J85).
• External power should be provided from the Molex cable and power module.
to all banks.
DDIO
Recommended Reading
• ORSO42G5 Data Sheet
• ORCA Series 4 FPGA Data Sheet
• ispVM System Software Data Sheet
• ispDOWNLOAD Cable Data Sheet
• High-Speed SERDES Briefcase Board User Manual
• ORCAstra System Bus Control Panel User Manual
Loop-back Description
Two types of high-speed loop-back are discussed in this document: Near-End Loop-back and Far-End Loop-back.
Near-End Loop-back (NELB) is defined as the data path from the FPGA Transmit into the SERDES and back
through the SERDES to the FPGA Receive as shown in Figure 1. The actual loop-back connection is made internally at the interfaces to the transmit and receive CML buffers of the ORSO42G5 device.
www.latticesemi.com
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tn1070_01
Evaluating the ORCA ORSO42G5 with the
Lattice Semiconductor High-Speed SERDES Board
Figure 1. Near-end Loop-back
ORSO42G5
Serial Data
FPGA SERDES
32-bit Data
Reference Clock
Far-end Loop-back (FELB) is defined as the data path from the SERDES input, to parallel data and back out the
SERDES as shown in Figure 2. Three different internal FELB path options are discussed: SERDES-only, SONET
and Aligned SONET.
Figure 2. Far-end Loop-back
ORSO42G5
32-bit Data
FPGA Data SourceSERDES
Serial Data
Reference Clock
ORSO4_FELB6 Bitstream
The orso4_felb6.bit design has been created as a base for all the described evaluation setups for the ORSO42G5
device. As shown in Figure 3, the design takes advantage of the four SERDES channels available on the board.
The orso4_felb6 bitstream and the ORCAstra macros used in the tests are included in the package downloaded
from www.latticesemi.com/products/devtools/hardware/orso42g5-board/index.cfm.
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Evaluating the ORCA ORSO42G5 with the
Lattice Semiconductor High-Speed SERDES Board
Figure 3. orso4_fleb6 Design
DOUTAD_OOF
DOUTAC_OOF
DOUTAC_FP
DOUTAC_B1_ERR
DOUTAC_SPE
DOUTBC_OOF
DOUTBD_OOF
RCK78B
TCK78B
ORSO42G5
STS48
FP Gen
ORCAstra sysBUS USI
32-bit data,
DOUTAx_FP
32-bit data,
DOUTBx_FP
FIFO
FPGA ASIC
TSYSCLKAx
TCK78A
RWCKBx
TSYSCLKBx
TCK78B
FIFO
Rx SONET
RWCKAx
Tx SONET
Rx SONET
Tx SONET
Rx SERDES
AC/AD
Tx SERDES
Rx SERDES
BC/BD
Tx SERDES
REFCLK_A
HDIN_Ax
HDOUT_Ax
REFCLK_B
HDIN_Bx
HDOUT_Bx
Data
Generator/
Analyzer
An STS48 frame generator in the FPGA logic can supply the transmit data source for all tests. Channels AC and
AD can be used in a Transmit-only mode to observe the transmit eye diagr am, or can be used for loop-back testing.
Channels AC and AD use the FIFO in the Embedded Core for clock domain crossing and can only be used in
SONET mode. Dual channel alignment can be performed on these two channels.
In channels BC and BD, the clock domain crosses the FIFO in the FPGA logic. These channels can be used in the
SERDES-only mode or the SONET mode.
Transmit Eye Diagram
One of the most fundamental evaluations that can be performed with the Lattice High-Speed SERDES Board is
observation and measurement of the data eye generated by the device. The ORSO42G5 device’s major mode will
produce a SONET scrambled data eye. The same experimental setup can be used for near-end loop-back tests.
Other data pattern eye diagrams can be measured using far-end loop-back setups discussed later in this document.
In this example, either channel AC or AD can be used to evaluate a SONET scrambled data eye. Both channels
use the SONET Transmit processing block, which includes a SONET scrambler. This scrambled data eye can then
be observed on the AC or AD HDOUT CML pins.
Evaluating the ORCA ORSO42G5 with the
Lattice Semiconductor High-Speed SERDES Board
Transmit Eye Diagram Setup Requirements
You will need the following to complete this evaluation:
• ORSO42G5 High-Speed SERDES Board configured as described earlier.
• Orso4_felb6.bit bitstream and bitstream programming devices (ispDOWNLOAD cable and ispVM running
on a PC).
• ORCAstra GUI application and tx_eye.fpm macro.
• Scope to view data eye and high speed SMA cables (50
scope.
• Clock source capable of driving a CML input clock (77.76-155.52MHz) and SMA cables from the clock
source to the Lattice High-Speed SERDES Board and to the trigger input of the scope. (Note: The eye measurements could alternately be made using a Serial Data Analyzer. In that case no trigger connection is
required.)
• 5V DC wall power supply.
• 1.5V DC supply for the bias tees
A typical setup is shown in Figure 4.
Ω
up to 3.0Gb/s) with bias tees at the input to the
Figure 4. Transmit Eye Diagram Setup
5V DC 4A
Power Supply
ispDOWNLOAD
Cable
High-Speed SERDES Board
ORSO42G5
DUT
HDOUTP_Bx
HDOUTN_Bx
REFCLKP_B
ORCAstra
Interface Cable
Computer
+
Agilent 86100B DCA
(or equivalent)
Picosecond
5575A
Bias Tee
REFCLKN_B
-
Agilent 81130A
Clock Source
High = 500mV
Low = 0V
155MHz
(or equivalent)
Agilent 816112
20GHz
Electrical
Module
(or equivalent)
Trigger In
Picosecond
5575A
Bias Tee
1.5V DC 0.5A
Power Supply
Note: Do not use
stand-alone bias tees
on channels (AA and BA).
Those channels have a
built-in bias tee.
Transmit Eye Diagram Test Procedures (SONET Scrambled Data Eye)
1. Connect the system as shown in Figure 4. The scope SMA cables should be connected to the
HDOUTP_Bx and HDOUTN_Bx SMA connectors on the board.
2. Power-up the system
3. Start the clock generator and provide a nominal 155.52MHz CML reference clock.
4. Download the orso4_felb6.bit bitstream into the ORSO42G5.
5. Run the tx_eye.fpm macro using the pull-down menu in the ORCAstra application. This macro will set up
the AC and AD channels in a SONET AUTO_TOH transmit mode using the SONET scrambler.
6. Observe the SONET scrambled data eye on the scope.
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