LATTICE M4A5 32/32-10 VC Datasheet

ispMACH™ 4A CPLD Family

High Performance E2CMOS®
In-System Programmable Logic

FEATURES

◆

High-performance, E2CMOS 3.3-V & 5-V CPLD families
Flexible architecture for rapid logic designs

◆

— Excellent First-Time-FitTM and refit feature
— SpeedLocking
— Central, input and output switch matrices for 100% routability and 100% pin-out retention

High speed

◆

— 5.0ns t

PD

— 182MHz f

◆

32 to 512 macrocells; 32 to 768 registers
44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages

◆

◆

Flexible architecture for a wide range of design styles

— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— Programmable polarity
— Reset/ preset swapping

Advanced capabilities for easy system integration

◆

— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
— Programmable pull-up or Bus-Friendly
— Hot-socketing
— Programmable security bit
— Individual output slew rate control

◆

Advanced E
Supported by ispDesignEXPERT

◆

— Supports HDL design methodologies with results optimized for ispMACH 4A
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success

Lattice and third-party hardware programming support

◆

— LatticePRO

equipment

— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,

and System General

TM

performance for guaranteed fixed timing

Commercial and 7.5ns t

CNT

2

CMOS process provides high-performance, cost-effective solutions

TM

software for in-system programmability support on PCs and automated test

TM

Industrial

PD

TM

inputs and I/Os

software for rapid logic development

Publication#
Amendment/

ISPM4A
0

Rev:

D

Issue Date:

August 2000

Table 1. ispMACH 4A Device Features

3.3 V Devices
Feature M4A3-32

2

M4A3-64

Macrocells 32 64 96 128 192 256 384 512
User I/O options 32 32/64
t

(ns) 5.0 5.5 5.5 5.5 6.0 5.5

PD

(MHz) 182 167 167 167 160 167 154 125

f

CNT

t

(ns) 4.0 4.0 4.0 4.0 4.5 4.0 4.5 5.5

COS

t

(ns) 3.0 3.5 3.5 3.5 3.5 3.5 3.5 5.0

SS

Static Power (mA) 20 25/52
JTAG Compliant Yes Yes Yes Yes Yes Yes Yes Yes
PCI Compliant Yes Yes Yes Yes Yes Yes Yes Yes

2

M4A3-96

1

1

2

M4A3-128

48 64 96 128

2

M4A3-192

2

M4A3-256 M4A3-384

2

40 55 85 110

/160

2

1

3

/150

/192

1

2

1

160/192 160/192/256

6.5 7.5

149/155 179

M4A3-512

1

5 V Devices
Feature M4A5-32

2

M4A5-64

2

M4A5-96

2

M4A5-128

2

M4A5-192

1

M4A5-256

2

Macrocells 32 64 96 128 192 256
User I/O options 32 32 48 64 96 128
t

(ns) 5.0 5.5 5.5 5.5 6.0 6.5

PD

(MHz) 182 167 167 167 160 154

f

CNT

t

(ns) 4.0 4.0 4.0 4.0 4.5 5.0

COS

t

(ns) 3.0 3.5 3.5 3.5 3.5 3.5

SS

Static Power (mA) 20 25 40 55 74 110
JTAG Compliant Yes Yes Yes Yes Yes Yes
PCI Compliant Yes Yes Yes Yes Yes Yes

Notes:

1. Advance information. Please contact a Lattice sales representative for details on availability.

2. Preliminary information.

3. M4A3-256/128 available now in 5.5ns. Contact factory for availability of 7.5ns M4A3-256/160 and M4A3-256/192

2 ispMACH 4A Family

GENERAL DESCRIPTION

The ispMACH
a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products
and software tools. The overall benefits for users are a guaranteed and predictable CPLD
solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer
densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention.
The ispMACH 4A families offer 5-V (M4A5-xxx) and 3.3-V (M4A3-xxx) operation.

ispMACH 4A products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std.

1149.1) interface. JTAG boundary scan testing also allows product testability on automated test
equipment for device connectivity.

All ispMACH 4A family members deliver First-Time-Fit and easy system integration with pin-out
retention after any design change and refit. For both 3.3-V and 5-V operation, ispMACH 4A
products can deliver guaranteed fixed timing as fast as 5.0 ns t
SpeedLocking feature when using up to 20 product terms per output (Table 2).

™

4A family from Lattice offers an exceptionally flexible architecture and delivers

and 182 MHz f

PD

through the

CNT

Device

3

M4A3-32

3

M4A5-32
M4A3-64/32

M4A5-64/32
M4A3-64/64

3

M4A3-96

3

M4A5-96
M4A3-128

M4A5-128
M4A3-192

M4A5-192
M4A3-256/128
M4A5-256/128
M4A3-256/192

M4A3-256/160
M4A3-384
M4A3-512

3
3

3
2

2
2

Table 2. ispMACH 4A Speed Grades

Speed Grade

-5 -55 -6 -65 -7 -10 -12 -14

C C, I C, I I

3
3

2

3
3
2

2

C C, I C, I I

C C, I C, I I

C C, I C, I I

C C, I C, I I

C C, I C, I I

C C C, I C, I I

C C C, I I

C C, I I

C C, I C, I I

C C, I C, I I

Notes:

1. C = Commercial, I = Industrial

2. Advance information. Please contact a Lattice sales representative for details on availability.

3. Preliminary information.

ispMACH 4A Family 3

The ispMACH 4A family offers 20 density-I/O combinations in Thin Quad Flat Pack (TQFP),
Plastic Quad Flat Pack (PQFP), Plastic Leaded Chip Carrier (PLCC), Ball Grid Array (BGA), fine­pitch BGA (fpBGA), and chip-array BGA (caBGA) packages ranging from 44 to 388 pins (Table

3). It also offers I/O safety features for mixed-voltage designs so that the 3.3-V devices can accept
5-V inputs, and 5-V devices do not overdrive 3.3-V inputs. Additional features include Bus­Friendly inputs and I/Os, a programmable power-down mode for extra power savings and
individual output slew rate control for the highest speed transition or for the lowest noise
transition.

Table 3. ispMACH 4A Package and I/O Options

(Number of I/Os and dedicated inputs in Table)

3.3 V Devices

2

Package M4A3-32

44-pin PLCC 32+2 32+2
44-pin TQFP 32+2 32+2
48-pin TQFP 32+2 32+2
100-pin TQFP 64+6

M4A3-64 M4A3-96

2
2
2
1

100-pin PQFP 64+6
100-ball caBGA 64+6
144-pin TQFP 96+16
144-ball fpBGA 96+16
208-pin PQFP 128+14
256-ball fpBGA 128+14
256-ball BGA 128+14

2

M4A3-128 M4A3-192 M4A3-256 M4A3-384

48+8 64+6

1

M4A3-512

2
2
1

2
1

2

1

, 160

2

, 192

2

160 160

1

192 192
192

388-ball fpBGA 256

5 V Devices

Package M4A5-32

2

M4A5-64

2

M4A5-96

2

M4A5-128

2

M4A5-192

1

M4A5-256

2

44-pin PLCC 32+2 32+2
44-pin TQFP 32+2 32+2
48-pin TQFP 32+2 32+2
100-pin TQFP 48+8 64+6
100-pin PQFP 64+6
144-pin TQFP 96+16
208-pin PQFP 128+14
256-ball BGA 128+14

1

Note:

1. Advance information. Please contact a Lattice sales representative for details on availability.

2. Preliminary information.

4 ispMACH 4A Family

FUNCTIONAL DESCRIPTION

The fundamental architecture of ispMACH 4A devices (Figure 1) consists of multiple, optimized

®

blocks interconnected by a central switch matrix. The central switch matrix allows

PAL
communication between PAL blocks and routes inputs to the PAL blocks. Together, the PAL
blocks and central switch matrix allow the logic designer to create large designs in a single
device instead of having to use multiple devices.

The key to being able to make effective use of these devices lies in the interconnect schemes.
In the ispMACH 4A architecture, the macrocells are flexibly coupled to the product terms
through the logic allocator, and the I/O pins are flexibly coupled to the macrocells due to the
output switch matrix. In addition, more input routing options are provided by the input switch
matrix. These resources provide the flexibility needed to fit designs efficiently.

PAL Block

Clock/Input

Pins

Note 3

Dedicated
Input Pins

Clock

Generator

33/
34/

36

Logic
Array

Input

Switch

Matrix

Central Switch Matrix

Logic

Allocator

with XOR

4

Output/

Buried

Macrocells

16

PAL Block

PAL Block

Note 2

I/O

1616

8

Note 1

Output Switch Matrix

16

I/O Cells

Pins

I/O

Pins

I/O

Pins

17466G-001

Figure 1. ispMACH 4A Block Diagram and PAL Block Structure

Notes:

1. 16 for ispMACH 4A devices with 1:1 macrocell-I/O cell ratio (see next page).

2. Block clocks do not go to I/O cells in M4A(3,5)-32/32.

3. M4A(3,5)-192, M4A(3,5)-256, M4A3-384, and M4A3-512 have dedicated clock pins which cannot be used as inputs and do
not connect to the central switch matrix.

ispMACH 4A Family 5

Table 4. Architectural Summary of ispMACH 4A devices

ispMACH 4A Devices

M4A3-64/32, M4A5-64/32

M4A3-96/48, M4A5-96/48
M4A3-128/64, M4A5-128/64
M4A3-192/96, M4A5-192/96

M4A3-256/128, M4A5-256/128

M4A3-384
M4A3-512

Macrocell-I/O Cell
Ratio

Input Switch Matrix Yes Yes
Input Registers Yes No
Central Switch Matrix Yes Yes
Output Switch Matrix Yes Yes

2:1 1:1

M4A3-32/32
M4A5-32/32

M4A3-64/64
M4A3-256/160
M4A3-256/192

1

The Macrocell-I/O cell ratio is defined as the number of macrocells versus the number of I/O
cells internally in a PAL block (Table 4).

The central switch matrix takes all dedicated inputs and signals from the input switch matrices
and routes them as needed to the P AL blocks. Feedback signals that return to the same P AL block
still must go through the central switch matrix. This mechanism ensures that PAL blocks in
ispMACH 4A devices communicate with each other with consistent, predictable delays.

The central switch matrix makes a ispMACH 4A device more advanced than simply several PAL
devices on a single chip. It allows the designer to think of the device not as a collection of
blocks, but as a single programmable device; the software partitions the design into PAL blocks
through the central switch matrix so that the designer does not have to be concerned with the
internal architecture of the device.

Each PAL block consists of:

◆

Product-term array

◆

Logic allocator

◆

Macrocells

◆

Output switch matrix

◆

I/O cells

◆

Input switch matrix

◆

Clock generator

Notes:

1. M4A3-64/64 internal switch matrix functionality embedded in central switch matrix.

6 ispMACH 4A Family

Product-Term Array

The product-term array consists of a number of product terms that form the basis of the logic
being implemented. The inputs to the AND gates come from the central switch matrix (Table 5),
and are provided in both true and complement forms for efficient logic implementation.

Table 5. PAL Block Inputs

Device Number of Inputs to PAL Block

M4A3-32/32 and M4A5-32/32
M4A3-64/32 and M4A5-64/32
M4A3-64/64
M4A3-96/48 and M4A5-96/48
M4A3-128/64 and M4A5-128/64

M4A3-192/96 and M4A5-192/96
M4A3-256/128 and M4A5-256/128

M4A3-256/160 and M4A3-256/192
M4A3-384
M4A3-512

33
33
33
33
33

34
34

36
36
36

Logic Allocator

Within the logic allocator, product terms are allocated to macrocells in “product term clusters.”
The availability and distribution of product term clusters are automatically considered by the
software as it fits functions within a PAL block. The size of a product term cluster has been
optimized to provide high utilization of product terms, making complex functions using many
product terms possible. Yet when few product terms are used, there will be a minimal number
of unused—or wasted—product terms left over. The product term clusters available to each
macrocell within a PAL block are shown in Tables 6 and 7.

Each product term cluster is associated with a macrocell. The size of a cluster depends on the
configuration of the associated macrocell. When the macrocell is used in synchronous mode
(Figure 2a), the basic cluster has 4 product terms. When the associated macrocell is used in
asynchronous mode (Figure 2b), the cluster has 2 product terms. Note that if the product term
cluster is routed to a different macrocell, the allocator configuration is not determined by the
mode of the macrocell actually being driven. The configuration is always set by the mode of the
macrocell that the cluster will drive if not routed away, regardless of the actual routing.

In addition, there is an extra product term that can either join the basic cluster to give an
extended cluster, or drive the second input of an exclusive-OR gate in the signal path. If included
with the basic cluster, this provides for up to 20 product terms on a synchronous function that
uses four extended 5-product-term clusters. A similar asynchronous function can have up to 18
product terms.

When the extra product term is used to extend the cluster, the value of the second XOR input
can be programmed as a 0 or a 1, giving polarity control. The possible configurations of the logic
allocator are shown in Figures 3 and 4.

ispMACH 4A Family 7

Table 6. Logic Allocator for All ispMACH 4A Devices (except M4A(3,5)-32/32)

Output Macrocell Available Clusters Output Macrocell Available Clusters

M

0

M

1

M

2

M

3

M

4

M

5

M

6

M

7

C

, C

, C

0

1

C

, C

, C

0

1

2

C1, C2, C3, C
C2, C3, C4, C
C3, C4, C5, C
C4, C5, C6, C
C5, C6, C7, C
C6, C7, C8, C

2

, C

3
4
5
6
7
8
9

M

8

M

9

M

10

M

11

M

12

M

13

M

14

M

15

C

,

C

, C

, C

7

8

9

C8, C9, C10, C

C9, C10, C11, C
C10, C11, C12, C
C11, C12, C13, C
C12, C13, C14, C

C13, C14, C

C14, C

15

10

11

12

13
14
15

15

Table 7. Logic Allocator for M4A(3,5)-32/32

Output Macrocell Available Clusters Output Macrocell Available Clusters

M

0

M

1

M

2

M

3

M

4

M

5

M

6

M

7

C0, C1, C
C0, C1, C2, C
C1, C2, C3, C
C2, C3, C4, C
C3, C4, C5, C
C4, C5, C6, C

C5, C6, C

C6, C

7

2

3
4
5
6
7

7

M

8

M

9

M

10

M

11

M

12

M

13

M

14

M

15

C8, C9, C

10

C8, C9, C10, C

C9, C10, C11, C
C10, C11, C12, C
C11, C12, C13, C
C12, C13, C14, C

C13, C14, C

C14, C

15

11

12

13
14
15

15

Basic Product

Term Cluster

Extra

Product

Term

Basic Product

Term Cluster

Extra

Product

Term

n

0 Default

To n-1

To n-2

To n+1

From n-1

From n+1

From n+2

Prog. Polarity

n

Logic Allocator

0 Default

n

To Macrocell

a. Synchronous Mode

To n-1

To n-2

From n-1

nn

0 Default

To n+1

From n+1

From n+2

Logic Allocator

0 Default

n

To Macrocell

17466G-005

b. Asynchronous Mode

Figure 2. Logic Allocator: Configuration of Cluster “n” Set by Mode of Macrocell “n”

8 ispMACH 4A Family

Prog. Polarity

17466G-006

a. Basic cluster with XOR

d. Basic cluster routed away;

single-product-term, active high

Figure 3. Logic Allocator Configurations: Synchronous Mode

a. Basic cluster with XOR

b. Extended cluster, active high c. Extended cluster, active low

0

e. Extended cluster routed away

17466G-007

b. Extended cluster, active high c. Extended cluster, active low

0

d. Basic cluster routed away;

single-product-term, active high

e. Extended cluster routed away

17466G-008

Figure 4. Logic Allocator Configurations: Asynchronous Mode

Note that the configuration of the logic allocator has absolutely no impact on the speed of the
signal. All configurations have the same delay. This means that designers do not have to decide
between optimizing resources or speed; both can be optimized.

If not used in the cluster, the extra product term can act in conjunction with the basic cluster to
provide XOR logic for such functions as data comparison, or it can work with the D-,T-type flip­flop to provide for J-K, and S-R register operation. In addition, if the basic cluster is routed to
another macrocell, the extra product term is still available for logic. In this case, the first XOR
input will be a logic 0. This circuit has the flexibility to route product terms elsewhere without
giving up the use of the macrocell.

Product term clusters do not “wrap” around a PAL block. This means that the macrocells at the
ends of the block have fewer product terms available.

ispMACH 4A Family 9

Macrocell

The macrocell consists of a storage element, routing resources, a clock multiplexer, and
initialization control. The macrocell has two fundamental modes: synchronous and
asynchronous (Figure 5). The mode chosen only affects clocking and initialization in the
macrocell.

Power-Up

Reset

PAL-Block

Initialization

Product Terms

Common PAL-block resource

Individual macrocell resources

From Logic Allocator

From

PAL-Clock

Generator

Block CLK0
Block CLK1
Block CLK2
Block CLK3

SWAP

AP AR

D/T/L

To Output and Input
Switch Matrices

Q

17466G-009

Individual

Initialization

Product Term

From Logic

Allocator

From PAL-Block

Clock Generator

Individual Clock

Product Term

Power-Up

Reset

Block CLK0
Block CLK1

a. Synchronous mode

AP AR

D/T/L

b. Asynchronous mode

Q

Figure 5. Macrocell

To Output and Input
Switch Matrices

17466G-010

In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous
mode will generally be used, since it provides more product terms in the allocator.

10 ispMACH 4A Family

The flip-flop can be configured as a D-type or T-type latch. J-K or S-R registers can be
synthesized. The primary flip-flop configurations are shown in Figure 6, although others are
possible. Flip-flop functionality is defined in Table 8. Note that a J-K latch is inadvisable as it will
cause oscillation if both J and K inputs are HIGH.

a. D-type with XOR

c. Latch with XOR

AP AR

DQ

AP AR

LQ

G

AP AR

DQ

b. D-type with programmable D polarity

AP AR

LQ

G

d. Latch with programmable D polarity

AP AR

TQ

e. T-type with programmable T polarity

g. Combinatorial with programmable polarity

Figure 6. Primary Macrocell Configurations

f. Combinatorial with XOR

17466G-011

ispMACH 4A Family 11

Table 8. Register/Latch Operation

0,1, ↓ (↑)

↑ (↓)
↑ (↓)

0, 1, ↓ (↑)

↑ (↓)
↑ (↓)

1(0)
0(1)
0(1)

1

Q+

Q

0
1

Q
Q
Q

Q

0
1

Configuration Input(s) CLK/LE

D-type Register

T-type Register

D-type Latch

Note:

1. Polarity of CLK/LE can be programmed

D=X
D=0
D=1

T=X
T=0
T=1

D=X
D=0
D=1

Although the macrocell shows only one input to the register, the XOR gate in the logic allocator
allows the D-, T-type register to emulate J-K, and S-R behavior. In this case, the available product
terms are divided between J and K (or S and R). When configured as J-K, S-R, or T-type, the
extra product term must be used on the XOR gate input for flip-flop emulation. In any register
type, the polarity of the inputs can be programmed.

The clock input to the flip-flop can select any of the four P AL block clocks in synchronous mode,
with the additional choice of either polarity of an individual product term clock in the
asynchronous mode.

The initialization circuit depends on the mode. In synchronous mode (Figure 7), asynchronous
reset and preset are provided, each driven by a product term common to the entire PAL block.

PAL-Block

Initialization

Product Terms

Power-Up

Reset

PAL-Block

Initialization

Product Terms

AP

D/T/L

a. Power-up reset

AR

Q

17466G-012 17466G-013

Figure 7. Synchronous Mode Initialization Configurations

Power-Up

Preset

b. Power-up preset

AP

D/L

AR

Q

12 ispMACH 4A Family

A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged,
providing flexibility. In asynchronous mode (Figure 8), a single individual product term is
provided for initialization. It can be selected to control reset or preset.

Power-Up

Preset

b. Preset

AP

D/L/T

AR

Q

Individual

Reset

Product Term

Power-Up

Reset

a. Reset

AP

D/L/T

Individual

Preset

Product Term

AR

Q

17466G-014 17466G-015

Figure 8. Asynchronous Mode Initialization Configurations

Note that the reset/preset swapping selection feature effects power-up reset as well. The
initialization functionality of the flip-flops is illustrated in Table 9. The macrocell sends its data
to the output switch matrix and the input switch matrix. The output switch matrix can route this
data to an output if so desired. The input switch matrix can send the signal back to the central
switch matrix as feedback.

Table 9. Asynchronous Reset/Preset Operation

AR AP CLK/LE

0 0 X See Table 8
01X1
10X0
11X0

Note:

1. Transparent latch is unaffected by AR, AP

1

Q+

ispMACH 4A Family 13

Output Switch Matrix

The output switch matrix allows macrocells to be connected to any of several I/O cells within a
PAL block. This provides high flexibility in determining pinout and allows design changes to
occur without effecting pinout.

In ispMACH 4A devices with 2:1 Macrocell-I/O cell ratio, each PAL block has twice as many
macrocells as I/O cells. The ispMACH 4A output switch matrix allows for half of the macrocells
to drive I/O cells within a PAL block, in combinations according to Figure 9. Each I/O cell can
choose from eight macrocells; each macrocell has a choice of four I/O cells. The ispMACH 4A
devices with 1:1 Macrocell-I/O cell ratio allow each macrocell to drive one of eight I/O cells
(Figure 9).

macrocells

Each I/O cell can

choose one of 8

macrocells in

all ispMACH 4A

devices.

MUX

M0
M1
M2
M3
M4
M5
M6
M7

I/O cell

M8

M9
M10
M11
M12
M13
M14
M15

Each macrocell can drive

one of 4 I/O cells in

ispMACH 4A devices with

2:1 macrocell-I/O cell ratio.

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7

M0
M1
M2
M3
M4
M5
M6
M7
M8

M9
M10
M11
M12
M13
M14
M15

Each macrocell can drive

one of 8 I/O cells in

ispMACH 4A devices with 1:1

macrocell-I/O cell ratio except

M4A(3, 5)-32/32 devices.

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15

M0
M1
M2
M3
M4
M5
M6
M7

M8

M9
M10
M11
M12
M13
M14
M15

Each macrocell can drive

one of 8 I/O cells in

M4A(3, 5)-32/32 devices.

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7

I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15

Figure 9. ispMACH 4A Output Switch Matrix

Table 10. Output Switch Matrix Combinations for ispMACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio

Macrocell Routable to I/O Cells

M0, M1 I/O0, I/O5, I/O6, I/O7
M2, M3 I/O0, I/O1, I/O6, I/O7
M4, M5 I/O0, I/O1, I/O2, I/O7
M6, M7 I/O0, I/O1, I/O2, I/O3
M8, M9 I/O1, I/O2, I/O3, I/O4

14 ispMACH 4A Family

Table 10. Output Switch Matrix Combinations for ispMACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio

Macrocell Routable to I/O Cells

M10, M11 I/O2, I/O3, I/O4, I/O5
M12, M13 I/O3, I/O4, I/O5, I/O6
M14, M15 I/O4, I/O5, I/O6, I/O7

I/O Cell Available Macrocells

I/O0 M0, M1, M2, M3, M4, M5, M6, M7
I/O1 M2, M3, M4, M5, M6, M7, M8, M9
I/O2 M4, M5, M6, M7, M8, M9, M10, M11
I/O3 M6, M7, M8, M9, M10, M11, M12, M13
I/O4 M8, M9, M10, M11, M12, M13, M14, M15
I/O5 M0, M1, M10, M11, M12, M13, M14, M15
I/O6 M0, M1, M2, M3, M12, M13, M14, M15
I/O7 M0, M1, M2, M3, M4, M5, M14, M15

Table 11. Output Switch Matrix Combinations for M4A3-256/160 and M4A3-256/192

Macrocell Routable to I/O Cells

M0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M1 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M2 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M3 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M4 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M5 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M6 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M7 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M8 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15

M9 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M10 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M11 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M12 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M13 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M14 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M15 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15

I/O Cell Available Macrocells

I/O0 M0 M1 M2 M3 M4 M5 M6 M7
I/O1 M0 M1 M2 M3 M4 M5 M6 M7
I/O2 M0 M1 M2 M3 M4 M5 M6 M7
I/O3 M0 M1 M2 M3 M4 M5 M6 M7
I/O4 M0 M1 M2 M3 M4 M5 M6 M7
I/O5 M0 M1 M2 M3 M4 M5 M6 M7
I/O6 M0 M1 M2 M3 M4 M5 M6 M7

ispMACH 4A Family 15

Table 11. Output Switch Matrix Combinations for M4A3-256/160 and M4A3-256/192

Macrocell Routable to I/O Cells

I/O7 M0 M1 M2 M3 M4 M5 M6 M7
I/O8 M8 M9 M10 M11 M12 M13 M14 M15
I/O9 M8 M9 M10 M11 M12 M13 M14 M15

I/O10 M8 M9 M10 M11 M12 M13 M14 M15
I/O11 M8 M9 M10 M11 M12 M13 M14 M15
I/O12 M8 M9 M10 M11 M12 M13 M14 M15
I/O13 M8 M9 M10 M11 M12 M13 M14 M15
I/O14 M8 M9 M10 M11 M12 M13 M14 M15
I/O15 M8 M9 M10 M11 M12 M13 M14 M15

Table 12. Output Switch Matrix Combinations for M4A(3,5)-32/32

Macrocell Routable to I/O Cells

M0, M1, M2, M3, M4, M5, M6, M7 I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7

M8, M9, M10, M11, M12, M13, M14, M15 I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15

I/O Cell Available Macrocells

I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7 M0, M1, M2, M3, M4, M5, M6, M7

I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15 M8, M9, M10, M11, M12, M13, M14, M15

Table 13. Output Switch Matrix Combinations for M4A3-64/64

Macrocell Routable to I/O Cells

MO, M1 I/O0, I/O1, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15

M2, M3 I/O0, I/O1, I/O2, I/O3, I/O12, I/O13, I/O14, I/O15
M4, M5 I/O0, I/O1, I/O2,I/O3, I/O4,I/O5, I/O14, I/O15
M6, M7 I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7

M8, M9 I/O2, I/O3, I/O4, I/O5, I/O6, I/O7, I/O8, I/O9
M10, M11 I/O4, I/O5, I/O6, I/O7, I/O8, I/O9, I/O10, I/O11
M12, M13 I/O6, I/O7, I/O8, I/O9, I/O10, I/O11, I/O12, I/O13
M14, M15 I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15

I/O Cell Available Macrocells

I/O0, I/O1 M0, M1, M2, M3, M4, M5, M6, M7
I/O2, I/O3 M2, M3, M4, M5, M6, M7, M8, M9
I/O4, I/O5 M4, M5, M6, M7, M8, M9, M10, M11
I/O6, I/O7 M6, M7, M8, M9, M10, M11, M12, M13
I/O8, I/O9 M8, M9, M10, M11, M12, M13, M14, M15

I/O10, I/O11 M0, M1, M10, M11, M12, M13, M14, M15
I/O12, I/O13 M0, M1, M2, M3, M12, M13, M14, M15
I/O14, I/O15 M0, M1, M2, M3, M4, M5, M14, M15

16 ispMACH 4A Family

I/O Cell

The I/O cell (Figures 10 and 11) simply consists of a programmable output enable, a feedback
path, and flip-flop (except ispMACH 4A devices with 1:1 macrocell-I/O cell ratio). An individual
output enable product term is provided for each I/O cell. The feedback signal drives the input
switch matrix.

Individual

Output Enable

Product Term

From Output

Switch Matrix

To

Input
Switch
Matrix

Q

D/L

Block CLK0
Block CLK1
Block CLK2
Block CLK3

Power-up reset

Individual

Output Enable

Product Term

From Output

Switch Matrix

To

Input
Switch
Matrix

17466G-017 17466G-018

Figure 10. I/O Cell for ispMACH 4A Devices with 2:1

Macrocell-I/O Cell Ratio

Figure 11. I/O Cell for ispMACH 4A Devices with 1:1

Macrocell-I/O Cell Ratio

The I/O cell (Figure 10) contains a flip-flop, which provides the capability for storing the input
in a D-type register or latch. The clock can be any of the PAL block clocks. Both the direct and
registered versions of the input are sent to the input switch matrix. This allows for such functions
as “time-domain-multiplexed” data comparison, where the first data value is stored, and then the
second data value is put on the I/O pin and compared with the previous stored value.

Note that the flip-flop used in the ispMACH 4A I/O cell is independent of the flip-flops in the
macrocells. It powers up to a logic low.

Zero-Hold-Time Input Register

The ispMACH 4A devices have a zero-hold-time (ZHT) fuse which controls the time delay
associated with loading data into all I/O cell registers and latches. When programmed, the ZHT
fuse increases the data path setup delays to input storage elements, matching equivalent delays
in the clock path. When the fuse is erased, the setup time to the input storage element is
minimized. This feature facilitates doing worst-case designs for which data is loaded from
sources which have low (or zero) minimum output propagation delays from clock edges.

ispMACH 4A Family 17

Input Switch Matrix

The input switch matrix (Figures 12 and 13) optimizes routing of inputs to the central switch
matrix. Without the input switch matrix, each input and feedback signal has only one way to
enter the central switch matrix. The input switch matrix provides additional ways for these
signals to enter the central switch matrix.

From Input Cell

Direct

From Macrocell 2

From Macrocell 1

Registered/Latched

From Macrocell

From I/O Pin

To Central Switch Matrix

17466G-002 17466G-003

Figure 12. ispMACH 4A with 2:1 Macrocell-I/O Cell

Ratio - Input Switch Matrix

To Central Switch Matrix

Figure 13. ispMACH 4A with 1:1 Macrocell-I/O Cell

Ratio - Input Switch Matrix

18 ispMACH 4A Family

PAL Block Clock Generation

Each ispMACH 4A device has four clock pins that can also be used as inputs. These pins drive
a clock generator in each P AL block (Figure 14). The clock generator provides four clock signals
that can be used anywhere in the PAL block. These four PAL block clock signals can consist of
a large number of combinations of the true and complement edges of the global clock signals.
Table 14 lists the possible combinations.

GCLK0

GCLK1

GCLK2

GCLK3

Figure 14. PAL Block Clock Generator

1. M4A(3,5)-32/32 and M4A(3,5)-64/32 have only two clock pins, GCLK0 and GCLK1. GCLK2 is tied to GCLK0, and GCLK3 is
tied to GCLK1.

Table 14. PAL Block Clock Combinations

Block CLK0 Block CLK1 Block CLK2 Block CLK3

GCLK0
GCLK1
GCLK0
GCLK1

X
X
X
X

GCLK1
GCLK1
GCLK0
GCLK0

X
X
X
X

Block CLK0
(GCLK0 or GCLK1)

Block CLK1
(GCLK1 or GCLK0)

Block CLK2
(GCLK2 or GCLK3)

Block CLK3
(GCLK3 or GCLK2)

1

1

X
X
X

X
GCLK2 (GCLK0)
GCLK3

(GCLK1)
GCLK2 (GCLK0)
GCLK3

(GCLK1)

17466G-004

X
X
X

X
GCLK3 (GCLK1)
GCLK3 (GCLK1)
GCLK2

(GCLK0)

GCLK2

(GCLK0)

Note:

1. Values in parentheses are for the M4A(3,5)-32/32 and M4A(3,5)-64/32.

This feature provides high flexibility for partitioning state machines and dual-phase clocks. It
also allows latches to be driven with either polarity of latch enable, and in a master-slave
configuration.

ispMACH 4A Family 19

ispMACH 4A TIMING MODEL

The primary focus of the ispMACH 4A timing model is to accurately represent the timing in a
ispMACH 4A device, and at the same time, be easy to understand. This model accurately
describes all combinatorial and registered paths through the device, making a distinction
between internal feedback and external feedback. A signal uses internal feedback when it is fed
back into the switch matrix or block without having to go through the output buffer. The input
register specifications are also reported as internal feedback. When a signal is fed back into the
switch matrix after having gone through the output buffer, it is using external feedback.

The parameter, t

, is defined as the time it takes to go from feedback through the output buffer

BUF

to the I/O pad. If a signal goes to the internal feedback rather than to the I/O pad, the parameter
designator is followed by an “i”. By adding t
is derived. For example, t

PD

= t

PDi

+ t

. A diagram representing the modularized ispMACH 4A

BUF

to this internal parameter, the external parameter

BUF

timing model is shown in Figure 15. Refer to the application note entitled MACH 4 Timing and
High Speed Design for a more detailed discussion about the timing parameters.

(External Feedback)

(Internal Feedback)

COMB/DFF/TFF/

IN

BLK CLK

INPUT REG/

INPUT LATCH

t

SIRS

t

HIRS

t

SIL

t

HIL

t

SIRZ

t

HIRZ

t

SILZ

t

HILZ

t

PDILi

t

ICOSi

t

IGOSi

t

PDILZi

Q

Central

Switch

Matrix

LATCH/SR*/JK*

*emulated

t

t

SS(T)

PDi

t

PDLi

t

CO(S/A)i

t

GO(S/A)i

t

SRi

Q

t

SA(T)

t

H(S/A)

t

S(S/A)L

t

t

PL

H(S/A)L

t

SRR

S/R

t

BUF

t

SLW

t

EA

t

ER

OUT

17466G-025

Figure 15. ispMACH 4A Timing Model

SPEEDLOCKING FOR GUARANTEED FIXED TIMING

The ispMACH 4A architecture allows allocation of up to 20 product terms to an individual
macrocell with the assistance of an XOR gate without incurring additional timing delays.

The design of the switch matrix and PAL blocks guarantee a fixed pin-to-pin delay that is
independent of the logic required by the design. Other competitive CPLDs incur serious timing
delays as product terms expand beyond their typical 4 or 5 product term limits. Speed and
SpeedLocking combine to give designs easy access to the performance required in today’s
designs.

20 ispMACH 4A Family

IEEE 1149.1-COMPLIANT BOUNDARY SCAN TESTABILITY

All ispMACH 4A devices have boundary scan cells and are compliant to the IEEE 1149.1 standard.
This allows functional testing of the circuit board on which the device is mounted through a
serial scan path that can access all critical logic nodes. Internal registers are linked internally,
allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be
captured and shifted out for verification. In addition, these devices can be linked into a board­level serial scan path for more complete board-level testing.

IEEE 1149.1-COMPLIANT IN-SYSTEM PROGRAMMING

Programming devices in-system provides a number of significant benefits including: rapid
prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications.
All ispMACH 4A devices provide In-System Programming (ISP) capability through their
Boundary ScanTest Access Ports. This capability has been implemented in a manner that ensures
that the port remains compliant to the IEEE 1149.1 standard. By using IEEE 1149.1 as the
communication interface through which ISP is achieved, customers get the benefit of a standard,
well-defined interface.

ispMACH 4A devices can be programmed across the commercial temperature and voltage range.
The PC-based LatticePRO software facilitates in-system programming of ispMACH 4A devices.
LatticePRO takes the JEDEC file output produced by the design implementation software, along
with information about the JTAG chain, and creates a set of vectors that are used to drive the
JT AG chain. LatticePRO software can use these vectors to drive a JT AG chain via the parallel port
of a PC. Alternatively, LatticePRO software can output files in formats understood by common
automated test equipment. This equpment can then be used to program ispMACH 4A devices
during the testing of a circuit board.

PCI COMPLIANT

ispMACH 4A devices in the -5/-55/-6/-65/-7/-10/-12 speed grades are compliant with the PCI
Local Bus Specification version 2.1, published by the PCI Special Interest Group (SIG). The 5-V

devices are fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI
condition to clamp the inputs as they rise above V

because of their 5-V input tolerant feature.

CC

SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS

Both the 3.3-V and 5-V VCC ispMACH 4A devices are safe for mixed supply voltage system
designs. The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V,
while they accept inputs from other 3.3-V devices. The 3.3-V device will accept inputs up to 5.5
V. Both the 5-V and 3.3-V versions have the same high-speed performance and provide easy-to­use mixed-voltage design capability.

PULL UP OR BUS-FRIENDLY INPUTS AND I/Os

All ispMACH 4A devices have inputs and I/Os which feature the Bus-Friendly circuitry
incorporating two inverters in series which loop back to the input. This double inversion weakly
holds the input at its last driven logic state. While it is good design practice to tie unused pins
to a known state, the Bus-Friendly input structure pulls pins away from the input threshold
voltage where noise can cause high-frequency switching. At power-up, the Bus-Friendly latches
are reset to a logic level “1.” For the circuit diagram, please refer to the document entitled MACH
Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site.

ispMACH 4A Family 21

All ispMACH 4A devices have a programmable bit that configures all inputs and I/Os with either
pull-up or Bus-Friendly characteristics. If the device is configured in pull-up mode, all inputs
and I/O pins are weakly pulled up. For the circuit diagram, please refer to the document entitled
MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site.

POWER MANAGEMENT

Each individual PAL block in ispMACH 4A devices features a programmable low-power mode,
which results in power savings of up to 50%. The signal speed paths in the low-power P AL block
will be slower than those in the non-low-power PAL block. This feature allows speed critical
paths to run at maximum frequency while the rest of the signal paths operate in the low-power
mode.

PROGRAMMABLE SLEW RATE

Each ispMACH 4A device I/O has an individually programmable output slew rate control bit.
Each output can be individually configured for the higher speed transition (3 V/ns) or for the
lower noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slow­slew rate will introduce fewer reflections, less noise, and keep ground bounce to a minimum.
For designs with short traces or well terminated lines, the fast slew rate can be used to achieve
the highest speed. The slew rate is adjusted independent of power.

POWER-UP RESET/SET

All flip-flops power up to a known state for predictable system initialization. If a macrocell is
configured to SET on a signal from the control generator, then that macrocell will be SET during
device power-up. If a macrocell is configured to RESET on a signal from the control generator
or is not configured for set/reset, then that macrocell will RESET on power-up. To guarantee
initialization values, the V
reset delay time has elapsed.

rise must be monotonic, and the clock must be inactive until the

CC

SECURITY BIT

A programmable security bit is provided on the ispMACH 4A devices as a deterrent to
unauthorized copying of the array configuration patterns. Once programmed, this bit defeats
readback of the programmed pattern by a device programmer, securing proprietary designs from
competitors. Programming and verification are also defeated by the security bit. The bit can only
be reset by erasing the entire device.

HOT SOCKETING

ispMACH 4A devices are well-suited for those applications that require hot socketing capability.
Hot socketing a device requires that the device, when powered down, can tolerate active signals
on the I/Os and inputs without being damaged. Additionally, it requires that the effects of the
powered-down MACH devices be minimal on active signals.

22 ispMACH 4A Family

CLK3

M4A(3, 5)-64/32
M4A3-64/64
M4A(3, 5)-96/48
M4A(3, 5)-128/64

A
B

16
17

M4(3, 5)-192/96
M4(3, 5)-256/128

17
17

M4A3-384
M4A3-512

18
18

CLK0

CLK1

CLK2

A

0

CLOCK

GENERATOR

4

CENTRAL SWITCH MATRIX

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

M0

M1

M2

M3

M4

M5

M6

M7

M8

LOGIC ALLOCATOR

M9

M10

M11

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

M0

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

OUTPUT SWITCH MATRIX

O0

O1

O2

O3

O4

O5

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

89

B

24

M12

M13

M14

O6

O7M15

16

INPUT SWITCH

MATRIX

C12

C13

C14

C15

M12

M13

M14

M15

MACROCELL

MACROCELL

MACROCELL

MACROCELL

16

Figure 16. PAL Block for ispMACH 4A with 2:1 Macrocell - I/O Cell Ratio

ispMACH 4A Family 23

I/O

CELL

I/O

CELL

I/O6

I/O7

M4A3-256/160
M4A3-256/192

18
18

CLK0

CLK1

CLK2

CLK3

A

0

CLOCK

GENERA T OR

4

A
B

M4A3-64/64

16
17

CENTRAL SWITCH MATRIX

M0

M1

M2

M3

M4

M5

M6

M7

M8

M9

O0

O1

O2

O3

O4

O5

O6

O7

O8

OUTPUT SWITCH MATRIX

O9

M0

C0

M1

C1

C2

M2

C3

M3

C4

M4

C5

M5

C6

M6

C7

M7

C8

M8

LOGIC ALLOCATOR

C9

M9

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O8

I/O9

C10

M10

C11

M11

C12

M12

C13

M13

C14

M14

C15

M15

97

B

INPUT

32

SWITCH

MATRIX

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

16

16

M10

M11

M12

M13

M14

M15

O10

O11

O12

O13

O14

O15

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

17466H-41

Figure 17. PAL Block for ispMACH 4A Devices with 1:1 Macrocell-I/O Cell Ratio (except M4A (3,5)-32/32)

24 ispMACH 4A Family

CLK0/I0 CLK0/I1

CENTRAL SWITCH MATRIX

16

0

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CLOCK

GENERATOR

2

M0

M1

M2

M3

M4

M5

M6

M7

M8

LOGIC ALLOCATOR

M9

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

M0

M1

M2

M3

M4

M5

M6

M7

M8

M9

O0

O1

O2

O3

O4

OUTPUT SWITCH MATRIX

O5

O6

O7

O8

O9

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O8

I/O9

C10

M10

C11

M11

C12

M12

C13

M13

C14

M14

C15

M15

97

17

INPUT

32

SWITCH

MATRIX

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

MACROCELL

16

16

M10

M11

M12

M13

M14

M15

O10

O11

O12

OUTPUT SWITCH MATRIX

O13

O14

O15

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

I/O

CELL

Figure 18. PAL Block for M4A (3,5)-32/32

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

17466H-042

ispMACH 4A Family 25

BLOCK DIAGRAM – M4A(3,5)-32/32

I/O8–I/O15 I/O0–I/O7

Block A

2

2

CLK0/I0, CLK1/I1

Output Switch

8

8

Matrix

Input Switch

16

16

Matrix

Input Switch

8

I/O Cells

8

Matrix

8

Macrocells

8

8

8

4

OE

66 X 98

AND Logic Array

and Logic Allocator

2

8

4

Clock Generator

33

Central Switch Matrix

33

66 X 98

AND Logic Array

and Logic Allocator

OE

2

OE

OE

8

I/O Cells

8

Output Switch

Matrix

8

Macrocells

8

8

8

8

Matrix

Input Switch

16

16

Matrix

Input Switch

Macrocells

8

8

8

Output Switch

Matrix

8

I/O Cells

8

I/O16–I/O23 I/O24–I/O31

4 4

8

Block B

26 ispMACH 4A Family

8

Clock Generator

Macrocells

8

Output Switch

Matrix

8

I/O Cells

8

8

8

17466H-019

BLOCK DIAGRAM – M4A(3,5)-64/32

2

2

CLK0/I0, CLK1/I1

4

8

Clock Generator

4

OE

2

Block A

I/O0–I/O7 I/O24–I/O31

8

I/O Cells

8

Output Switch

Matrix

16

Macrocells

16

66 X 90

AND Logic Array

and Logic Allocator

33

16

16

Matrix

Input Switch

24

4

8

Clock Generator

4

OE

2

AND Logic Array

and Logic Allocator

Central Switch Matrix

33

24

Block D

8

I/O Cells

8

Output Switch

Matrix

16

Macrocells

16

66 X 90

33

33

16

16

Matrix

Input Switch

24

24

2

OE

4

8

4

Clock Generator

66 X 90

AND Logic Array

and Logic Allocator

16

Macrocells

16

Output Switch

Matrix

8

I/O Cells

8

Block B

Matrix

Input Switch

16

16

2

OE

4

8

4

Clock Generator

66 X 90

AND Logic Array

and Logic Allocator

16

Macrocells

16

Output Switch

Matrix

8

I/O Cells

8

I/O16–I/O23I/O8–I/O15

Block C

Matrix

Input Switch

16

16

17466H-020

ispMACH 4A Family 27

BLOCK DIAGRAM – M4A3-64/64

4

4

CLK0/I0, CLK1/I1

CLK2/I3, CLK3/I4

16

Clock Generator

4

OE

4

4

OE

4

16

Block A

16
I/O Cells

16

Output Switch

Matrix

16

Macrocells

16

66 X 90

AND Logic Array

and Logic Allocator

33

33

66 X 90

AND Logic Array

and Logic Allocator

16

Macrocells

16

Output Switch

Matrix

16

16

16

Clock Generator

4

OE

4

AND Logic Array

and Logic Allocator

Central Switch Matrix

4

16

16

AND Logic Array

and Logic Allocator

OE

4

16

Block D

16

I/O Cells

16

Output Switch

Matrix

16

Macrocells

16

66 X 90

33

33

66 X 90

16

Macrocells

16

Output Switch

Matrix

16

16

2

16

16

Clock Generator

16

I/O Cells
16

Clock Generator

Block B

28 ispMACH 4A Family

16

I/O Cells

16

Block C

17466H-020A

BLOCK DIAGRAM – M4A(3,5)-96/48

I2, I3, I6, I7

4

8

8

8

I/O Cells

4

Clock Generator

8

I/O Cells

4

Clock Generator

16

16

Matrix

16

Output Switch

8

4

16

Matrix

16

Output Switch

8

4

16

16

Macrocells

16

Macrocells

Input Switch

Matrix

16

OE

Input Switch

Matrix

16

OE

Input Switch

Matrix

66 X 90

AND Logic Array

and Logic Allocator

4

66 X 90

AND Logic Array

and Logic Allocator

4

24

33

24

33

33

33

Central Switch Matrix

24

Input Switch

Matrix

24

66 X 90

Input Switch

Matrix

24

66 X 90

Input Switch

Matrix

24

16

AND Logic Array

and Logic Allocator

OE

4

16

AND Logic Array

and Logic Allocator

OE

4

16

16

16

Macrocells

4

Clock Generator

16

16

16

Macrocells

4

Clock Generator

16

16

Matrix

8

Output Switch

8

4

Matrix

8

Output Switch

8

4

8

I/O Cells

8

I/O Cells

I/O40–I/O47I/O32–I/O39I/O24–I/O31

Block C Block B Block A

I/O16–I/O23 I/O8–I/O15 I/O0–I/O7

8

I/O Cells

Matrix

8

Output Switch

8

4

Clock Generator

16

4

16

Macrocells

OE

66 X 90

AND Logic Array

and Logic Allocator

4

CLK0/I0, CLK1/I1,

33

4

4

CLK2/I4, CLK3/I5

33

66 X 90

16

AND Logic Array

and Logic Allocator

OE

4

16

Macrocells

4

Clock Generator

8

Output Switch

8

4

8

I/O Cells

17466G-021

Matrix

ispMACH 4A Family 29

Block D Block E Block F

BLOCK DIAGRAM – M4A(3,5)-128/64

I2, I5

2

Block ABlock BBlock CBlock D

I/O0–I/O7I/O8–I/O15I/O16–I/O23I/O24–I/031

8

8

I/O Cells

I/O Cells

16

Matrix

8

Output Switch

8

4

Clock Generator

16

Matrix

8

Output Switch

8

4

Clock Generator

16

16

16

4

16

16

4

Macrocells

Macrocells

16

Input Switch

Matrix

16

OE

Input Switch

Matrix

16

OE

Input Switch

Matrix

66 X 90

AND Logic Array

and Logic Allocator

4

66 X 90

AND Logic Array

and Logic Allocator

4

24

33

24

33

24

33

Central Switch Matrix

Input Switch

24

Input Switch

24

33

Input Switch

24

Matrix

66 X 90

AND Logic Array

and Logic Allocator

OE

4

Matrix

66 X 90

AND Logic Array

and Logic Allocator

OE

4

Matrix

16

16

Macrocells

Macrocells

16

16

Matrix

16

Output Switch

8

4

Clock Generator

16

16

Matrix

16

Output Switch

8

4

Clock Generator

16

16

8

4

8

4

8

I/O Cells

8

I/O Cells

Block HBlock GBlock FBlock E

8

8

8

I/O Cells

4

Clock Generator

8

I/O Cells

4

Clock Generator

Matrix

16

Output Switch

8

4

16

16

Matrix

16

Output Switch

8

4

16

Macrocells

OE

Input Switch

16

Macrocells

OE

66 X 90

AND Logic Array

and Logic Allocator

4

Matrix

66 X 90

AND Logic Array

and Logic Allocator

4

33

24

33

4

4

CLK0/I0, CLK1/I1,

CLK2/I3, CLK3/I4

33

Input Switch

24

33

66 X 90

AND Logic Array

and Logic Allocator

OE

4

Matrix

66 X 90

AND Logic Array

and Logic Allocator

OE

4

16

16

16

Macrocells

4

Clock Generator

16

16

16

Macrocells

4

Clock Generator

Matrix

8

Output Switch

8

4

Matrix

8

Output Switch

8

4

8

I/O Cells

8

I/O Cells

I/O32–I/O39 I/O40–I/O47 I/O48–I/O55 I/O56–I/O63

17466H-022

ispMACH 4A Family 30

BLOCK DIAGRAM – M4A(3,5)-192/96

Block C I/O16–I/O23
Block D I/O24–I/O31

Output Switch

16

16

AND Logic Array

Matrix

and Logic Allocator

Input Switch

24

Output Switch

16

16

AND Logic Array

Matrix

and Logic Allocator

Input Switch

24

Block B

I/O8–I/O15

8

I/O Cells

8

Matrix

16

Macrocells

16

68 X 90

34

8

I/O Cells

8

Matrix

16

Macrocells

16

68 X 90

4

8

4

OE

4

8

4

OE

16

Clock Generator

16

4

Input Switch

24

16

Clock Generator

16

4

Input Switch

24

Block A

I/O0–I/O7

I/O Cells

8

Output Switch

Matrix

16

Macrocells

16

68 X 90

AND Logic Array

Matrix

and Logic Allocator

I/O Cells

8

Output Switch

Matrix

16

Macrocells

16

68 X 90

AND Logic Array

Matrix

and Logic Allocator

CLK0–CLK3

4

8

4

Block L

I/O88–I/O95

8

I/O Cells

8

4

8

4

Clock Generator

OE

4

34

8

4

8

4

Clock Generator

OE

4

and Logic Allocator

Output Switch

Matrix

16

Macrocells

16

68 X 90

AND Logic Array

34

8

16

16

Input Switch

24

Matrix

4

I/O Cells

8

4

8

4

OE

Clock Generator

4

4

Output Switch

8

4

Clock Generator

Central Switch Matrix

4

OE

AND Logic Array

and Logic Allocator

Matrix

16

Macrocells

16

68 X 90

34 34 34 34

16

16

Input Switch

24

Matrix

4

I/O80–I/O87

4

Output Switch

8

4

Clock Generator

OE

AND Logic Array

and Logic Allocator

4

Output Switch

8

4

Clock Generator

OE

AND Logic Array

and Logic Allocator

Block K

8

I/O Cells

8

Matrix

16

Macrocells

16

68 X 90

34

8

I/O Cells

8

Matrix

16

Macrocells

16

68 X 90

16

16

Input Switch

24

16

16

Input Switch

24

Matrix

I/O72–I/O79 Block J
I/O64–I/O71 Block I

Matrix

24

AND Logic Array

and Logic Allocator

Matrix

Input Switch

Macrocells

16

16

Output Switch

68 X 90

16

16

Matrix

8

I/O Cells

8

I/O32–I/O39

Block E

OE

4

8

4

24

4

Input Switch

16

16

Clock Generator

68 X 90

AND Logic Array

and Logic Allocator

Matrix

Macrocells

Output Switch

Matrix

I/O Cells

8

I/O40–I/O47

Block F

34 34 34 34

24

4

16

OE

16

4

8

4

8

Clock Generator

4

OE

4

8

4

Clock Generator

and Logic Allocator

16

Macrocells

16

Output Switch

Matrix

8

Input Switch

16

16

Matrix

4

68 X 90

AND Logic Array

I/O Cells

16

I0–I15

8

I/O48–I/O55

Block G

AND Logic Array

and Logic Allocator

OE

4

8

Output Switch

4

Clock Generator

I/O56–I/O63

68 X 90

Macrocells

I/O Cells

Block H

16

16

Matrix

8

8

24

Input Switch

16

16

Matrix

17466G-067

ispMACH 4A Family 31

BLOCK DIAGRAM – M4A(3,5)-256/128

Block C I/O16–I/O23
Block D I/O24–I/O31

Block E I/O32–I/O39
Block F I/O40–I/O47

Output Switch

16

16

AND Logic Array

Matrix

and Logic Allocator

Input Switch

24

24

AND Logic Array

and Logic Allocator

Matrix

Input Switch

16

16

Output Switch

Output Switch

16

16

AND Logic Array

Matrix

and Logic Allocator

Input Switch

24

Block B

I/O8–I/O15

I/O Cells

8

Matrix

16

Macrocells

16

68 X 90

68 X 90

Macrocells

Matrix

I/O Cells

8

I/O Cells

8

Matrix

16

Macrocells

16

68 X 90

Block A

I/O0–I/O7

8

8

CLK0–CLK3

4

4

I/O Cells

8

4

8

4

Clock Generator

OE

4

34

34

4

16

OE

16

4

8

4

8

Clock Generator

Output Switch

16

16

AND Logic Array

Matrix

and Logic Allocator

Input Switch

24

24

AND Logic Array

and Logic Allocator

Matrix

Input Switch

16

16

Output Switch

Matrix

16

Macrocells

16

68 X 90

68 X 90

Macrocells

Matrix

4

8

4

Clock Generator

OE

4

34

34

4

16

OE

16

4

8

4

8

Clock Generator

4

4

I/O Cells

8

I/O Cells

Output Switch

Matrix

16

16

Macrocells

16

68 X 90

AND Logic Array

Matrix

and Logic Allocator

8

Central Switch Matrix

8

4

8

4

Clock Generator

OE

4

34

4

8

4

8

4

OE

4

16

Clock Generator

Input Switch

34

24

I/O120–I/O127

4

Output Switch

8

4

Clock Generator

OE

AND Logic Array

and Logic Allocator

AND Logic Array

and Logic Allocator

OE

4

8

Output Switch

4

Clock Generator

4

Output Switch

8

4

Clock Generator

OE

AND Logic Array

and Logic Allocator

Block P

8

I/O Cells

8

Matrix

16

Macrocells

16

68 X 90

34

34

68 X 90

16

Macrocells

16

Matrix

8

I/O Cells

8

8

I/O Cells

8

Matrix

16

Macrocells

16

68 X 90

34

16

16

Input Switch

24

24

Input Switch

16

16

16

16

Input Switch

24

Matrix

Matrix

Matrix

4

4

4

I/O112–I/O119

4

Output Switch

8

4

Clock Generator

OE

AND Logic Array

and Logic Allocator

AND Logic Array

and Logic Allocator

OE

4

8

Output Switch

4

Clock Generator

4

Output Switch

8

4

Clock Generator

OE

AND Logic Array

and Logic Allocator

Block O

8

I/O Cells

8

Matrix

16

Macrocells

16

68 X 90

34

34

68 X 90

16

Macrocells

16

Matrix

8

I/O Cells

8

8

I/O Cells

8

Matrix

16

Macrocells

16

68 X 90

34

16

16

Input Switch

24

24

Input Switch

16

16

16

16

Input Switch

24

Matrix

Matrix

I/O104–I/O111 Block N
I/O96–I/O103 Block M
I/O88–I/O95 Block L
I/O80–I/O87 Block K

Matrix

24

AND Logic Array

and Logic Allocator

Matrix

Input Switch

16

16

Output Switch

68 X 90

Macrocells

Matrix

I/O Cells

8

I/O48–I/O55

Block G

34

4

16

OE

16

4

8

4

8

Input Switch

16

Clock Generator

24

AND Logic Array

and Logic Allocator

Matrix

Macrocells

16

Output Switch

I/O56–I/O63

68 X 90

Matrix

I/O Cells

8

Block H

34

4

16

OE

16

4

8

4

8

Clock Generator

4

and Logic Allocator

OE

4

8

4

Clock Generator

14

I0–I13

32 ispMACH 4A Family

34

68 X 90

AND Logic Array

16

Macrocells

16

Output Switch

Matrix

8

I/O Cells

8

I/O64–I/O71

Block I

24

Input Switch

16

16

Matrix

4

OE

4

8

4

Clock Generator

34

68 X 90

AND Logic Array

and Logic Allocator

16

Macrocells

16

Output Switch

Matrix

8

I/O Cells

8

I/O72–I/O79

Block J

24

Input Switch

16

16

Matrix

17466G-024

BLOCK DIAGRAM – M4A3-256/160, M4A3-256/192

Block C
Block D
Block E
Block F

Output Switch

16

16

AND Logic Array

Matrix

and Logic Allocator

Input Switch

32

32

AND Logic Array

and Logic Allocator

Matrix

Input Switch

16

16

Output Switch

Output Switch

16

16

AND Logic Array

Matrix

and Logic Allocator

Input Switch

32

Block B

I/O Cells

16

Matrix

16

Macrocells

16

72 X 98

72 X 98

Macrocells

Matrix

I/O Cells

16

I/O Cells

16

Matrix

16

Macrocells

16

72 X 98

4

16

4

OE

OE

4

16

4

4

16

4

OE

CLK0–CLK3

4

4

Clock Generator

4

4

Clock Generator

Clock Generator

4

4

Output Switch

16

4

Clock Generator

OE

4

AND Logic Array

and Logic Allocator

AND Logic Array

4

and Logic Allocator

OE

4

16

Output Switch

4

Clock Generator

Central Switch Matrix

4

Output Switch

16

4

Clock Generator

OE

4

AND Logic Array

and Logic Allocator

16

I/O Cells

16

Matrix

16

Macrocells

16

72 X 98

36

36

72 X 98

16

Macrocells

16

Matrix

16

I/O Cells

16

16

I/O Cells

16

Matrix

16

Macrocells

16

72 X 98

36

16

16

Input Switch

32

32

Input Switch

16

16

16

16

Input Switch

32

Matrix

Matrix

Matrix

Clock Generator

4

4

Clock Generator

Clock Generator

4

Block A

16

16

I/O Cells

16

16

Matrix

and Logic Allocator

Input Switch

32

32

and Logic Allocator

Matrix

Input Switch

16

16

16

Output Switch

Matrix

16

Macrocells

16

72 X 98

AND Logic Array

36

36

72 X 98

AND Logic Array

16

Macrocells

16

Output Switch

Matrix

16

4

16

4

Clock Generator

OE

4

36

36

4

16

OE

16

4

16

4

16

Clock Generator

I/O Cells

16

16

16

I/O Cells

16

16

Matrix

and Logic Allocator

Input Switch

32

16

Output Switch

Matrix

16

Macrocells

16

72 X 98

AND Logic Array

36

4

16

4

Clock Generator

OE

4

36

4

Output Switch

16

4

OE

AND Logic Array

and Logic Allocator

AND Logic Array

and Logic Allocator

OE

4

16

Output Switch

4

4

Output Switch

16

4

OE

AND Logic Array

and Logic Allocator

Block OBlock P

16

I/O Cells

16

Matrix

16

Macrocells

16

72 X 98

36

36

72 X 98

16

Macrocells

16

Matrix

16

I/O Cells

16

16

I/O Cells

16

Matrix

16

Macrocells

16

72 X 98

36

16

16

Input Switch

32

32

Matrix

Input Switch

16

16

16

16

Matrix

Input Switch

32

Matrix

Block N
Block M
Block L
Block K

32

AND Logic Array

and Logic Allocator

Matrix

Input Switch

16

16

Output Switch

72 X 98

Macrocells

Matrix

I/O Cells

16

Block G

72 X 98

AND Logic Array

and Logic Allocator

Matrix

Macrocells

Output Switch

Matrix

36

4

16

OE

16

4

16

4

16

Clock Generator

4

Clock Generator

36

16

OE

16

4

16

4

16

32

4

Input Switch

16

16

Clock Generator

I/O Cells

16

AND Logic Array

and Logic Allocator

OE

4

16

Output Switch

4

36

72 X 98

16

Macrocells

16

Matrix

16

I/O Cells

16

Block IBlock H

32

Input Switch

16

16

Matrix

4

OE

4

16

4

Clock Generator

36

72 X 98

AND Logic Array

and Logic Allocator

16

Macrocells

16

Output Switch

Matrix

16

I/O Cells

16

Block J

32

Matrix

Input Switch

16

16

17466G-050

ispMACH 4A Family 33

BLOCK DIAGRAM – M4A3-384/160, M4A3-384/192

Detail A

Block C
Block F

Block G
Block J

16

16

AND Logic Array

Matrix

and Logic Allocator

Input Switch

24

24

AND Logic Array

and Logic Allocator

Matrix

Input Switch

16

16

Output Switch

16

16

AND Logic Array

Matrix

and Logic Allocator

Input Switch

24

Block B

8

I/O Cells

8

Output Switch

Matrix

16

Macrocells

16

72 X 90

36

36

72 X 90

16

Macrocells

16

Matrix

8

I/O Cells

8

8

I/O Cells

8

Output Switch

Matrix

16

Macrocells

16

72 X 90

36

8

OE

8

8

OE

4

4

4

4

OE

4

4

4

4

4

16

Clock Generator

16

Matrix

Input Switch

24

24

Matrix

Input Switch

16

16

Clock Generator

Block D

Block E

Block H

Block I

16

Clock Generator

16

Matrix

Input Switch

24

Block A Block GXBlock HX

8

CLK0–CLK3

4

4 4

I/O Cells

8

Output Switch

Matrix

16

Macrocells

16

72 X 90

AND Logic Array

and Logic Allocator

36

36

72 X 90

AND Logic Array

and Logic Allocator

16

Macrocells

16

Output Switch

Matrix

8

I/O Cells

8

4

8

4

OE

OE

4

8

4

Clock Generator

4

4

Clock Generator

4

8

4

Clock Generator

4

4

4

8

4

Central Switch Matrix

Clock Generator

Repeat Detail A

8

I/O Cells

8

Output Switch

Matrix

16

Macrocells

16

72 X 90

AND Logic Array

and Logic Allocator

36

4

8

4

OE

Clock Generator

4

4

8

4

Clock Generator

4

8

I/O Cells

8

Output Switch

Matrix

16

Macrocells

16

OE

72 X 90

AND Logic Array

and Logic Allocator

36

36

72 X 90

AND Logic Array

and Logic Allocator

16

OE

Macrocells

16

Output Switch

Matrix

8

I/O Cells

8

8

I/O Cells

8

Output Switch

Matrix

16

Macrocells

16

OE

72 X 90

AND Logic Array

and Logic Allocator

36

16

16

Input Switch

24

24

Input Switch

16

16

Block EX
Block DX

16

16

Input Switch

24

Matrix

Matrix

Block AX
Block P

Matrix

4

8

4

Clock Generator

OE

4

4

OE

4

8

4

Clock Generator

4

8

4

Clock Generator

OE

4

8

I/O Cells

8

Output Switch

Matrix

16

Macrocells

16

72 X 90

AND Logic Array

and Logic Allocator

36

36

72 X 90

AND Logic Array

and Logic Allocator

16

Macrocells

16

Output Switch

Matrix

8

I/O Cells

8

8

I/O Cells

8

Output Switch

Matrix

16

Macrocells

16

72 X 90

AND Logic Array

and Logic Allocator

36

16

16

Input Switch

24

24

Input Switch

16

16

Block FX
Block CX

Block BX
Block O

16

16

Input Switch

24

Matrix

Matrix

Matrix

24

AND Logic Array

and Logic Allocator

Matrix

Input Switch

16

16

Output Switch

72 X 90

Macrocells

Matrix

I/O Cells

8

36

4

16

OE

16

4

8

4

8

Clock Generator

24

AND Logic Array

and Logic Allocator

Matrix

Input Switch

16

16

Output Switch

72 X 90

Macrocells

Matrix

I/O Cells

8

36

AND Logic Array

4

16

OE

16

4

8

4

8

Clock Generator

4

OE

4

8

4

Clock Generator

and Logic Allocator

Block LBlock K Block M Block N

34 ispMACH 4A Family

36

72 X 90

16

Macrocells

16

Output Switch

Matrix

8

I/O Cells

8

24

Input Switch

16

16

Matrix

4

OE

4

8

4

Clock Generator

36

72 X 90

AND Logic Array

and Logic Allocator

16

Macrocells

16

Output Switch

Matrix

8

I/O Cells

8

24

Input Switch

16

16

Matrix

17466G-067

BLOCK DIAGRAM - M4A3-512/160, M4A3-512/192, M4A3-512/256

Detail A

Block C

Block F

Block G

Block J

Block K

Block N

16

16

AND Logic Array

Matrix

and Logic Allocator

Input Switch

24

24

AND Logic Array

and Logic Allocator

Matrix

Input Switch

16

16

Output Switch

16

16

AND Logic Array

Matrix

and Logic Allocator

Input Switch

24

Block B

8

I/O Cells

8

Output Switch

Matrix

16

Macrocells

16

72 X 90

36

36

72 X 90

16

Macrocells

16

Matrix

8

I/O Cells

8

8

I/O Cells

8

Output Switch

Matrix

16

Macrocells

16

72 X 90

36

8

8

8

4

4

OE

OE

4

4

4

4

OE

16

Clock Generator

4

4

16

Clock Generator

Block D
Block E

Block H

Block I

Block L

Block M

16

Clock Generator

4

Block A Block OXBlock PX

8

CLK0–CLK3

4

4 4

I/O Cells

8

Matrix

16

16

72 X 90

72 X 90

8

4

8

4

Clock Generator

OE

4

36

36

4

16

OE

16

4

8

4

8

Central Switch Matrix

Clock Generator

Output Switch

16

Macrocells

AND Logic Array

Matrix

and Logic Allocator

Input Switch

24

24

AND Logic Array

and Logic Allocator

Matrix

Input Switch

Macrocells

16

Output Switch

Matrix

I/O Cells

Repeat Detail A

Repeat Detail A

8

I/O Cells

8

Matrix

16

16

72 X 90

4

8

4

Clock Generator

OE

4

36

Output Switch

16

Macrocells

AND Logic Array

Matrix

and Logic Allocator

Input Switch

24

4

8

4

Clock Generator

OE

4

4

OE

4

8

4

Clock Generator

4

8

4

Clock Generator

OE

4

8

I/O Cells

8

Output Switch

Matrix

16

Macrocells

16

72 X 90

AND Logic Array

and Logic Allocator

36

36

72 X 90

AND Logic Array

and Logic Allocator

16

Macrocells

16

Output Switch

Matrix

8

I/O Cells

8

8

I/O Cells

8

Output Switch

Matrix

16

Macrocells

16

72 X 90

AND Logic Array

and Logic Allocator

36

16

16

Input Switch

24

24

Input Switch

16

16

16

16

Input Switch

24

Matrix

Matrix

Block MX
Block LX

Block IX
Block HX

Block EX
Block DX

Matrix

4

8

4

Clock Generator

OE

4

4

and Logic Allocator

OE

4

8

4

Clock Generator

4

8

4

Clock Generator

OE

4

8

I/O Cells

8

Output Switch

Matrix

16

Macrocells

16

72 X 90

AND Logic Array

and Logic Allocator

36

36

72 X 90

AND Logic Array

16

Macrocells

16

Output Switch

Matrix

8

I/O Cells

8

8

I/O Cells

8

Output Switch

Matrix

16

Macrocells

16

72 X 90

AND Logic Array

and Logic Allocator

36

16

16

Input Switch

24

24

Input Switch

16

16

Block NX
Block KX

Block JX
Block GX

Block FX
Block CX

16

16

Input Switch

24

Matrix

Matrix

Matrix

24

AND Logic Array

and Logic Allocator

Matrix

Input Switch

16

16

Output Switch

72 X 90

Macrocells

Matrix

I/O Cells

8

AND Logic Array

and Logic Allocator

OE

4

8

Output Switch

4

Clock Generator

36

72 X 90

16

Macrocells

16

Matrix

8

I/O Cells

8

24

Input Switch

16

16

Matrix

4

and Logic Allocator

OE

4

8

4

Clock Generator

36

72 X 90

AND Logic Array

16

Macrocells

16

Output Switch

Matrix

8

I/O Cells

8

24

Input Switch

16

16

Matrix

17466G-068

36

4

16

OE

16

4

8

4

8

Clock Generator

24

AND Logic Array

and Logic Allocator

Matrix

Input Switch

16

16

Output Switch

72 X 90

Macrocells

Matrix

I/O Cells

8

36

4

16

OE

16

4

8

4

8

Clock Generator

4

Block PBlock O Block AX Block BX

ispMACH 4A Family 35

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES

M4A5

Storage Temperature. . . . . . . . . . . . . . . -65°C to +150°C

Ambient T emperature

with Power Applied . . . . . . . . . . . . . . . .-55°C to +100°C

Device Junction Temperature. . . . . . . . . . . . . . . +130°C

Supply V oltage

with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V

DC Input Voltage. . . . . . . . . . . . . . . -0.5 V to V

Static Discharge Voltage . . . . . . . . . . . . . . . . . . . .2000 V

Latchup Current (TA = -40°C to +85°C) . . . . . . . 200 mA

Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality
at or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect device

CC

+ 0.5 V

Commercial (C) Devices

Ambient T emperature (TA)

Operating in Free Air. . . . . . . . . . . . . . . . . 0°C to +70°C

Supply V oltage (VCC)

with Respect to Ground . . . . . . . . . . +4.75 V to +5.25 V

Industrial (I) Devices

Ambient T emperature (TA)

Operating in Free Air. . . . . . . . . . . . . . . . -40°C to +85°C

Supply V oltage (VCC)

with Respect to Ground . . . . . . . . . . . +4.50 V to +5.5 V

Operating rang es define those limits betw een which the func­tionality of the device is guaranteed.

reliability.

5-V DC CHARACTERISTICS OVER OPERATING RANGES

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

V

V

V

V

I
I
I
I
I

OH

OL

IH

IL

IH
IL
OZH
OZL
SC

= –3.2 mA, VCC = Min, VIN = V

I

Output HIGH Voltage

OH

= –2.5 mA, VCC = Max, VIN = V

I

OH

Output LOW Voltage IOL = 24 mA, VCC = Min, VIN = VIH or V

Input HIGH Voltage

Input LOW Voltage

Guaranteed Input Logical HIGH Voltage for all Inputs
(Note 2)

Guaranteed Input Logical LOW Voltage for all Inputs

(Note 2)
Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 3) 10 µA
Input LOW Leakage Current VIN = 0 V, V
Off-State Output Leakage Current HIGH V
Off-State Output Leakage Current LOW V
Output Short-Circuit Current V

OUT
OUT
OUT

= Max (Note 3) –10 µA

CC

= 5.25 V, VCC = Max, VIN = V
= 0 V, VCC = Max , VIN = V
= 0.5 V, VCC = Max (Note 4) –30 –160 mA

or V

IH

IL

or V

IH

IL

(Note 1) 0.5 V

IL

2.4 V

3.6 V

2.0 V

0.8 V

or VIL (Note 3) 10 µA

IH

or VIL (Note 3) –10 µA

IH

Notes:

1. Total I

for one PAL block should not exceed 64 mA.

OL

2. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.

3. I/O pin leakage is the worst case of I

and I

IL

(or IIH and I

OZL

OZH

).

4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

V

OUT

36 ispMACH 4A Family

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES

M4A3

Storage Temperature. . . . . . . . . . . . . . . -65°C to +150°C

Ambient T emperature

with Power Applied . . . . . . . . . . . . . . . .-55°C to +100°C

Device Junction Temperature. . . . . . . . . . . . . . . +130°C

Supply V oltage

with Respect to Ground . . . . . . . . . . . . . -0.5 V to +4.5 V

DC Input Voltage. . . . . . . . . . . . . . . . . . . . -0.5 V to 6.0 V

Static Discharge Voltage . . . . . . . . . . . . . . . . . . . .2000 V

Latchup Current (TA = -40°C to +85°C) . . . . . . . 200 mA

Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality

Commercial (C) Devices

Ambient T emperature (TA)

Operating in Free Air. . . . . . . . . . . . . . . . . 0°C to +70°C

Supply V oltage (VCC)

with Respect to Ground . . . . . . . . . . . . +3.0 V to +3.6 V

Industrial (I) Devices

Ambient T emperature (TA)

Operating in Free Air. . . . . . . . . . . . . . . . -40°C to +85°C

Supply V oltage (VCC)

with Respect to Ground . . . . . . . . . . . . +3.0 V to +3.6 V

Operating rang es define those limits betw een which the func­tionality of the device is guaranteed.

at or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect device
reliability.

3.3-V DC CHARACTERISTICS OVER OPERATING RANGES

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

V

V

V

V

I
I

I

I

I

OH

OL

IH

IL

IH
IL

OZH

OZL

SC

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage

= Min

V

CC

V

= VIH or V

IN

= Min

V

CC

V

= VIH or V

IN

IL

IL

(Note 1)
Guaranteed Input Logical HIGH Voltage for all

Inputs
Guaranteed Input Logical LOW Voltage for all

Inputs

IOH = –100 µAV

= –3.2 mA 2.4 V

I

OH

I

= 100 µA 0.2 V

OL

= 24 mA 0.5 V

I

OL

Input HIGH Leakage Current VIN = 3.6 V, VCC = Max (Note 2) 5 µA
Input LOW Leakage Current VIN = 0 V, V

V

Off-State Output Leakage Current HIGH

Off-State Output Leakage Current LOW

Output Short-Circuit Current V

OUT

V

= V

IN

V

OUT

V

= V

IN
OUT

= Max (Note 2) –5 µA

CC

= 3.6 V, VCC = Max

or VIL (Note 2)

IH

= 0 V, VCC = Max

or VIL (Note 2)

IH

= 0.5 V, VCC = Max (Note 3) –15 –160 mA

– 0.2 V

CC

2.0 5.5 V

–0.3 0.8 V

5 µA

–5 µA

Notes:

1. Total I

2. I/O pin leakage is the worst case of I

for one PAL block should not exceed 64 mA.

OL

and I

IL

OZL

(or IIH and I

OZH

).

3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

Notes:

1. See “MACH Switching Test Circuit” document on the Literature Download page of the Lattice web site.

2. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.

ispMACH 4A Family 37

ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1

-5 -55 -6 -65 -7 -10 -12 -14

Combinatorial Delay:

Internal combinatorial propagation

t

PDi

delay
Combinatorial propagation delay 5.0 5.5 6.0 6.5 7.5 10.0 12.0 14.0 ns

t

PD

Registered Delays:

Synchronous clock setup time, D-type

t

SS

register
Synchronous clock setup time, T-type

t

SST

register
Asynchronous clock setup time, D-type

t

SA

register
Asynchronous clock setup time, T-type

t

SAT

register
Synchronous clock hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns

t

HS

Asynchronous clock hold time 2.5 2.5 2.5 3.0 3.5 4.0 5.0 8.0 ns

t

HA

Synchronous clock to internal output 2.5 2.5 2.8 3.0 3.0 3.0 3.5 3.5 ns

t

COSi

Synchronous clock to output 4.0 4.0 4.5 5.0 5.5 6.0 6.5 6.5 ns

t

COS

Asynchronous clock to internal output 5.0 5.0 5.0 5.0 6.0 8.0 10.0 12.0 ns

t

COAi

Asynchronous clock to output 6.5 6.5 6.8 7.0 8.5 11.0 13.0 15.0 ns

t

COA

Latched Delays:

Synchronous latch setup time 4.0 4.0 4.0 4.5 6.0 7.0 8.0 10.0 ns

t

SSL

Asynchronous latch setup time 3.0 3.0 3.5 3.5 4.0 4.0 5.0 8.0 ns

t

SAL

Synchronous latch hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns

t

HSL

Asynchronous latch hold time 3.0 3.0 3.5 3.5 4.0 4.0 5.0 8.0 ns

t

HAL

Transparent latch to internal output 5.5 5.5 5.8 6.0 7.5 9.0 11.0 12.0 ns

t

PDLi

Propagation delay through transparent

t

PDL

latch to output
Synchronous gate to internal output 3.0 3.0 3.0 3.0 3.5 4.5 7.0 8.0 ns

t

GOSi

Synchronous gate to output 4.5 4.5 4.8 5.0 6.0 7.5 10.0 11.0 ns

t

GOS

Asynchronous gate to internal output 6.0 6.0 6.0 6.0 8.5 10.0 13.0 15.0 ns

t

GOAi

Asynchronous gate to output 7.5 7.5 7.8 8.0 11.0 13.0 16.0 18.0 ns

t

GOA

Input Register Delays:

Input register setup time 1.5 1.5 2.0 2.0 2.0 2.0 2.0 2.0 ns

t

SIRS

Input register hold time 2.5 2.5 3.0 3.0 3.0 3.0 3.0 4.0 ns

t

HIRS

Input register clock to internal feedback 3.0 3.0 3.0 3.0 3.5 4.5 6.0 6.0 ns

t

ICOSi

Input Latch Delays:

Input latch setup time 1.5 1.5 1.5 2.0 2.0 2.0 2.0 2.0 ns

t

SIL

Input latch hold time 2.5 2.5 2.5 3.0 3.0 3.0 3.0 4.0 ns

t

HIL

Input latch gate to internal feedback 3.5 3.5 3.8 4.0 4.0 4.0 4.0 5.0 ns

t

IGOSi

Transparent input latch to internal

t

PDILi

feedback

3.5 4.0 4.3 4.5 5.0 7.0 9.0 11.0 ns

3.0 3.5 3.5 3.5 5.0 5.5 7.0 10.0 ns

4.0 4.0 4.0 4.0 6.0 6.5 8.0 11.0 ns

2.5 2.5 2.5 3.0 3.5 4.0 5.0 8.0 ns

3.0 3.0 3.0 3.5 4.5 5.0 6.0 9.0 ns

7.0 7.0 7.5 8.0 10.0 12.0 14.0 15.0 ns

1.5 1.5 1.5 1.5 2.0 2.0 2.0 2.0 ns

UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max

38 ispMACH 4A Family

ispMACH 4A TIMING P ARAMETERS OVER OPERATING RANGES1 (CONTINUED)

-5 -55 -6 -65 -7 -10 -12 -14
UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max

Input Register Delays with ZHT Option:

Input register setup time - ZHT 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 ns

t

SIRZ

Input register hold time - ZHT 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns

t

HIRZ

Input Latch Delays with ZHT Option:

Input latch setup time - ZHT 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 ns

t

SILZ

Input latch hold time - ZHT 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns

t

HILZ

Transparent input latch to internal

t

PDIL

feedback - ZHT

Zi

Output Delays:

Output buffer delay 1.5 1.5 1.8 2.0 2.5 3.0 3.0 3.0 ns

t

BUF

Slow slew rate delay adder 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns

t

SLW

Output enable time 7.5 7.5 8.5 8.5 9.5 10.0 12.0 15.0 ns

t

EA

Output disable time 7.5 7.5 8.5 8.5 9.5 10.0 12.0 15.0 ns

t

ER

Power Delay:

Power-down mode delay adder 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns

t

PL

Reset and Preset Delays:

Asynchronous reset or preset to internal

t

SRi

register output
Asynchronous reset or preset to register

t

SR

output
Asynchronous reset and preset register

t

SRR

recovery time
Asynchronous reset or preset width 7.0 7.0 8.0 8.0 10.0 10.0 12.0 15.0 ns

t

SRW

Clock/LE Width:

Global clock width low 2.0 2.0 2.5 2.5 3.0 4.0 5.0 6.0 ns

t

WLS

Global clock width high 2.0 2.0 2.5 2.5 3.0 4.0 5.0 6.0 ns

t

WHS

Product term clock width low 3.0 3.0 3.5 3.5 4.0 5.0 8.0 9.0 ns

t

WLA

Product term clock width high 3.0 3.0 3.5 3.5 4.0 5.0 8.0 9.0 ns

t

WHA

Global gate width low (for low
transparent) or high (for high

t

GWS

transparent)
Product term gate width low (for low

t

transparent) or high (for high

GWA

transparent)

t

Input register clock width low 3.0 3.0 3.5 3.5 4.0 5.0 6.0 6.0 ns

WIRL

Input register clock width high 3.0 3.0 3.5 3.5 4.0 5.0 6.0 6.0 ns

t

WIRH

Input latch gate width 4.0 4.0 4.5 4.5 5.0 5.0 6.0 6.0 ns

t

WIL

6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 ns

7.5 7.7 8.0 8.0 9.5 11.0 13.0 16.0 ns

9.0 9.2 10.0 10.0 12.0 14.0 16.0 19.0 ns

7.0 7.0 7.5 7.5 8.0 8.0 10.0 15.0 ns

4.0 4.0 4.5 4.5 5.0 5.0 6.0 6.0 ns

4.0 4.0 4.5 4.5 5.0 5.0 6.0 9.0 ns

ispMACH 4A Family 39

ispMACH 4A TIMING P ARAMETERS OVER OPERATING RANGES1 (CONTINUED)

-5 -55 -6 -65 -7 -10 -12 -14
UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max

Frequency:

External feedback, D-type, Min of
1/(t

+ t

WLS

) or 1/(tSS + t

WHS

External feedback, T-type, Min of 1/(t
+ t

Internal feedback (f

f

MAXS

1/(t
Internal feedback (f

1/(t
No feedback

1/(t

) or 1/(t

WHS

+ t

WLS

+ t

WLS

+ tHS) or 1/(t

SS

+ t

SST

) or 1/(tSS + t

WHS

) or 1/(t

WHS

2

, Min of 1/(t

COS

CNT

CNT

SST

External feedback, D-type, Min of 1/
(t

+ t

WLA

) or 1/(tSA + t

WHA

External feedback, T-type, Min of 1/(t
+ t

) or 1/(t

WHA

Internal feedback (f

f

MAXA

1/(t

+ t

WLA

Internal feedback (f
1/(t

+ t

WLA

No feedback
1/(t

+ tHA) or 1/(t

SA

Maximum input register frequency, Min

f

MAXI

of 1/(t

WIRH

SAT

) or 1/(tSA + t

WHA

) or 1/(t

WHA

2

, Min of 1/(t

+ t

WIRL

+ t

COA

CNTA

CNTA

SAT

) or 1/(t

)

COS

)

), D-type, Min of

)

COSi

), T-type, Min of

+ t

SST

COSi

+ t

WLS

WHS

+ tHS)

)

COA

)

), D-type, Min of

)

COAi

), T-type, Min of

+ t

SAT

COAi

+ t

WLA

WHA

+ tHA)

+ t

SIRS

143 133 125 118 95.2 87.0 74.1 60.6 MHz

WLS

125 125 118 111 87.0 80.0 69.0 57.1 MHz

182 167 160 154 125 118 95.0 74.1 MHz

154 154 148 143 111 105 87.0 69.0 MHz

)

),

250 250 200 200 154 125 100 83.3 MHz

111 111 108 100 83.3 66.7 55.6 43.5 MHz

WLA

105 105 102 95.2 76.9 62.5 52.6 41.7 MHz

133 133 125 125 105 83.3 66.7 50.0 MHz

125 125 125 118 95.2 76.9 62.5 47.6 MHz

)

),

167 167 143 143 125 100 62.5 55.6 MHz

167 167 143 143 125 100 83.3 83.3 MHz

)

HIRS

Notes:

1. See “Switching Test Circuit” document on the Literature Download page of the Lattice web site.

2. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.

CAPACITANCE

1

Parameter Symbol Parameter Description Test Conditions Typ Unit

C

IN

C

I/O

Input capacitance VIN=2.0 V 3.3 V or 5 V, 25°C, 1 MHz 6 pF

Output capacitance V

=2.0V 3.3 V or 5 V, 25°C, 1 MHz 8 pF

OUT

Note:

1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where this parameter may be affected.

40 ispMACH 4A Family

I

vs. FREQUENCY

CC

These curves represent the typical power consumption for a particular device at system frequen­cy. The selected “typical” pattern is a 16-bit up-down counter. This pattern fills the device and ex­ercises every macrocell. Maximum frequency shown uses internal feedback and a D-type register.
Power/Speed are optimized to obtain the highest counter frequency and the lowest power. The
highest frequency (LSBs) is placed in common PAL blocks, which are set to high power. The low­est frequency signals (MSBs) are placed in a common PAL block and set to lowest power.

400

VCC = 5 V or 3.3 V, TA = 25º C

M4A-512/160

(mA)

CC

I

350

300

250

200

150

100

250

50

M4A-384/160

M4A-256/160

M4A-256/128

M4A-192/96

M4A-96/48

M4A-128/64

M4A-64/64

M4A-64/32

M4A-32/32

0

0

20

40

60

80

Frequency (MHz)

100

120

140

160

180

200

Figure 19. ispMACH 4A ICC Curves at High Speed Mode

VCC = 5 V or 3.3 V, TA = 25º C

M4A-512/160

(mA)

CC

I

200

150

100

50

M4A-384/160

M4A-256/160

M4A-256/128

M4A-192/96
M4A-96/48

M4A-128/64

M4A-64/64
M4A-64/32

M4A-32/32

0

0

20

40

60

80

Frequency (MHz)

100

120

140

160

180

200

Figure 20. ispMACH 4A ICC Curves at Low Power Mode

ispMACH 4A Family 41

44-PIN PLCC CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32)

Top View

44-Pin PLCC

A2
A1
A0

M4A(3,5)-32/32

A8

A9
A10
A11

M4A(3,5)-64/32

A2

I/O5

A1

I/O6

A0

I/O7

TDI

CLK0/I0

GND

TCK

B0

I/O8

B1

I/O9

B2

I/O10

B3

I/O11

M4A(3,5)-64/32

A3A4A5A6A7

A3A4A5A6A7

I/O4

I/O3

I/O2

I/O1

I/O0

3

2

I/O Cell

PAL Block

22

I/O15
B7

1

23

VCC

5

641

4

7
8

9

C7

10
11
12
13
14
15
16
17

19

20

I/O13

21

I/O14

18 27

I/O12
B4B5B6

B7B6B5

D7D6D5

GND

VCC

I/O31

I/O30

43

44

42

25

24

26

GND

I/O16

I/O17

I/O18

C7C6C5C4C3

I/O29

40

28

I/O19

B4

D4

I/O28

39
38

37
36

35
34

33
32

31
30
29

I/O20

M4A(3,5)-64/32

I/O27

D3

I/O26

D2

I/O25

D1

I/O24

D0
TDO
GND
CLK1/I1
TMS

C0

I/O23

C1

I/O22

C2

I/O21

M4A(3,5)-64/32

B3
B2
B1
B0

M4A(3,5)-32/32

B8
B9
B10

PIN DESIGNATIONS

CLK/I = Clock or Input
GND = Ground
I/O = Input/Output
V

= Supply V oltage

CC

TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out

A12

A13

A14

A15

B15

B14

B13

B12

B11

17466G-026

42 ispMACH 4A Family

44-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32)

Top View

44-Pin TQFP

A2
A1
A0

M4A(3,5)-32/32

A8

A9
A10
A11

M4A(3,5)-64/32

I/O5

A2

I/O6

A1

I/O7

A0

TDI

CLK0/I0

GND

TCK

I/O8

B0

I/O9

B1

I/O10

B2

I/O11

B3

M4A(3,5)-64/32

A3A4A5A6A7

A3A4A5A6A7

I/O4

4443424140

1
2
3
4

C7

5

6
7
8
9
10

11

1213141516

I/O12
B4B5B6

I/O3

I/O2

I/O13

I/O14

I/O1

I/O0

I/O Cell
PAL Block

17

VCC

I/O15
B7

B7B6B5

D7D6D5

GND

VCC

I/O31

I/O30

39

38

373635

18

192021

GND

I/O16

I/O17

I/O18

C7C6C5C4C3

B4

D4

I/O29

I/O28

34

22

I/O19

I/O20

M4A(3,5)-64/32

33
32
31
30
29

28
27
26
25
24

23

M4A(3,5)-64/32

I/O27
I/O26
I/O25
I/O24
TDO
GND
CLK1/I1
TMS
I/O23
I/O22
I/O21

D3
D2
D1
D0

C0
C1
C2

B3
B2
B1
B0

M4A(3,5)-32/32

B8
B9
B10

PIN DESIGNATIONS

CLK/I = Clock or Input
GND = Ground
I/O = Input/Output
V

= Supply V oltage

CC

TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out

A12

A13

A14

A15

B15

B14

B13

B12

B11

ispMACH 4A Family 43

48-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32)

Top View

48-Pin TQFP

A2
A1
A0

M4A(3,5)-32/32

A8

A9
A10
A11

M4A(3,5)-64/32

I/O5

A2

I/O6

A1

I/O7

A0

TDI

CLK0/I0

NC

GND

TCK

B0

I/O8

B1

I/O9

B2

I/O10

B3

I/O11

M4A(3,5)-64/32

1
2
3

4

5
6
7
8
9
10
11
12

A3A4A5A6A7

A3A4A5A6A7

I/O4

I/O3

I/O2

I/O1

I/O0

44

45

46

47

48

C7

I/O14

I/O15
B7

17

VCC

13

141516

I/O12

I/O13

B4B5B6

GNDNCVCC

43

424140

I/O Cell
PAL Block

18

192021

NC

GND

I/O16
C7C6C5C4C3

B7B6B5

D7D6D5

I/O31

I/O30

I/O29

39

38

222324

I/O17

I/O18

I/O19

B4

D4

I/O28

37

36
35
34
33
32
31
30
29

28
27
26

25

I/O20

M4A(3,5)-64/32

I/O27

D3

I/O26

D2

I/O25

D1

I/O24

D0
TDO
GND
NC
CLK1/I1
TMS

C0

I/O23

C1

I/O22

C2

I/O21

M4A(3,5)-64/32

B3
B2
B1
B0

M4A(3,5)-32/32

B8
B9
B10

A12

A13

A14

A15

B15

B14

B13

PIN DESIGNATIONS

CLK/I = Clock or Input
GND = Ground
I/O = Input/Output
V

= Supply V oltage

CC

NC = No Connect
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out

44 ispMACH 4A Family

B12

B11

17466G-028

100-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-96/48)

Top View

100-Pin TQFP

A2A3A4A5A6

A7

F7F6F5F4F3

F2

A1
A0
B0
B1
B2
B3

B4
B5
B6
B7
C0
C1

NC

TDI

NC

NC
I/O6
I/O7
I/O8
I/O9

I/O10
I/O11

I0/CLK0

V

GND

I1/CLK1

I/O12
I/O13
I/O14
I/O15
I/O16
I/O17

NC

NC

TMS

TCK

NC

CC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

GNDNCNC

I/O5

I/O4

I/O3

I/O2

9998979695949392919089888786858483828180797877

100

I/O1

I/O0I7V

CC

GNDNCNCI6NC

I/O47

I/O46

I/O45

I/O44

I/O43

C7

I/O Cell

PAL Block

I/O42NCNC

GND

76

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

NC
TDO
NC
NC
NC
I/O41
I/O40
I/O39
I/O38
I/O37
I/O36
I5/CLK3
GND
V

CC

I4/CLK2
I/O35
I/O34
I/O33
I/O32
I/O31
I/O30
NC
NC
NC
NC

F1
F0
E0
E1
E2
E3

E4
E5
E6
E7
D0
D1

PIN DESIGNATIONS

CLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output
V

= Supply V oltage

CC

NC = No Connect
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out

26272829303132333435363738394041424344454647484950

I3

GND

NC

NC

I/O18
C2C3C4C5C6

I/O19

I/O20

I/O21

I/O22

NCI2NC

I/O23
C7

NC

GND

CC

V

I/O24

I/O25

I/O26

D7D6D5D4D3

I/O27

I/O28

NC

I/O29
D2

NC

GND

17466G-029

ispMACH 4A Family 45

100-PIN PQFP CONNECTION DIAGRAM (M4A(3,5)-128/64)

Top View

100-Pin PQFP

B7
B6
B5
B4
B3
B2
B1
B0

IO/CLK0

C0
C1
C2
C3
C4
C5
C6
C7

GND
GND

TDI

I/O8

I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15

V

CC

V

CC

GND
GND

I1/CLK1

I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23

TMS

TCK
GND
GND

A6A5A4A3A2A1A0

I/O7 A7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

9796959493929190898887868584828183

99

98

100

1

(9)

(8)

(7)

(6)

(5)

(4)

C7

(36)

(37)

(38)

(39)

(3)

(40)

(10)

2
3

(83)

4

I5

(12)

5

(13)

6

(14)

7

(15)

8

(16)

9

(17)

10

(18)

11

(19)

12

(20)

13
14
15
16
17

(23)

18

(24)

19

(25)

20

(26)

21

(27)

22

(28)

23

(29)

24

(30)

25

(31)

26
27
28
29
30

(33)

(34)

(35)

31323334353637383940414243444546474849

CC

V

GND

GND

I/O Cell
PAL Block

H0H1H2H3H4H5H6

CC

I/O63

I/O62

I/O61

I/O60

V

(82)

(81)

(80)

(79)

(45)

(46)

(47)

(48)

I/O59

(78)

(77)

(49)

(50)

I/O58

I/O57

(76)

(73)
(72)
(71)
(70)
(69)
(68)
(67)
(66)
(65)

(62)
(61)
(60)
(59)

(58)
(57)
(56)
(55)
(54)
(41)

(51)

H7

I/O56

80

(75)

79
78
77
76
75
74
73
72
71
70
69
68
67
66

65
64
63
62
61
60

59
58
57
56
55
54
53
52
51

(52)

50

GND
GND
TD0
TRST
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/CLK3
GND
GND
V

CC

V

CC

I3/CLK2
I/O47
I/O46
I/O45

I/O44
I/O43
I/O42
I/O41
I/O40
I2
ENABLE
GND
GND

G7
G6
G5
G4
G3
G2
G1
G0

F0
F1
F2
F3
F4
F5
F6
F7

PIN DESIGNATIONS

I/CLK = Input or Clock
GND = Ground
I = Input
I/O = Input/Output
V

= Supply V oltage

CC

TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
TRST = Test Reset
ENABLE = Program

I/O24

I/O25

I/O29

I/O28

I/O30

I/O26

I/O27

D7D6D5D4D3D2D1

I/O31

D0

CC

V

GND

CC

V

GND

I/O32

I/O33

I/O34

E0E1E2E3E4E5E6

I/O36

I/O35

I/O37

I/O38

I/O39
E7

17466G-031

46 ispMACH 4A Family

100-PIN TQFP CONNECTION DIAGRAM (M4A3-64/64 AND M4A(3,5)-128/64)

Top View

100-Pin TQFP

A7A6A5A4A3A2A1

A0

H0H1H2H3H4H5H6

H7

M4A3-128/64
M4A5-128/64

A14

A12

A10A8A6A4A2

GND

GND

I/O7

I/O6

I/O5

9998979695949392919089888786858483828180797877

100

GND

TDI

A11
A13
A15

B15
B13
B11

A1
A3
A5
A7
A9

B9
B7
B5
B3
B1

I/O8

I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15

I0/CLK0

V
GND

I1/CLK1

I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23

TMS

TCK

GND

CC

B7
B6
B5
B4
B3
B2
B1
B0

C0
C1
C2
C3
C4
C5
C6
C7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

C7

26272829303132333435363738394041424344454647484950

GND

GND

I/O24

I/O25

I/O26

B14

B12

B10

D7D6D5D4D3D2D1

A0

I/O4

I/O3

I/O2

I/O1

I/O0

I/O27

I/O28

I/O29

I/O30

I/O31

B8B6B4B2B0

D0

VCCGND

I2

CC

V

GND

VCCI5

I/O Cell

PAL Block

CC

V

GND

GND

D0D2D4D6D8

I/O63

I/O62

I/O32

I/O33

C0C2C4C6C8

E0E1E2E3E4E5E6

I/O61

I/O34

I/O60

I/O35

I/O59

I/O36

D10

I/O58

I/O37

C10

D12

I/O57

I/O38

C12

D14

I/O56

I/O39

C14

E7

GND

GND

GND

76

GND

M4A3-64/64

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

GND
TDO
TRST
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/CLK3
GND
V

CC

I3/CLK2
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
ENABLE
GND

D1
D3
D5
D7
D9
D11
D13
D15

C15
C13
C11
C9
C7
C5
C3
C1

G7
G6
G5
G4
G3
G2
G1
G0

F0
F1
F2
F3
F4
F5
F6
F7

17466G-032a

PIN DESIGNATIONS

CLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output

= Supply V oltage

V

CC

TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
TRST = Test Reset
ENABLE = Program

ispMACH 4A Family 47

100-BALL caBGA CONNECTION DIAGRAM (M4A3-128/64)

Bottom View

100-Ball caBGA

10987654321

I/O63H7I/O60H4I/O57

GND

A

TRST GND

B

I/O53

C

G5

I/O50G2I/O55

D

E

F

G

H

J

K

CLK3/I3

I/O49G1I/O51G3I/O54

GND VCC

I/O41

CLK2/I2

F1

I/O44F4I/O45F5I/O46

I/O47

ENABLE GND

F7

I/O39E7I/O36E4I/O33

GND

10987654321

I/O61

H5

I/O62H6I/O58H2I/O56H0I/O2

TDO

I/O59H3I/O3A3I/O5A5I/O11B3I/O10

GND

G7

I/O40F0I/O52G4I/O48

I/O42F2I/O43F3I/O37E5I/O35E3I/O27

F6

I/O38E6I/O32

GND GND

H1

I5 VCC

VCC

G6

I/O34E2I/O24D0I/O26D2I/O30

GND

GND GND

E1

I/O0A0I/O6

I/O16C0I/O20C4I/O8

VCC

G0

VCC I2

E0

I/O1A1I/O4A4I/O7

A6

GND

A2

I/O22C6I/O19C3I/O17

D3

I/O25D1I/O28D4I/O31

A7

GND TDI

I/O14B6I/O13B5I/O12

CLK0/I0

B2

VCC GND

B0

C1

I/O23C7I/O18

GND

TCK

D6

I/O29

D5

GND TMS

D7

GND

I/O15

B7

B4

I/O9

B1

CLK1/I1

C2

I/O21

C5

GND

A

B

C

D

E

F

G

H

J

K

PIN DESIGNATIONS

CLK
GND
I
I/O
N/C
VCC
TDI
TCK
TMS
TDO
TRST
ENABLE

=

Clock

=

Ground

=

Input

=

Input/Output

=

No Connect

=

Supply Voltage

=

Test Data In

=

Test Clock

=

Test Mode Select

=

Test Data Out

=

Test Reset

=

Program

C7

48 ispMACH 4A Family

I/O Cell
PAL Block

17466G-100cabga

144-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-192/96)

Top View

144-Pin TQFP

B7B6B5B4B3B2B1B0A7A6A5A4A3A2A1

I/O95

I/O94

I/O93

I/O92

I/O91

144

143

142

141

GND

TDI

D7

I/O0

D6

I/O1

D5

I/O2

D4

I/O3

D3

I/O4

D2

I/O5

D1

I/O6

D0

I/O7

I2
I3

V

CC

GND

I4

C7

I/O8

C6

I/O9

C5

I/O10

C4

I/O11

C3

I/O12

C2

I/O13

C1

I/O14

C0

I/O15

GND

V

CC

E7

I/O16

E6

I/O17

E5

I/O18

E4

I/O19

E3

I/O20

E2

I/O21

E1

I/O22

E0

I/O23

TMS

TCK

GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

140

3738394041424344454647484950515253545556575859606162636465666768697071

CC

I/O90

I/O89

I/O88

GND

V

I/O87

139

138

137

136

135

134

C7

I/O86

133

I/O85

132

I/O84

131

I/O83

130

I/O82

129

I/O81

128

A0

I/O80I1I0

CLK0

127

126

125

124

I/O Cell

PAL Block

GND

123

VCCCLK3

122

121

I15

120

I14

119

I13

118

L0L1L2L3L4L5L6

I/O79

I/O78

I/O77

I/O76

I/O75

I/O74

117

116

115

114

113

112

I/O73

111

L7

I/O72

110

GND

109

108
107
106
105
104
103
102
101
100

72

GND
TDO
NC

K0

I/O71

K1

I/O70

K2

I/O69

K3

I/O68

K4

I/O67

K5

I/O66
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

I/O65

I/O64

I12

V

CC

GND

I11

I10

I/O63

I/O62

I/O61

I/O60

I/O59

I/O58

I/O57

I/O56

GND

V

CC

I/O55

I/O54

I/O53

I/O52

I/O51

I/O50

I/O49

I/O48

NC

GND

K6
K7

J0
J1
J2
J3
J4
J5
J6
J7

I0
I1
I2
I3
I4
I5
I6
I7

PIN DESIGNATIONS

CLK = Clock
GND = Ground
I = Input
I/O = Input/Output
V

= Supply V oltage

CC

TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out

GND

I/O24

I/O25

I/O26

I/O27

I/O28

F7F6F5F4F3F2F1

I/O29

I8

I/O30

I/O31

F0

I5I6I7

CLK1

GND

V

CC

CLK2

I9

I/O32

I/O33

I/O34

I/O35

I/O36

G0G1G2G3G4G5G6

I/O37

I/O38

I/O39
G7

CC

V

GND

I/O40

I/O41

I/O42

H0H1H2H3H4H5H6

I/O43

I/O44

I/O45

I/O46

H7

I/O47

ispMACH 4A Family 49

17466G-033

144-BALL fpBGA CONNECTION DIAGRAM (M4A3-192/96)

Bottom View

144-Ball fpBGA

121110987654321

GND

A

GND

B

GND TDO

C

I/O84 K4I/O82K2I/O80K0I/O92

D

I12

E

I10 I11 GND

F

I/O75 J3I/O74J2I/O73 J1I/O72

G

I/O79J7I/O78J6I/O77J5I/O76J4I/O66I2I/O57 H1I/O53 G5I/O41F1I/O33E1I/O37 E5I/O39

H

I/O64I0I/O65

J

I/O95L7I/O91

L3

I/O94L6I/O90L2I/O88

I/O93

L5

I/O87 K7I/O85 K5I/O81 K1I/O89 L1I/O5

I1

VCC

I/O69 I5I/O59

GBCLK3 I0

I13

L0

I14 GND

L4

I/086 K6I/O83

J0

VCC I1

GBCLK0

K3

VCC GND I7

H3

I/O0

A0

I/O1

A1

A5

I15 I3 GND

VCC

I/O2 A2I/O6 A6I/O8 B0I/O13B5I/O15

I/O3 A3I/O7A7I/O10B2I/O14 B6I/O31

I/O4

A4

VCC

I/O9 B1I/O26D2I/O23

I/O49

G1

GND

I/O11 B3I/O29

I/O35E3I/O38E6I/O16C0I/O17C1I/O18

GBCLK2

I/O12 B4I/O30 D6I/O27 D3I/O28

D5

C7

I/O19 C3I/O20 C4I/O21C5I/O22

I/O44F4I/O32E0I/O34E2I/O36

B7

D7

I2

I4 GND VCC

I/O25 D1I/O24

E7

GND

TDI

D4

D0

C6

C2

VCC

E4

A

B

C

D

E

F

G

H

J

I/O68 I4I/O67 I3I/O70I6I/O60

K

I/O71I7I/O62H6I/O58H2I/O55G7I/O51

I/O63H7I/O61H5I/O56H0I/O54G6I/O50

M

GND

L

GND

H4

GND

I/O52G4I/O48

G0

G3

G2

I9 GND

I8 GBCLK1 I5

VCC I6

I/O40F0I/O42F2I/O46

I/O45

F5

I/O43F3I/O47

TCK TMS

F6

F7

121110987654321

PIN DESIGNATIONS

CLK
GND
I
I/O
N/C
VCC
TDI
TCK
TMS
TDO
TRST
ENABLE

=

Clock

=

Ground

=

Input

=

Input/Output

=

No Connect

=

Supply Voltage

=

Test Data In

=

Test Clock

=

Test Mode Select

=

Test Data Out

=

Test Reset

=

Program

C7

I/O Cell
PAL Block

m4a3.192.96_144bga

GND

GND

K

L

M

50 ispMACH 4A Family

208-PIN PQFP CONNECTION DIAGRAM (M4A(3,5)-256/128 AND M4A3-256/160)

Top View

208-Pin PQFP

B15

B14

B13

B12

B11

C15
C14
C13
C12
C11
C10

D14
D12

E10

F10
F12

F13
F14
F15

B10B9B8B7B6B5B4B3B2B1B0

GND

I/O19

I/O18

I/O17

I/O16

I/O15

I/O14

I/O13

I/O12

GND

VCC

I/O11

I/O10

I/O9

I/O8

B7B6B5B4B3B2B1B0A7A6A5A4A3A2A1

GND

I/O15

I/O14

I/O13

I/O12

I/O11

I/O10

I/O9

I/O8

GND

VCC

I/O7

I/O6

I/O5

I/O4

208

207

206

205

204

203

202

201

200

199

198

197

196

195

VCC

VCC

I/O56

I/O68

I/O57

I/O69

=
=
=
=
=
=
=
=
=
=
=
=

I/O70

194

Clock
Ground
Input
Input/Output
No Connect
Supply Voltage
Test Data In
Test Clock
Test Mode Select
Test Data Out
Test Reset
Program

I/O58

I/O59

I/O71

GND

TDI

C7

I/O20

C6

I/O21

C5

I/O22

C4

I/O23

C3

I/O24

C2

I/O25

C1

I/O26

C9

C0

I/O27

C8

VCC

GND

D7

I/O28

C7

D6

I/O29

C6

D5

I/O30

C5

D4

I/O31

C4

D3

I/O32

C3

D2

I/O33

C2

D1

I/O34

C1

D0

I/O35

C0

I/O36
I/O37
GND

VCC

I/O38

D6

I/O39

D4

I/O40

E0

I/O41

E2

I/O42

E6

GND
I/O43

E0

I/O44

F0

E1

I/O45

F1

E2

I/O46

F2

E3

I/O47

F3

E4

I/O48

F4

E5

I/O49

F5

E6

I/O50

F6

E7

I/O51

F7

GND

VCC

F0

I/O52

F8

F1

I/O53

F9

F2

I/O54

F3

I/O55

F11

F4

I/O56

F5

I/O57

F6

I/O58

F7

I/O59

TMS
TCK

GND

I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23

VCC

GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31

GND

VCC

VCC
GND
GND

VCC

VCC
GND

I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39

GND

VCC

I/O40
I/O41
I/O42
I/O43
I/O44
I/O45
I/O46
I/O47

TMS

TCK

GND

2

TDI

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

I2

22

I3

23
24
25
26
27
28
29
30
31

I4

32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

5354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899

GND

I/O48

I/O49

G7G6G5G4G3G2G1G0H7H6H5H4H3H2H1

GND

I/O60

I/O61

G15

G14

PIN DESIGNATIONS

CLK
GND
I
I/O
N/C
VCC
TDI
TCK
TMS
TDO
TRST
ENABLE

I/O50

I/O51

I/O52

I/O53

I/O54

I/O55

I/O62

I/O63

I/O64

I/O65

I/O66

I/O67

G9G8G7G6G5G4G3G2G1

G11

G13

G12

G10

GND

GND

1

GND

I/O7

I/O3

193

I/O60

I/O72

I/O6

I/O2

192

I/O61

I/O73

I/O5

I/O1

191

I/O62

I/O74

A14

I/O4

I/O3

A0

I/O0I1I0

190

189

I5

I/O63
H0

I/O75

I/O76

G0

H14

A12

I/O2

188

I6

I/O77
H12

CLK0

CLK0

187

CLK1

CLK1

VCC

VCC

186

VCC

VCC

GND

GND

185

GND

GND

A6A4P4

I/O1

GND

184

GND

I/O78
H6

P6

I/O0

I/O159

I/O158

GND

VCC

VCC

GND

GND

183

182

181

180

C7

VCC

VCC

GND

GND

GND

I/O79

I/O80

I/O81

I4

I6

H4

P12

P14O0O1O2O3O4O5O6O7O8O9

VCC

CLK3

I/O157

I/O156

I/O155

I/O154

I/O153

I/O152

I/O151

P0P1P2P3P4P5P6

VCC

CLK3

I13

I12

I/O127

I/O126

I/O125

I/O124

I/O123

179

178

177

176

175

174

173

172

171

I/O Cell
PAL Block

I7

I8

VCC

I/O64

I/O66

I/O66

I/O67

I/O68

I0I1I2I3I4I5I6

I/O84

I/O85

I/O86

I/O87

I/O88

J0J1J2J3J4J5J6

VCC

CLK2

CLK2

I/O82
I12

I/O83

I14

O10

O11

O12

I/O150

I/O149

I/O148

VCC

GND

I/O147

I/O146

I/O145

I/O144

I/O143

P7

O0O1O2O3O4O5O6

I/O122

I/O121

I/O120

VCC

GND

I/O119

I/O118

I/O117

I/O116

I/O115

170

169

168

167

166

165

164

163

162

161

RECOMMEND TO TIE TO VCC

RECOMMEND TO TIE TO GND

100

VCC

GND

I/O69

I/O70

I/O71

I/O72

I/O73

I/O74

I/O75

I/O76

I7

J0J1J2J3J4J5J6

VCC

GND

I/O92

I/O93

I/O94

I/O95

I/O89

I/O90

I/O91
J7

I/O96

J8

J9

J11

J10

J12

O13

I/O142

I/O114

160

101

I/O77

I/O97
J13

O14

I/O141

I/O113

159

102

I/O78

I/O98
J14

O15

I/O140
O7

I/O112

158

103

I/O79
J7

I/O99
J15

GND

GND

157
156

155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120

109
108
107
106
105

104

GND

GND

119
118
117
116
115
114
113
112
111
110

M4A3-256/160

M4A(3, 5)-

256/128

GND
TDO
TRST
I/O111
I/O110
I/O109
I/O108
I/O107
I/O106
I/O105
I/O104
VCC
GND
I/O103
I/O102
I/O101
I/O100
I/O99
I/O98
I/O97
I/O96
I11
GND
VCC
VCC
GND
GND
VCC
VCC
GND
I10
I9
I/O95
I/O94
I/O93
I/O92
I/O91
I/O90
I/O89
I/O88
GND
VCC
I/O87
I/O86
I/O85
I/O84
I/O83
I/O82
I/O81
I/O80
ENABLE
GND

GND
TDO
NC
I/O139
I/O138
I/O137
I/O136
I/O135
I/O134
I/O133
I/O132
VCC
GND
I/O131
I/O130
I/O129
I/O128
I/O127
I/O126
I/O125
I/O124
I/O123
GND
I/O122
I/O121
I/O120
I/O119
I/O118
VCC
GND
I/O117
I/O116
I/O115
I/O114
I/O113
I/O112
I/O111
I/O110
I/O109
I/O108
GND
VCC
I/O107
I/O106
I/O105
I/O104
I/O103
I/O102
I/O101
I/O100
NC
GND

N15
N14
N13
N12
N11
N10
N9
N8

N7
N6
N5
N4
N3
N2
N1
N0
M10

M6
M2
M0
L4
L6

L12
L14
K0
K1
K2
K3
K4
K5
K6
K7

K8
K9
K10
K11
K12
K13
K14
K15

N7
N6
N5
N4
N3
N2
N1
N0

M7
M6
M5
M4
M3
M2
M1
M0

L0
L1
L2
L3
L4
L5
L6
L7

K0
K1
K2
K3
K4
K5
K6
K7

17466G-044

ispMACH 4A Family 51

208-PIN PQFP CONNECTION DIAGRAM (M4A3-384/160 AND M4A3-512/160)

Top View

208-Pin PQFP

GND
TDO
NC
I/O137
I/O136
I/O135
I/O134
I/O133
I/O132
I/O131
I/O130
VCC
GND
I/O129
I/O128
I/O127
I/O126
I/O125
I/O124
I/O123
I/O122
I/O121
GND
I/O120
I/O119
I/O118
I/O117
I/O116
VCC
GND
I/O115
I/O114
I/O113
I/O112
I/O111
I/O110
I/O109
I/O108
I/O107
I/O106
GND
VCC
I/O105
I/O104
I/O103
I/O102
I/O101
I/O100
I/O99
I/O98
NC
GND

M4A3-512/160

GND
TDO
NC

XF7

I/O137

XF6

I/O136

XF5

I/O135

XF4

I/O134

XF3

I/O133

XF2

I/O132

XF1

I/O131

XF0

I/O130
VCC
GND

XC7

I/O129

XC6

I/O128

XC5

I/O127

XC4

I/O126

XC3

I/O125

XC2

I/O124

XC1

I/O123

XC0

I/O122

XD5

I/O121
GND

XD3

I/O120

XD2

I/O119

XD0

I/O118

XA0

I/O117

XA2

I/O116
VCC
GND

XA5

I/O115

XA7

I/O114

XB0

I/O113

XB1

I/O112

XB2

I/O111

XB3

I/O110

XB4

I/O109

XB5

I/O108

XB6

I/O107

XB7

I/O106
GND
VCC

O0

I/O105

O1

I/O104

O2

I/O103

O3

I/O102

O4

I/O101

O5

I/O100

O6

I/O99

O7

I/O98
NC
GND

XK7
XK6
XK5
XK4
XK3
XK2
XK1
XK0

XJ7
XJ6
XJ5
XJ4
XJ3
XJ2
XJ1
XJ0
XL5

XL3
XL2
XL0
XE0
XE2

XE5
XE7
XG0
XG1
XG2
XG3
XG4
XG5
XG6
XG7

XF0
XF1
XF2
XF3
XF4
XF5
XF6
XF7

B7B6B5B4B3B2B1

GND

I/O17

I/O16

I/O15

B7B6B5B4B3B2B1

GND

I/O17

I/O16

I/O15

208

207

206

GND

TDI

F7

I/O18

F6

I/O19

F5

I/O20

F4

I/O21

F3

I/O22

F2

I/O23

F1

I/O24

F0

I/O25

VCC
GND

G7

I/O26

G6

I/O27

G5

I/O28

G4

I/O29

G3

I/O30

G2

I/O31

G1

I/O32

G0

I/O33

E7

I/O34

E5

I/O35

GND
VCC

E2

I/O36

E0

I/O37

L0

I/O38

L2

I/O39

L3

I/O40

GND

L5

I/O41

J0

I/O42

J1

I/O43

J2

I/O44

J3

I/O45

J4

I/O46

J5

I/O47

J6

I/O48

J7

I/O49

GND
VCC

K0

I/O50

K1

I/O51

K2

I/O52

K3

I/O53

K4

I/O54

K5

I/O55

K6

I/O56

K7

I/O57

TMS

TCK

GND

GND

1

TDI
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
I/O24
I/O25

VCC

GND
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I/O32
I/O33
I/O34
I/O35

GND

VCC
I/O36
I/O37
I/O38
I/O39
I/O40

GND
I/O41
I/O42
I/O43
I/O44
I/O45
I/O46
I/O47
I/O48
I/O49

GND

VCC
I/O50
I/O51
I/O52
I/O53
I/O54
I/O55
I/O56
I/O57

TMS

TCK

GND

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

C7
C6
C5
C4
C3
C2
C1
C0

F7
F6
F5
F4
F3
F2
F1
F0
E7
E5

E2

E0
H0
H2
H3

H5
G0
G1
G2
G3
G4
G5
G6
G7

J0

J1

J2

J3

J4

J5

J6

J7

205

5354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899

GND

I/O58

I/O59

I/O60

K7K6K5K4K3K2K1

B0

I/O14

I/O13

I/O12

I/O11

I/O10

GND

VCC

B0

I/O14

I/O13

I/O12

I/O11

I/O10

GND

VCC

204

203

202

201

200

199

198

PIN DESIGNATIONS

CLK
GND
I
I/O
N/C
VCC
TDI
TCK
TMS
TDO
TRST
ENABLE

VCC

I/O62

I/O63

I/O64

I/O65
K0

GND

I/O61

C7C6C5C4C3C2C1C0A7

I/O9

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

D7D6D5D4D3D2D1

I/O9

I/O8

I/O7

197

196

195

=
=
=
=
=
=
=
=
=
=
=
=

I/O66

I/O67

I/O68

I7I6I5I4I3I2I1I0L7

D0

I/O6

I/O5

I/O4

I/O3

I/O2

194

193

192

191

190

Clock
Ground
Input
Input/Output
No Connect
Supply Voltage
Test Data In
Test Clock
Test Mode Select
Test Data Out
Test Reset
Program

I/O69

I/O70

I/O71

I/O72

I/O73

I/O1
A7

I/O1
189

I/O74

A6

I/O0
A6

I/O0
188

I/O75
L6

CLK0

CLK0
187

CLK1

VCC

VCC

186

VCC

GND

GND

185

GND

A4A1XP1

I/O159
A4

I/O159
184

I/O76
L4L1M1

XP4

I/O158

I/O157

I/O156

GND

A1

XH1

XH4

I/O158

I/O157

I/O156

GND

183

182

181

180

C7

GND

I/O77

I/O78

I/O79
M4

XP6

XP7

XN0

XN1

VCC

CLK3

I/O155

I/O154

I/O153

I/O152

XE0

XE1

XH6

XH7

VCC

CLK3

I/O155

I/O154

I/O153

I/O152

179

178

177

176

175

174

I/O Cell
PAL Block

VCC

I/O80

I/O81

I/O82

I/O83

CLK2

M6M7P0P1P2P3P4P5P6

XN2

XN3

XN4

XN5

XN6

XN7

I/O151

I/O150

I/O149

I/O148

I/O147

I/O146

VCC

XE2

XE3

XE4

XE5

XE6

XE7

I/O151

I/O150

I/O149

I/O148

I/O147

I/O146

VCC

173

172

171

170

169

168

167

RECOMMEND TO TIE TO VCC

RECOMMEND TO TIE TO GND

I/O86

I/O87

I/O88

I/O89
P7

VCC

I/O84

I/O85

XO0

XO1

XO2

XO3

GND

I/O145

I/O144

I/O143

I/O142

XG0

XG1

XG2

XG3

GND

I/O145

I/O144

I/O143

I/O142

166

165

164

163

162

GND

I/O90

I/O91

I/O92

I/O93

N0N1N2N3N4N5N6

XO4

I/O141

XG4

I/O141
161

100

I/O94

XO5

XG5

I/O140

I/O95

I/O140

160

101

XO6

I/O139

XG6

I/O139
159

102

I/O96

XO7

I/O138

XG7

I/O138

I/O97
N7

GND

M4A3-384/160

GND

158

157

156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120

119
118
117
116
115
114
113
112
111

110
109
108
107
106
105

103

104

GND

GND

I/O58

I/O59

I/O60

I/O61

O7O6O5O4O3O2O1

I/O62

I/O63

I/O64

I/O65
O0

VCC

GND

I/O66

I/O67

N7N6N5N4N3N2N1

I/O68

I/O69

I/O70

I/O71

I/O72

I/O73

N0

I/O74
P7

I/O75
P6

CLK1

VCC

GND

I/O76
P4

I/O77
P1

I/O78
XA1

I/O79
XA4

GND

VCC

CLK2

I/O80

XA6

I/O81
XA7

52 ispMACH 4A Family

I/O82
XC0

I/O83
XC1

I/O84

XC2

I/O85
XC3

I/O86
XC4

I/O87
XC5

I/O88

XC6

I/O89

XC7

VCC

GND

I/O90
XB0

I/O91
XB1

I/O92
XB2

I/O93
XB3

I/O94
XB4

I/O95
XB5

I/O96
XB6

I/O97
XB7

GND

17466Ga-044

256-BALL BGA CONNECTION DIAGRAM (M4A(3,5)-256/128)

Bottom View

256-Ball BGA

GND

I/O82

K5

VCC

I/O79

J7

I/O77

J5

I/O73

J1

I/O70

I6

I/O66

I2

N/C

N/C

N/C

N/C

I/O61

H2

I/O57

H6

I/O54

G1

I/O50

G5

I/O48

G7

VCC

N/C

GND

21

GND

N/C

I/O78

J6

I/O75

J3

I/O72

J0

I/O69

I5

I/O65

I1

I/O64

I0

N/C

CLK2

CLK1

I/O63

H0

I/O59

H4

I/O58

H5

I/O56

H7

I/O55

G0

I/O53

G2

I/O52

G3

I/O49

G6

N/C

6

GND

I/O88

L7

I/O84

K3

I/O81

K6

I/O43

F3

I/O39

E7

GND

I/O87

K0

I/O85

K2

I/O80

K7

VCC

I/O46

F6

I/O42

F2

I/O40

F0

5

N/C

I/O83

K4

ENABLE

VCC

TDO

I/O76

J4

VCC

I/O67

I3

I7

N/C

N/C

I6

I/O60

H3

VCC

I/O51

G4

TMS

VCC

I/O47

F7

I/O45

F5

I/O44

F4

7

20 19 18 17 16 15 14 13 12 11 10 9

I/O96

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

N/C

GND

I/O113

O6

N/C

I/O117

O2

I/O119

O0

I/O122

P5

I/O125

P2

I/O127

P0

N/C

CLK3

CLK0

N/C

I/O0

A0

I/O1

A1

I/O5

A5

I/O8

B0

I/O11

B3

I/O13

B5

I/O14

B6

GND

N/C

VCC

I/O112

O7

I/O114

O5

I/O118

O1

I/O121

P6

I/O126

P1

N/C

N/C

N/C

N/C

I/O2

A2

I/O6

A6

I/O9

B1

I/O12

B4

I/O15

B7

VCC

N/C

GND

GND

I/O116

O3

I/O120

P7

I/O123

P4

GND

I12

GND

N/C

GND

N/C

N/C

GND

I1

GND

I/O4

A4

I/O7

A7

I/O10

B2

GND

GND

2019181716151413121110987654321

N4

I/O106

I/O109

N5

I/O111

TRST

VCC

TDI

I/O115

O4

VCC

I/O124

P3

I13

N/C

N/C

I0

I/O3

A3

VCC

N/C

TCK

VCC VCC

I/O16

C7

N/C

N/C

N1

N2

N7

VCC

I/O17

C6

I/O19

C4

I/O20

C3

I/O105

I/O108

GND

I/O100

GND

I/O103

M7

I/O107

N3

I/O110

N6

M4

I/O102

M6

I/O104

N0

VCC

M0

I/O98

M2

I/O101

M5

N/C

PIN DESIGNATIONS

CLK
GND
I
I/O
N/C
VCC
TDI
TCK
TMS
TDO
TRST
ENABLE

I/O18

C5

I/O21

C2

I/O22

C1

GND

=

Clock

=

Ground

=

Input

=

Input/Output

=

No Connect

=

Supply Voltage

=

Test Data In

=

Test Clock

=

Test Mode Select

=

Test Data Out

=

Test Reset

=

Program

I/O24D7I/O29

VCC

I/O23

I/O27

C0

D4

I/O25

I/O28

D6

D3

I/O26

I/O30

D5

D1

GND

N/C

I/O97

M1

I/O99

M3

D2

I/O31

D0

N/C

GND

GND

I11

N/C

N/C

I2 N/C

I3

N/C

GND

GND

N/C

I10

I9

C7

N/C

I4

GND

8

I/O95

GND

L0

I/O93

N/C

L2

I/O90

I/O94

L5

L1

I/O92

N/C

L3

I/O Cell
PAL Block

I/O35

N/C VCC N/C VCC

E3

I/O33

I/O37

E1

E5

I/O34

N/C

E2

I/O32

GND

E0

I/O91

L4

I/O89

L6

I/O86

K1

VCC

I/O41

F1

I/O38

E6

I/O36

E4

43

GND

GND

I/O74

J2

I/O71

I7

I/O68

I4

GND

I8

GND

N/C

N/C

GND

I/O62

H1

GND

I5

GND

N/C

N/C

N/C

GND

GND

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

17466G-045

ispMACH 4A Family 53

256-BALL fpBGA CONNECTION DIAGRAM (M4A3-256/192)

Bottom View

256-Ball fpBGA

16151413121110987654321

I/O167

I/O181

I/O180

A

N15

I/O165

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

I/O166

N13

I/O163

I/O164

N11

I/O158N6I/O159

I/O156

N4

I/O152N0I/O157N5I/O155

I/O147M6I/O150

I/O144M0I/O146M4I/145

I/O138L4I/O139L6I/O140

I/O143

I/O120K0I/O121

L14

I/O124K4I/O125K5I/O127

I/O128K8I/O129K9I/O131

I/O132

I/O133

K12

I/O134

I/O117

K14

I/O116

I/O115

J12

I/O114

I/O113J9I/O110J6I/O109J5I/O103

J10

O13

N14

N12

N7
NC

M12

K13

J13

J11

I/O177O9I/O174O6I/O172O4I/O191

O12

I/O182

I/O179

O14

NC

TDO GND GND VCC GND VCC GND GND VCC GND VCC

I/O162

N10

N3

I/O149

M10

OM2

L8

K1

K7

K11

I/O135

K15

I/O118

J14

I/O112J8I/O111J7I/O104J0I/O102

I/O175O7I/O173O5I/O168O0I/O187P6I/O0A0I/O5

O11

I/O183

I/O178

O15

VCC

GND

VCC

GND

GND

VCC

GND

GND

VCC GND VCC GND VCC GND GND VCC GND GND TCK

I/O119

J15

I/O170O2I/O171O3I/O189

O10

I/O160N8I/O161N9I/O190

I/O154N2I/O153N1I/O176O8I/O169O1I/O185P2I/O4A8I/O11B3I/O34

I/O148M8I/O151

I/O136L0I/O137

I/O142

I/O123K3I/O122

I/O130

I/O107J3I/O105J1I/O100I8I/O90H4I/O74G2I/O80G8I/O83

I/O108J4I/O106J2I/O101

M14

L2

I/O141

L12

L10

K2

I/O126K6I/O98I4I/O91H6I/O75G3I/O77G5I/O52E8I/O51

K10

I12

GCLK2

I14

I/O186P4I/O1A2I/O3

P14

I/O184P0I/O6

P10

I/O188P8I/O2A4I/O8

GCLK3

P12

VCC GND GND VCC

GND VCC VCC GND

GND VCC VCC GND

VCC GND GND VCC

I/O89H2I/O93

I10

I/O99I6I/O96I0I/O92H8I/O72G0I/O76G4I/O81G9I/O85

I/O97I2I/O88

H0

H10

GCLK1

GCLK0

A6

A10

I/O12B4I/O14B6I/O23

A12

I/O33C9I/O28

I/O27C3I/O24

I/O46

I/O41D2I/O40

I/O94

I/O79G7I/O84

H12

I/O95

I/O73G1I/O78G6I/O82

H14

I/O9B1I/O13B5I/O15B7I/O18

I/O7

I/O10B2I/O16B8I/O19

A14

NC GND

B0

C10

C4

C0

I/O45

D12

D10

D0

E6

I/O53

G11

E10

G12

B11

I/O22

B15

B14

I/O17B9I/O38

I/O36

C12

I/O32C8I/O30C6I/O29

VCC

I/O26C2I/O25C1I/O47

GND

I/O44D8I/O43D6I/O42

VCC

I/O49E2I/O48E0I/O50

GND

I/O55

VCC

GND

VCC

I/O87

E14

I/O59F3I/O60F4I/O57

I/O68

F12

TMS

G15

I/O71

G13

F15

I/O86

G10

G14

I/O20

B10

B12

I/O21

I/O35

I/O54

I/O63F7I/O58

I/O64F8I/O61

I/O65F9I/O62

I/O67

I/O70

B13

TDI

C14

C11

E12

F11

F14

NC

I/O39

C15

I/O37

C13

I/O31

C7

C5

D14

D4

E4

I/O56

F0

F1

F2

F5

F6

I/O66

F10

I/O69

F13

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

16151413121110987654321

PIN DESIGNATIONS

CLK
GND
I
I/O
N/C
VCC
TDI
TCK
TMS
TDO
TRST
ENABLE

=

Clock

=

Ground

=

Input

=

Input/Output

=

No Connect

=

Supply Voltage

=

Test Data In

=

Test Clock

=

Test Mode Select

=

Test Data Out

=

Test Reset

=

Program

C7

54 ispMACH 4A Family

I/O Cell
PAL Block

17466G-047

256-BALL BGA CONNECTION DIAGRAM - (M4A3-384/192)

Bottom View

256-Ball BGA

GND

I/O148

O6

VCC

I/O149

N4

I/O150

N2

I/O151

N0

I/O152

P4

I/O153

P1

I/O154

M5

I/O155

M1

I/O156

L4

I/O157

L5

I/O158

I0

I/O159

I4

I/O160

K0

I/O161

K4

I/O162

K7

VCC

I/O163

J6

GND

21

GND

I/O164

O7

I/O165

N7

I/O166

N5

I/O167

N3

I/O168

P5

I/O169

P3

I/O170

P0

I/O171

M4

CLK2

CLK1

I/O172

L0

I/O173

L7

I/O174

I1

I/O175

I3

I/O176

K1

I/O177

K2

I/O178

K3

I/O179

J7

I/O180

K6

20 19 18 17 16 15 14 13 12 11 10 9

GND

I/O28

XF5

VCC

I/O29

XG4

I/O30

XG1

I/O31

XE6

I/O32

XE5

I/O33

XE2

I/O34

XH4

I/O35

XH2

I/O36

A0

I/O37

A5

I/O38

D0

I/O39

D4

I/O40

D6

I/O41

B7

I/O42

B6

VCC

I/O43

C6

GND

I/O44

XC6

XF6

I/O59

I/O45

XC7

XF3

I/O46

I/O60

XF4

XF2

VCC

VCC

TDI

I/O47
XG2

VCC

I/O48

XE3

I/O49

XH7

I/O50

XH3

I/O51

A1

I/O52

A6

I/O53

D1

VCC

I/O54

D7

TCK

VCC VCC

I/O55

I/O61

C5

I/O56

I/O62

C3

I/O57

I/O63

C4

PIN DESIGNATIONS

CLK
GND
I
I/O
N/C
VCC
TDI
TCK
TMS
TDO

C2

F7

F6

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

I/O11

GND

XF7

I/O12

GND

XG7

I/O13

I/O0

XG5

XG6

I/O14

I/O1

XG3

XE7

I/O15

I/O2

XG0

XE0

I/O16

GND

XE1

I/O17

I/O3

XE4

XH6

I/O18

GND

XH5

I/O19

I/O4

XH1

XH0

CLK3

GND

I/O5

CLK0

A2

I/O20

I/O6

A3

A4

I/O21

GND

A7

I/O22

I/O7

D3

D2

I/O23

GND

D5

I/O8

I/O24

B3

B0

I/O9

I/O25

B4

B1

I/O26

I/O10

B2

B5

I/O27

GND

C7

GND

GND

2019181716151413121110987654321

I/O58

GND

I/O64

XC5

I/O65

XF1

I/O66

XF0

I/O67

C0

I/O68

C1

I/O69

F5

GND

I/O70

I/O76

XC2

I/O71

XC3

I/O72

XC4

VCC

=

Clock

=

Ground

=

Input

=

Input/Output

=

No Connect

=

Supply Voltage

=

Test Data In

=

Test Clock

=

Test Mode Select

=

Test Data Out

VCC

I/O73

F4

I/O74

F3

I/O75

F2

GND

XD6

I/O77

I/O84

XD7

XD5

I/O78

I/O85

XC0

XD4

I/O79

I/O86

XC1

XD3

I/O80F0I/O87E5I/O93E2I/O99

I/O81

I/O88

F1

I/O82

I/O89

E7

I/O83

GND

E6

GND

GND

I/O90

I/O96

XD2

XA0

I/O91

I/O97

XD1

XA1

I/O92

I/O98

XD0

XA2

C7

H2

I/O100

I/O94

H1

E1

E4

I/O101

I/O95

H0

E0

E3

GND

GND

GND

I/O102

XA3

I/O103

XA4

I/O104

XA7

I/O105

H5

I/O106

H4

I/O107

H3

GND

8

I/O108

XA5

I/O109

XA6

I/O110

XB2

I/O111

XB3

I/O Cell
PAL Block

I/O112

G0

I/O113

G1

I/O114

H7

I/O115

H6

7

I/O116

XB0

I/O117

XB1

I/O118

XB5

VCC

VCC

I/O119

G4

I/O120

G3

I/O121

G2

6

GND

I/O122

XB4

I/O123

O0

I/O124

O2

I/O125

J1

I/O126

J0

I/O127

G5

GND

I/O128

I/O129

I/O130

I/O131

I/O132

I/O133

5

XB7

XB6

O1

VCC

VCC

J2

G7

G6

43

I/O134

O3

I/O135

O4

I/O136

O5

VCC

TDO

I/O137

N1

VCC

I/O138

P2

I/O139

M6

I/O140

M0

I/O141

L3

I/O142

L6

I/O143

I5

VCC

I/O144

K5

TMS

VCC

I/O145

J5

I/O146

J4

I/O147

J3

GND

GND

I/O181

N6

I/O182

P7

I/O183

P6

GND

I/O184

M7

GND

I/O185

M3

I/O186

M2

GND

I/O187

L1

GND

I/O188

L2

GND

I/O189

I2

I/O190

I6

I/O191

I7

GND

GND

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

17466G-046

ispMACH 4A Family 55

256-BALL fpBGA CONNECTION DIAGRAM (M4A3-256/128)

Bottom View

256-Ball fpBGA

16151413121110987654321

I/O117O5I/O116O4I/O113O1I/O126P6I/O124

TRST

A

I12 NC NC NC CLK0

P4

I/O1A1I/O5A5I/O7A7I/O10B2I/O12

A

B4

I/O110N6I/O111N7I/O118O6I/O115O3I/O127P7I/O125P5I/O120

B

I/O108N4I/O109

C

D

I/O102

E

I/O98M2I/O103M7I/O101

F

G

I/O88

H

I/O91L3I/O92L4I/O93

J

K

L

I/O81K1I/O82K2I/O84

M

I/O85K5I/O86

N

N5

I/O104

NC

N0

NC

M6

I/O96

NC

M0

I10 I9 GND

L0

NC NC NC VCC NC NC VCC GND GND VCC NC NC VCC I4 NC

NC NC

K6

I/O119O7I/O114O2I/O122P2I/O123

NC

TDO GND GND VCC GND VCC GND GND VCC GND VCC

I/O107

N3

M5

I11 VCC NC

L5

I/O80

K0

K4

TENB VCC GND VCC GND VCC GND GND VCC GND GND TCK

I/O105N1I/O106

VCC

I/O100M4I/O99M3I/O112O0I/O121

GND

I/O89L1I/O90

I/O95L7I/O94

GND

I/O83

GND

I/O67I3I/O65

GND

N2

I/O97

M1

L2

L6

NC NC NC

K3

I1

VCC GND GND VCC

GND VCC VCC GND

GND VCC VCC GND I3 NC GND NC NC NC

NC NC NC I1

P0

NC NC I0

P3

I13 CLK3 NC NC

NC NC

P1

NC NC

I/O59H3I/O61

I/O58H2I/O48G0I/O51

H5

I/O2A2I/O8B0I/O11B3I/O13

I/O4A4I/O6A6I/O5B7I/O14

I/O0

NC GND

A0

I/O3A3I/O18

I/O17C1I/O28

I/O27D3I/O24

NC NC GND

G3

VCC

C2

GND

D4

VCC NC NC NC

D0

NC VCC

NC

B5

I/O23

TDI

B6

I/O9B1I/O22C6I/O21

I/O20C4I/O19C3I/O31

I/O16C0I/O30D6I/O29

I/O26D2I/O25

I/O35E3I/O36E4I/O33

I/O44F4I/O39E7I/O34

I/O40F0I/O37

D1

C7

C5

D7

D5

I2

I/O32

E0

E1

E2

E5

B

C

D

E

F

G

H

J

K

L

M

N

I/O87K7I/O77J5I/O78J6I/O79J7I/O68I4I/O66

P

I/O76J4I/O75J3I/O72J0I/O71I7I/O64

R

I/O74J2I/O73J1I/O70I6I/O69

T

I5

I0

I8 CLK2 NC NC CLK1 I5

NC NC NC I6

I2

I7 NC NC NC

I/O56H0I/O60H4I/O49G1I/O53G5I/O47F7I/O43F3I/O42

16151413121110987654321

PIN DESIGNATIONS

CLK
GND
I
I/O
N/C
VCC
TDI
TCK
TMS
TDO
TRST
ENABLE

=

Clock

=

Ground

=

Input

=

Input/Output

=

No Connect

=

Supply Voltage

=

Test Data In

=

Test Clock

=

Test Mode Select

=

Test Data Out

=

Test Reset

=

Program

C7

56 ispMACH 4A Family

I/O63H7I/O52G4I/O55

I/O57H1I/O62H6I/O50G2I/O54G6I/O46F6I/O45

G7

TMS

I/O41F1I/O38

E6

F2

F5

I/O Cell
PAL Block

m4a3.256.128_256bga

P

R

T

256-BALL fpBGA CONNECTION DIAGRAM (M4A3-384/192)

Bottom View

256-Ball fpBGA

16151413121110987654321

I/O175

I/O181

I/O180

I/O177

I/O166

I/O164

I/O191

I/O186

A

FX7

GX5

GX4

GX1

EX6

EX4

HX7

I/O173

I/O174

I/O182

I/O179

I/O167

I/O165

B

FX5

FX6

GX6

GX3

EX7

I/O171

C

D

E

F

G

H

J

K

L

M

N

P

R

T

I/O172

FX3

FX4

I/O150

I/O151

CX6

CX7

I/O148

N/C

CX4

I/O144

I/O149

CX0

CX5

I/O155

I/O158

DX3

DX6

I/O152

I/O154

DX0

DX2

I/O130

I/O131

AX2

AX3

I/O135

I/O136

AX7

BX0

I/O140

I/O141

BX4

BX5

I/O112O0I/O113O1I/O115

I/O116O4I/O117O5I/O119

I/O118O6I/O109N5I/O110N6I/O111N7I/O124P4I/O122P2I/O101M5I/O89L1I/O93L5I/O94L6I/O71I7I/O84K4I/O87

I/O108N4I/O107N3I/O104N0I/O127P7I/O120P0I/O102M6I/O99M3I/O96M0I/O92L4I/O64I0I/O68I4I/O81K1I/O85K5I/O79J7I/O75J3I/O74

I/O106N2I/O105N1I/O126P6I/O125P5I/O103

I/O183

N/C

TDO GND GND VCC GND VCC GND GND VCC GND VCC

I/O170

FX2

I/O147

CX3

I/O157

DX5

I/O153

DX1

I/O132

AX4

I/O137

BX1

I/O143

BX7

O3

O7

I/O178

GX7

GX2

I/O168

VCC

FX0

I/O146

GND

CX2

I/O156

VCC

DX4

I/O128

GND

AX0

I/O134

GND

AX6

I/O139

VCC

BX3

I/O114O2I/O142

GND

I/O123P3I/O121P1I/O100M4I/O90L2I/O66I2I/O80K0I/O83K3I/O61

GND

VCC GND VCC GND VCC GND GND VCC GND GND TCK

M7

I/O160

EX5

EX0

I/O162

I/O163

EX2

EX3

169

I/O190

FX1

HX6

I/O145

I/O176

CX1

GX0

I/O159

VCC GND GND VCC

DX7

I/O129

GND VCC VCC GND

AX1

I/O133

GND VCC VCC GND

AX5

I/O138

VCC GND GND VCC

BX2

I/O98M2I/O91L3I/O67I3I/O69I5I/O60H4I/O59

BX6

I/O97M1I/O88

CLK2

I/O1 A1I/O3

HX2

I/O187

HX3

I/O189

HX5

CLK3

I/O161

EX1

L0

A3

I/O0A0I/O5A5I/O7A7I/O26D2I/O8B0I/O11B3I/O13

I/O184

I/O6A6I/O28D4I/O30D6I/O15B7I/O14

HX0

I/O188

I/O2A2I/O24

HX4

I/O185

I/O4 A4I/O27D3I/O18

HX1

I/O95L7I/O65I1I/O70I6I/O82K2I/O86K6I/O78J6I/O77

CLK1

16151413121110987654321

I/O25D1I/O29D5I/O31D7I/O10B2I/O12

CLK0

N/C GND

D0

VCC

C2

I/O17C1I/O44

I/O43F3I/O40

I/O38E6I/O37

I/O33E1I/O32

GND

F4

VCC

F0

GND

E5

VCC

E0

GND

H3

VCC

H5

K7

B4

N/C

B5

I/O23

TDI

B6

I/O9B1I/O22C6I/O21

I/O20C4I/O19C3I/O47

I/O16C0I/O46F6I/O45

I/O42F2I/O41F1I/O39

I/O36E4I/O35E3I/O34

I/O57H1I/O56H0I/O58

I/O63H7I/O62H6I/O48

I/O51G3I/O52G4I/O49

I/O76J4I/O55G7I/O50

TMS

C7

C5

F7

F5

E7

E2

H2

G0

G1

G2

I/O72J0I/O53

G5

I/O73J1I/O54

G6

J2

J5

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

PIN DESIGNATIONS

CLK
GND
I
I/O
N/C
VCC
TDI
TCK
TMS
TDO
TRST
ENABLE

=

Clock

=

Ground

=

Input

=

Input/Output

=

No Connect

=

Supply Voltage

=

Test Data In

=

Test Clock

=

Test Mode Select

=

Test Data Out

=

Test Reset

=

Program

C7

I/O Cell
PAL Block

m4a3.384.192_256bga

ispMACH 4A Family 57

256-BALL fpBGA CONNECTION DIAGRAM (M4A3-512/192)

Bottom View

256-Ball fpBGA

16151413121110987654321

I/O159

I/O181

I/O180

I/O177

I/O174

I/O172

I/O191

I/O186

A

B

C

D

KX7

I/O157

KX5

I/O155

KX3

I/O150

JX6

OX5

OX4

OX1

NX6

NX4

PX7

I/O158

I/O182

I/O179

I/O175

I/O173

KX6

OX6

OX3

NX7

I/O156

KX4

I/O151

JX7

I/O183

OX7

I/O178

OX2

N/C

TDO GND GND VCC GND VCC GND GND VCC GND VCC

NX5

I/O170

NX2

I/O168

NX0

I/O171

NX3

I/O1A1I/O3

PX2

I/O187

PX3

I/O189

PX5

I/O184

A3

I/O0A0I/O5A5I/O7A7I/O18C2I/O8B0I/O11B3I/O13

I/O6A6I/O20C4I/O22C6I/O15B7I/O14

PX0

I/O17C1I/O21C5I/O21C7I/O10B2I/O12

CLK0

B4

N/C B

B5

I/O39

TDI

B6

I/O9B1I/O38F6I/O37

F7

F5

A

C

D

E

F

G

H

J

K

L

M

N

P

R

T

I/O148

JX4

I/O144

JX0

I/O163

LX3

I/O160

LX0

I/O122

EX2

I/O127

EX7

I/O140

GX4

I/O128

FX0

I/O132

FX4

I/O134

FX6

I/O108

BX4

I/O106

BX2

N/C

I/O149

JX5

I/O166

LX6

I/O162

LX2

I/O123

EX3

I/O136

GX0

I/O141

GX5

I/O129

FX1

I/O133

FX5

I/O109

BX5

I/O107

BX3

I/O105

BX1

I/O154

KX2

I/O147

JX3

I/O165

LX5

I/O161

LX1

I/O124

EX4

I/O137

GX1

I/O143

GX7

I/O131

FX3

I/O135

FX7

I/O110

BX6

I/O104

BX0

I/O118

CX6

I/O152

I/O153

VCC

KX0

I/O146

GND

JX2

I/O164

VCC

LX4

I/O120

GND

EX0

I/O126

GND

EX6

I/O139

VCC

GX3

I/O130

GND

FX2

I/O115

GND

CX3

VCC GND VCC GND VCC GND GND VCC GND GND TCK

I/O111

I/O116

BX7

CX4

I/O119

I/O112

CX7

CX0

I/O117

I/O103

CX5

AX7

I/O190

KX1

PX6

I/O145

I/O176

JX1

OX0

I/O167

VCC GND GND VCC

LX7

I/O121

GND VCC VCC GND

EX1

I/O125

GND VCC VCC GND

EX5

I/O138

VCC GND GND VCC

GX2

I/O142

I/O98

GX6

AX2

I/O113

I/O100

CX1

AX4

I/O114

I/O101

CX2

AX5

I/O102

I/O99

AX6

AX3

I/O97

CLK2

AX1

I/O188

CLK3

I/O169

NX1

I/O91P3I/O75N3I/O77N5I/O68L4I/O67

I/O90P2I/O74N2I/O80O0I/O83O3I/O69

I/O89P1I/O93P5I/O94P6I/O79N7I/O84O4I/O87

I/O96

AX0

I/O88

P0

I/O2A2I/O16

PX4

I/O185

PX1

I/O92P4I/O72N0I/O76N4I/O81O1I/O85O5I/O63K7I/O59K3I/O58

CLK1

C0

I/O4A4I/O19C3I/O34

I/O33F1I/O44

I/O43G3I/O40

I/O30E6I/O29

I/O25E1I/O24

I/O95P7I/O73N1I/O78N6I/O82O2I/O86O6I/O62K6I/O61

N/C GND

VCC

F2

GND

G4

VCC

G0

GND

E5

VCC

E0

GND

L3

VCC

L5

O7

I/O36F4I/O35F3I/O47

I/O32F0I/O46G6I/O45

I/O42G2I/O41G1I/O31

I/O28E4I/O27E3I/O26

I/O65L1I/O64L0I/O66

I/O71L7I/O70L6I/O48

I/O51J3I/O52J4I/O49

I/O60K4I/O55J7I/O50

TMS

G7

G5

E7

E2

L2

J0

J1

J2

I/O56K0I/O53

I/O57K1I/O54

J5

J6

K2

K5

E

F

G

H

J

K

L

M

N

P

R

T

16151413121110987654321

PIN DESIGNATIONS

CLK
GND
I
I/O
N/C
VCC
TDI
TCK
TMS
TDO
TRST
ENABLE

=

Clock

=

Ground

=

Input

=

Input/Output

=

No Connect

=

Supply Voltage

=

Test Data In

=

Test Clock

=

Test Mode Select

=

Test Data Out

=

Test Reset

=

Program

C7

58 ispMACH 4A Family

I/O Cell
PAL Block

m4a3.512.192_256bga

388-BALL fpBGA CONNECTION DIAGRAM (M4A3-512/256)

Bottom View

388-Ball fpBGA

22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

I/O243

I/O240

I/O241

I/O236

I/O231

I/O228

I/O226

I/O255

I/O251

I/O248

GND

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

N/C GND

I/O213

KX5

I/O210

I/O212

KX2

I/O207

I/O209

JX7

I/O203

I/O205

JX3

I/O200

I/O202

JX0

I/O221

I/O222

LX5

I/O218

I/O219

LX2

I/O197

I/O198

IX5

I/O192

I/O194

IX0

I/O184

I/O185

HX0

I/O188

I/O189

HX4

I/O160

I/O161

EX0

I/O164

I/O165

EX4

I/O167

I/O176

EX7

I/O178

I/O180

GX2

I/O182

GX6

I/O168

I/O170

FX0

I/O171

I/O174

FX3

I/O175

FX7

GND N/C

OX3

OX0

I/O245

OX5

TDO GND

I/O215

KX4

KX7

I/O211

KX1

KX3

I/O208

JX5

KX0

I/O204

JX2

JX4

I/O223

LX6

LX7

I/O220

LX3

LX4

I/O199

IX6

IX7

I/O195

IX2

IX3

I/O187

HX1

HX3

I/O191

HX5

HX7

I/O163

EX1

EX3

I/O166

EX5

EX6

I/O179

GX0

GX3

I/O183

GX4

GX7

I/O169

N/C

FX1

I/O173

FX2

FX5

GND

FX6

I/O142

GND

BX6

I/O139

BX3

OX1

NX4

MX7

MX4

MX2

PX7

PX3

I/O242

I/O238

I/O234

I/O232

I/O229

I/O224

OX2

NX6

NX2

NX0

MX5

I/O247

I/O244

I/O239

I/O235

OX7

OX4

NX7

I/O246

GND

I/O214

KX6

VCC VCC

I/O206

JX6

I/O201

JX1

VCC N/C GND GND GND GND GND GND GND GND N/C VCC

I/O216

LX0

I/O196

IX4

VCC

I/O190

HX6

VCC N/C GND GND GND GND GND GND GND GND N/C VCC

I/O177

GX1

I/O181

GX5

VCC VCC

I/O172

FX4

GND

I/O141

BX5

I/O140

BX4

I/O137

BX1

OX6

I/O143

BX7

I/O138

BX2

I/O151

CX7

I/O148

CX4

VCC

VCC

I/O136

BX0

I/O149

CX5

I/O146

CX2

I/O230

NX3

MX6

I/O237

I/O233

NX5

NX1

VCC VCC N/C

VCC N/C GND GND GND GND GND GND N/C VCC

I/O217

GND GND GND GND GND GND GND GND

LX1

I/O193

GND GND GND GND GND GND GND GND

IX1

I/O186

GND GND GND GND GND GND GND GND

HX2

I/O162

GND GND GND GND GND GND GND GND

EX2

VCC N/C GND GND GND GND GND GND N/C VCC

VCC VCC N/C

I/O150

I/O145

CX6

CX1

I/O147

I/O158

CX3

DX6

I/O144

I/O157

CX0

DX5

I/O159

I/O155

DX7

DX3

MX0

I/O227

MX3

VCC

VCC

I/O156

DX4

I/O154

DX2

I/O135

AX7

I/O253

PX5

CLK3

I/O254

PX6

I/O225

MX1

I/O152

DX0

I/O153

DX1

CLK2

I/O134

AX6

I/O133

AX5

22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

PIN DESIGNATIONS

I/O0A0I/O5A5I/O6A6I/O27D3I/O30D6I/O17C1I/O22C6I/O8B0I/O10

PX0

I/O249

I/O2

PX1

A2

I/O250

I/O11A1I/O7A7I/O25D1I/O16C0I/O18C2I/O23C7I/O11B3I/O15

PX2

I/O3A3I/O24

VCC

I/O252

I/O4A4I/O28

PX4

I/O131

I/O122P2I/O98

AX3

I/O123

VCC

P3

I/O132

I/O121P1I/O125P5I/O99M3I/O101M5I/O106N2I/O110N6I/O115O3I/O118

AX4

I/O130

I/O128

AX2

AX0

I/O129

I/O120P0I/O124P4I/O126P6I/O97M1I/O102M6I/O105N1I/O107N3I/O112O0I/O114O2I/O117

AX1

I/O26D2I/O29D5I/O31D7I/O20C4I/O9B1I/O12B4I/O13

CLK0

D0

N/C VCC VCC

D4

N/C VCC VCC

M2

I/O96

VCC

M0

I/O127P7I/O100M4I/O103M7I/O108N4I/O109N5I/O113O1I/O116

CLK1

C5

I/O33

E1

I/O58

H2

I/O69

I5

I/O89

L1

I/O104N0I/O111

N7

I/O19C3I/O21

VCC

VCC

VCC

I/O14

B6

I/O119

O7

B7

GND

I/O45F5I/O42F2I/O40F0I/O54

I/O53G5I/O51G3I/O49G1I/O39

I/O48G0I/O38E6I/O37E5I/O36

I/O63H7I/O62H6I/O61H5I/O60

VCC

I/O67I3I/O65I1I/O66I2I/O64

I/O88L0I/O71I7I/O70I6I/O68

I/O74J2I/O95L7I/O94L6I/O93

I/O78J6I/O76J4I/O73J1I/O72

I/O86K6I/O83K3I/O81K1I/O79

GND

O6

N/C GND

B2

GND TDI

B5

I/O47F7I/O44

GND

I/O46F6I/O43F3I/O41

I/O55G7I/O52G4I/O50

I/O35E3I/O34E2I/O32

I/O59H3I/O57H1I/O56

I/O92L4I/O91L3I/O90

I/O80K0I/O77J5I/O75

I/O87K7I/O84K4I/O82

GND TMS

O4

F4

F1

G6

G2

E7

E4

E0

H4

H0

I0

I4

L2

L5

J0

J3

J7

K2

I/O85

K5

GND TCK

GND

O5

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

CLK
GND
I
I/O
N/C
VCC
TDI
TCK
TMS
TDO
TRST
ENABLE

=

Clock

=

Ground

=

Input

=

Input/Output

=

No Connect

=

Supply Voltage

=

Test Data In

=

Test Clock

=

Test Mode Select

=

Test Data Out

=

Test Reset

=

Program

C7

I/O Cell
PAL Block

m4a3.512.256_388bga

ispMACH 4A Family 59

ispMACH 4A PRODUCT ORDERING INFORMATION

M
M

ispMACH 4A Devices Commercial and Industrial - 3.3V and 5V

Lattice programmable logic products are available with sev eral ordering options. The or der number (Valid Combination)
is formed by a combination of:

M4A3- 256 Y C

/

128

-7

FAMILY TYPE

4A3- = ispMACH 4A Family Low Voltage Advanced

Feature (3.3-V V

CC

)

48 = 48-pin TQFP for

M4A3-32/32 or M4A3-64/32
M4A5-32/32 or M4A5-64/32

4A5- = ispMACH 4A Family Advanced Feature (5-V VCC)

OPERATING CONDITIONS

MACROCELL DENSITY

32=32 Macrocells192 = 192 Macrocells
64=64 Macrocells256 = 256 Macrocells
96=96 Macrocells384 = 384 Macrocells
128=128 Macrocells512 = 512 Macrocells

C = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)

PACKAGE TYPE

A = Ball Grid Array (BGA)
J = Plastic Leaded Chip Carrier

(PLCC)

I/Os

/32 = 32 I/Os in 44-pin PLCC, 44-pin TQFP or 48-pin TQFP
/48 = 48 I/Os in 100-pin TQFP
/64 = 64 I/Os in 100-pin TQFP, 100-pin PQFP, or 100-ball caBGA

/96 = 96 I/Os in 144-pin TQFP or 144-ball fpBGA

V = Thin Quad Flat Pack (TQFP)
Y = Plastic Quad Flat Pack (PQFP)
FA = Fine-pitch Ball Grid Array

(fpBGA)

CA = Chip-array Ball Grid Array

(caBGA)

/128 = 128 I/Os in 208-pin PQFP, 256-ball BGA or 256-ball fpBGA
/160 = 160 I/Os in 208-pin PQFP
/192 = 192 I/Os in 256-ball BGA or 256-ball fpBGA
/256 = 256 I/Os in 388-ball fpBGA

SPEED

-5 =5.0 ns t

-55 =5.5 ns t

-6 =6.0 ns t

-65 =6.5 ns t

-7 =7.5 ns t

-10 =10 ns t

-12 =12 ns t

PD
PD
PD
PD

PD
PD
PD

-14 =14 ns tPD

3.3V Commercial Combinations

M4A3-32/32 -5, -7, -10 JC, VC, VC48
M4A3-64/32
M4A3-64/64 VC
M4A3-96/48 VC

-55, -7, -10

JC, VC, VC48

M4A3-128/64 YC, VC, CAC
M4A3-192/96 -6, -7, -10 VC, FAC
M4A3-256/128 -55, -65, -7, -10 YC, AC, FAC
M4A3-256/160
M4A3-256/192
M4A3-384/160
M4A3-384/192 AC, FAC
M4A3-512/160
M4A3-512/192 FAC

1
1

-7, -10

-65, -10, -12

YC
FAC
YC

YC

-7, -10, -12

M4A3-512/256 FAC

M4A3-32/32
M4A3-64/32 JI, VI, VI48
M4A3-64/64 VI
M4A3-96/48 VI
M4A3-128/64 YI, VI, CAI
M4A3-192/96
M4A3-256/128 YI, AI, FAI
M4A3-256/160
M4A3-256/192 FAI
M4A3-384/160
M4A3-384/192 AI, FAI
M4A3-512/160 YI
M4A3-512/192 FAI
M4A3-512/256 FAI

3.3V Industrial Combinations

JI, VI, VI48

-7, -10, -12

-7, -10, -12

-10, -12

VI, FAI

YI

YI

-10, -12, -14

1. Contact Factory for 6.5ns availability

60 ispMACH 4A Family

5V Commercial Combinations

M4A5-32/32 -5, -7, -10, JC, VC, VC48
M4A5-64/32
M4A5-96/48 VC
M4A5-128/64 YC, VC
M4A5-192/96 -6, -7, -10 VC
M4A5-256/128 -65, -7, -10 YC, AC

Most ispMACH devices are dual-marked with both Commer cial and Industrial gr ades. The Industrial speed grade is slower, i.e., M4A3­256/128-7YC-10YI

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice sales office to
confirm availability of specific valid combinations and to check on newly released combinations.

-55, -7, -10

JC, VC, VC48

Valid Combinations

M4A5-32/32 -7, -10, -12 JI, VI, VI48
M4A5-64/32
M4A5-96/48 VI
M4A5-128/64 YI, VI
M4A5-192/96 -7, -10, -12 VI
M4A5-256/128 -10, -12 YI, AI

5V Industrial Combinations

JI, VI, VI48

-7, -10, -12

Copyright © 2000 Lattice Semiconductor. All rights reserved.

ispMACH 4A Family 61

62 ispMACH 4A Family