LATTICE M4A5 128/64-10VN Datasheet

ispMACH

High Performance E

™

4A CPLD Family

2

CMOS

®

In-System Programmable Logic

FEATURES

◆

High-performance, E

◆

Flexible architecture for rapid logic designs

— Excellent First-Time-Fit
— SpeedLocking
— Central, input and output switch matrices for 100% routability and 100% pin-out retention

◆

High speed

— 5.0ns t
— 182MHz f

◆

32 to 512 macrocells; 32 to 768 registers

◆

44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages

◆

Flexible architecture for a wide range of design styles

Commercial and 7.5ns t

PD

CNT

— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— Programmable polarity
— Reset/ preset swapping

◆

Advanced capabilities for easy system integration

— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
— Programmable pull-up or Bus-Friendly
— Hot-socketing
— Programmable security bit
— Individual output slew rate control

◆

Advanced E

◆

Lead-free package options

2

CMOS process provides high-performance, cost-effective solutions

2

CMOS 3.3-V & 5-V CPLD families

TM

TM

performance for guaranteed fixed timing

and refit feature

Industrial

PD

TM

inputs and I/Os

Lead-

Free

Package

Options

Available!

Publication# ISPM4A Rev: M
Amendment/ 0

Issue Date: September 2006

Table 1. ispMACH 4A Device Features

3.3 V Devices
Feature M4A3-32 M4A3-64 M4A3-96 M4A3-128 M4A3-192 M4A3-256 M4A3-384 M4A3-512

Macrocells 32 64 96 128 192 256 384 512
User I/O options 32 32/64 48 64 96 128/160/192 160/192 160/192/256

(ns) 5.0 5.5 5.5 5.5 6.0 5.5 6.5 7.5

t

PD

f

(MHz) 182 167 167 167 160 167 154 125

CNT

t

(ns) 4.0 4.0 4.0 4.0 4.5 4.0 4.5 5.5

COS

(ns) 3.0 3.5 3.5 3.5 3.5 3.5 3.5 5.0

t

SS

Static Power (mA) 20 25/52 40 55 85 110/150 149/155 179
JTAG Compliant Yes Yes Yes Yes Yes Yes Yes Yes
PCI Compliant Yes Yes Yes Yes Yes Yes Yes Yes

5 V Devices
Feature M4A5-32 M4A5-64 M4A5-96 M4A5-128 M4A5-192 M4A5-256

Macrocells 32 64 96 128 192 256
User I/O options 32 32 48 64 96 128

(ns) 5.0 5.5 5.5 5.5 6.0 6.5

t

PD

f

(MHz) 182 167 167 167 160 154

CNT

t

(ns) 4.0 4.0 4.0 4.0 4.5 5.0

COS

(ns) 3.0 3.5 3.5 3.5 3.5 3.5

t

SS

Static Power (mA) 20 25 40 55 74 110
JTAG Compliant Yes Yes Yes Yes Yes Yes
PCI Compliant Yes Yes Yes Yes Yes Yes

2 ispMACH 4A Family

GENERAL DESCRIPTION

The ispMACH
Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools.
The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market,
greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512
macrocells with 100% utilization and 100% pin-out retention. The ispMACH 4A families offer 5-V (M4A5­xxx) and 3.3-V (M4A3-xxx) operation.

ispMACH 4A products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std. 1149.1)
interface. JTAG boundary scan testing also allows product testability on automated test equipment for
device connectivity.

All ispMACH 4A family members deliv er First-Time-Fit and easy system integration with pin-out retention
after any design change and refit. For both 3.3-V and 5-V operation, ispMACH 4A products can deliver
guaranteed fixed timing as fast as 5.0 ns t
using up to 20 product terms per output (Table 2).

™

4A family from Lattice offers an exceptionally flexible architecture and delivers a superior

and 182 MHz f

PD

through the SpeedLocking feature when

CNT

Table 2. ispMACH 4A Speed Grades

Speed Grade

Device

M4A3-32
M4A5-32

M4A3-64/32
M4A5-64/32

M4A3-64/64 C C, I C, I I
M4A3-96

M4A5-96
M4A3-128

M4A5-128
M4A3-192

M4A5-192
M4A3-256/128 C C C, I C, I I
M4A5-256/128 C C C, I I
M4A3-256/192

M4A3-256/160
M4A3-384 C C, I C, I I
M4A3-512 C C, I C, I I

-5 -55 -6 -65 -7 -10 -12 -14

C C, I C, I I

C C, I C, I I

C C, I C, I I

C C, I C, I I

C C, I C, I I

C C, I I

Note:

1. C = Commercial, I = Industrial

ispMACH 4A Family 3

The ispMACH 4A family offers 20 density-I/O combinations in Thin Quad Flat Pack (TQFP), Plastic
Quad Flat Pack (PQFP), Plastic Leaded Chip Carrier (PLCC), Ball Grid Array (BGA), fine-pitch BGA
(fpBGA), and chip-array BGA (caBGA) packages ranging from 44 to 388 pins (Table 3). It also offers I/O
safety features for mixed-voltage designs so that the 3.3-V devices can accept 5-V inputs, and 5-V devices
do not overdrive 3.3-V inputs. Additional features include Bus-Friendly inputs and I/Os, a programmable
power-down mode for extra power savings and individual output slew rate control for the highest speed
transition or for the lowest noise transition.

Table 3. ispMACH 4A Package and I/O Options

Package M4A3-32 M4A3-64 M4A3-96 M4A3-128 M4A3-192 M4A3-256 M4A3-384 M4A3-512

44-pin PLCC 32+2 32+2
44-pin TQFP 32+2 32+2
48-pin TQFP 32+2 32+2
100-pin TQFP 64+6 48+8 64+6
100-pin PQFP 64+6
100-ball caBGA 64+6
144-pin TQFP 96+16
144-ball fpBGA 96+16
208-pin PQFP 128+14, 160 160 160
256-ball fpBGA 128+14, 192 192 192
256-ball BGA 128+14 192
388-ball fpBGA 256

5 V Devices

Package M4A5-32 M4A5-64 M4A5-96 M4A5-128 M4A5-192 M4A5-256

44-pin PLCC 32+2 32+2
44-pin TQFP 32+2 32+2
48-pin TQFP 32+2 32+2
100-pin TQFP 48+8 64+6
100-pin PQFP 64+6
144-pin TQFP 96+16
208-pin PQFP 128+14

(Number of I/Os and dedicated inputs in Table)

3.3 V Devices

4 ispMACH 4A Family

FUNCTIONAL DESCRIPTION

The fundamental architecture of ispMACH 4A devices (Figure 1) consists of multiple, optimized PAL
blocks interconnected by a central switch matrix. The central switch matrix allows comm unication between
P AL bloc ks and routes inputs to the PAL blocks. T ogether , the PAL blocks and central switch matrix allo w
the logic designer to create large designs in a single device instead of having to use multiple devices.

The key to being able to make effective use of these devices lies in the interconnect schemes. In the
ispMACH 4A architecture, the macrocells are flexibly coupled to the product terms through the logic
allocator, and the I/O pins are flexibly coupled to the macrocells due to the output switch matrix. In
addition, more input routing options are provided by the input switch matrix. These resources provide the
flexibility needed to fit designs efficiently.

PAL Block

®

Clock/Input

Pins

Note 3

Dedicated
Input Pins

Clock

Generator

33/
34/

36

Logic
Array

Input

Switch

Matrix

Central Switch Matrix

Logic

Allocator

with XOR

4

Output/

Buried

Macrocells

16

PAL Block

PAL Block

Note 2

I/O

1616

8

Note 1

Output Switch Matrix

16

I/O Cells

Pins

I/O

Pins

I/O

Pins

17466G-001

Figure 1. ispMACH 4A Block Diagram and PAL Block Structure

Notes:

1. 16 for ispMACH 4A devices with 1:1 macrocell-I/O cell ratio (see next page).

2. Block clocks do not go to I/O cells in M4A(3,5)-32/32.

3. M4A(3,5)-192, M4A(3,5)-256, M4A3-384, and M4A3-512 have dedicated clock pins which cannot be used as inputs and do not connect to the central switch
matrix.

ispMACH 4A Family 5

Table 4. Architectural Summary of ispMACH 4A devices

ispMACH 4A Devices

M4A3-64/32, M4A5-64/32

M4A3-96/48, M4A5-96/48
M4A3-128/64, M4A5-128/64
M4A3-192/96, M4A5-192/96

M4A3-256/128, M4A5-256/128

M4A3-384

M4A3-512
Macrocell-I/O Cell Ratio 2:1 1:1
Input Switch Matrix Yes Yes
Input Registers Yes No
Central Switch Matrix Yes Yes
Output Switch Matrix Yes Yes

M4A3-32/32
M4A5-32/32

M4A3-64/64
M4A3-256/160
M4A3-256/192

1

The Macrocell-I/O cell ratio is defined as the number of macrocells versus the number of I/O cells
internally in a PAL block (Table 4).

The central switch matrix takes all dedicated inputs and signals from the input switch matrices and routes
them as needed to the P AL blocks . F eedback signals that return to the same P AL block still must go through
the central switch matrix. This mechanism ensures that PAL blocks in ispMACH 4A devices comm unicate
with each other with consistent, predictable delays.

The central switch matrix makes a ispMACH 4A device more adv anced than simply several PAL devices on
a single chip. It allows the designer to think of the device not as a collection of blocks, but as a single
programmable device; the software partitions the design into PAL bloc ks through the central switch matrix
so that the designer does not have to be concerned with the internal architecture of the device.

Each PAL block consists of:

Product-term array

◆

◆

Logic allocator
Macrocells

◆

◆

Output switch matrix

◆

I/O cells
Input switch matrix

◆

◆

Clock generator

Notes:

1. M4A3-64/64 internal switch matrix functionality embedded in central switch matrix.

6 ispMACH 4A Family

Product-T erm Array

The product-term array consists of a number of product terms that form the basis of the logic being
implemented. The inputs to the AND gates come from the central switch matrix (Table 5), and are provided
in both true and complement forms for efficient logic implementation.

Table 5. PAL Block Inputs

Device Number of Inputs to PAL Block

M4A3-32/32 and M4A5-32/32
M4A3-64/32 and M4A5-64/32
M4A3-64/64
M4A3-96/48 and M4A5-96/48
M4A3-128/64 and M4A5-128/64

M4A3-192/96 and M4A5-192/96
M4A3-256/128 and M4A5-256/128

M4A3-256/160 and M4A3-256/192
M4A3-384
M4A3-512

33
33
33
33
33

34
34

36
36
36

Logic Allocator

Within the logic allocator, product terms are allocated to macrocells in “product term clusters.” The
availability and distribution of product term clusters are automatically considered by the software as it fits
functions within a PAL block. The size of a product term cluster has been optimized to provide high
utilization of product terms, making complex functions using many product terms possible. Yet when few
product terms are used, there will be a minimal number of unused—or wasted—product terms left over.
The product term clusters available to each macrocell within a PAL block are shown in Tables 6 and 7.

Each product term cluster is associated with a macrocell. The size of a cluster depends on the configuration
of the associated macrocell. When the macrocell is used in synchronous mode
(Figure 2a), the basic cluster has 4 product terms. When the associated macrocell is used in asynchronous
mode (Figure 2b), the cluster has 2 product terms. Note that if the product term cluster is routed to a
different macrocell, the allocator configuration is not determined by the mode of the macrocell actually
being driven. The configuration is always set b y the mode of the macrocell that the cluster will drive if not
routed away, re gardless of the actual routing.

In addition, there is an extra product term that can either join the basic cluster to give an extended cluster,
or drive the second input of an exclusive-OR gate in the signal path. If included with the basic cluster, this
provides for up to 20 product terms on a synchronous function that uses four extended 5-product-term
clusters. A similar asynchronous function can have up to 18 product terms.

When the extra product term is used to extend the cluster, the value of the second XOR input can be
programmed as a 0 or a 1, giving polarity control. The possible configurations of the logic allocator are
shown in Figures 3 and 4.

ispMACH 4A Family 7

Table 6. Logic Allocator for All ispMACH 4A Devices (except M4A(3,5)-32/32)

Output Macrocell Available Clusters Output Macrocell Available Clusters

M

0

M

1

M

2

M

3

M

4

M

5

M

6

M

7

C

, C

, C

0

1

C

, C

, C

0

1

C

, C

, C

1

2

C

, C

, C

2

3

C

, C

, C

3

4

C

, C

, C

4

5

C

, C

, C

5

6

C6, C7, C8, C

2

, C

2

3

, C

3

4

, C

4

5

, C

5

6

, C

6

7

,

C

7

8
9

M

8

M

9

M

10

M

11

M

12

M

13

M

14

M

15

C

,

C

7

C

, C

8

C

, C

9

10

C

, C

10

C

, C

11

C

, C

12

C13, C14, C

C14, C

, C

, C

8

9

10

, C

, C

9

10

11

, C

, C

11

12

, C

, C

11

12

13

, C

, C

12

13

14

, C

, C

13

14

15

15

15

Table 7. Logic Allocator for M4A(3,5)-32/32

Output Macrocell Available Clusters Output Macrocell Available Clusters

M

0

M

1

M

2

M

3

M

4

M

5

M

6

M

7

C0, C1, C
C0, C1, C2, C
C1, C2, C3, C
C2, C3, C4, C
C3, C4, C5, C
C4, C5, C6, C

C5, C6, C

C6, C

7

2

3
4
5
6
7

7

M

8

M

9

M

10

M

11

M

12

M

13

M

14

M

15

C8, C9, C

10

C8, C9, C10, C

C9, C10, C11, C
C10, C11, C12, C
C11, C12, C13, C
C12, C13, C14, C

C13, C14, C

C14, C

15

11

12

13
14
15

15

Basic Product

Term Cluster

Extra

Product

Term

Basic Product

Term Cluster

Extra

Product

Term

n

0 Default

To n-1

To n-2

To n+1

From n-1

From n+1

From n+2

Prog. Polarity

n

Logic Allocator

0 Default

n

To Macrocell

a. Synchronous Mode

To n-1

To n-2

From n-1

nn

0 Default

To n+1

From n+1

From n+2

Logic Allocator

0 Default

n

To Macrocell

17466G-005

b. Asynchronous Mode

Figure 2. Logic Allocator: Configuration of Cluster “n” Set by Mode of Macrocell “n”

8 ispMACH 4A Family

Prog. Polarity

17466G-006

0

0

a. Basic cluster with XOR

d. Basic cluster routed away;

single-product-term, active high

a. Basic cluster with XOR

b. Extended cluster, active high c. Extended cluster, active low

e. Extended cluster routed away

17466G-007

Figure 3. Logic Allocator Configurations: Synchronous Mode

b. Extended cluster, active high c. Extended cluster, active low

d. Basic cluster routed away;

single-product-term, active high

e. Extended cluster routed away

17466G-008

Figure 4. Logic Allocator Configurations: Asynchronous Mode

Note that the configuration of the logic allocator has absolutely no impact on the speed of the signal. All
configurations have the same delay. This means that designers do not have to decide between optimizing
resources or speed; both can be optimized.

If not used in the cluster, the extra product ter m can act in conjunction with the basic cluster to provide
XOR logic for such functions as data comparison, or it can work with the D-,T-type flip-flop to provide
for J-K, and S-R register operation. In addition, if the basic cluster is routed to another macrocell, the extra
product term is still available for logic. In this case, the first X OR input will be a logic 0. This circuit has the
flexibility to route product ter ms elsewhere without giving up the use of the macrocell.

Product term clusters do not “wrap” around a PAL block. This means that the macrocells at the ends of
the block have fewer product terms available.

ispMACH 4A Family 9

Macrocell

The macrocell consists of a storage element, routing resources, a clock multiplexer, and initialization
control. The macrocell has two fundamental modes: synchronous and asynchronous (Figure 5). The mode
chosen only affects clocking and initialization in the macrocell.

Power-Up

Reset

PAL-Block

Initialization

Product Terms

Common PAL-block resource

Individual macrocell resources

From Logic Allocator

From

PAL-Clock

Generator

Block CLK0
Block CLK1
Block CLK2
Block CLK3

SWAP

AP AR

D/T/L

a. Synchronous mode

To Output and Input
Switch Matrices

Q

17466G-009

Power-Up

Reset

Individual

Initialization

Product Term

SWAP

To Output and Input

From Logic

Allocator

From PAL-Block

Clock Generator

Individual Clock

Product Term

Block CLK0
Block CLK1

AP AR

D/T/L

b. Asynchronous mode

Q

Switch Matrices

17466G-010

Figure 5. Macrocell

In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous mode will
generally be used, since it provides more product terms in the allocator.

10 ispMACH 4A Family

The flip-flop can be configured as a D-type or T-type latch. J-K or S-R registers can be synthesized. The
primary flip-flop configurations are shown in Figure 6, although others are possible. Flip-flop functionality
is defined in Table 8. Note that a J-K latch is inadvisable as it will cause oscillation if both J and K inputs
are HIGH.

a. D-type with XOR

c. Latch with XOR

AP AR

DQ

AP AR

LQ

G

AP AR

DQ

b. D-type with programmable D polarity

AP AR

LQ

G

d. Latch with programmable D polarity

AP AR

TQ

e. T-type with programmable T polarity

g. Combinatorial with programmable polarity

Figure 6. Primary Macrocell Configurations

f. Combinatorial with XOR

17466G-011

ispMACH 4A Family 11

Table 8. Register/Latch Operation

0,1, ↓ (↑)

↑ (↓)
↑ (↓)

0, 1, ↓ (↑)

↑ (↓)
↑ (↓)

1(0)
0(1)
0(1)

1

Q+

Q
0
1

Q
Q
Q

Q
0
1

Configuration Input(s) CLK/LE

D-type Register

T-type Register

D-type Latch

Note:

1. Polarity of CLK/LE can be programmed

D=X
D=0
D=1

T=X
T=0
T=1

D=X
D=0
D=1

Although the macrocell shows only one input to the register, the X OR gate in the logic allocator allows the
D-, T-type register to emulate J-K, and S-R behavior. In this case, the available product ter ms are divided
between J and K (or S and R). When configured as J-K, S-R, or T-type , the extra product term must be used
on the XOR gate input for flip-flop emulation. In any register type, the polarity of the inputs can be
programmed.

The clock input to the flip-flop can select any of the four P AL block cloc ks in synchronous mode, with the
additional choice of either polarity of an individual product term clock in the asynchronous mode.

The initialization circuit depends on the mode. In synchronous mode (Figure 7), asynchronous reset and
preset are provided, each driven by a product ter m common to the entire PAL block.

PAL-Block

Initialization

Product Terms

Power-Up

Reset

a. Power-up reset

Figure 7. Synchronous Mode Initialization Configurations

AP

D/T/L

PAL-Block

Initialization

Product Terms

AR

Q

17466G-012 17466G-013

Power-Up

Preset

b. Power-up preset

AP

D/L

AR

Q

12 ispMACH 4A Family

A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing
flexibility. In asynchronous mode (Figure 8), a single individual product term is provided for initialization.
It can be selected to control reset or preset.

Power-Up

Preset

b. Preset

AP

D/L/T

AR

Q

Individual

Reset

Product Term

Power-Up

Reset

a. Reset

AP

D/L/T

Individual

Preset

Product Term

AR

Q

17466G-014 17466G-015

Figure 8. Asynchronous Mode Initialization Configurations

Note that the reset/preset swapping selection feature effects power-up reset as well. The initialization
functionality of the f lip-flops is illustrated in Table 9. The macrocell sends its data to the output switch
matrix and the input switch matrix. The output switch matrix can route this data to an output if so desired.
The input switch matrix can send the signal back to the central switch matrix as feedback.

Note:

1. Transparent latch is unaffected by AR, AP

Table 9. Asynchronous Reset/Preset Operation

AR AP CLK/LE

0 0 X See Table 8
01X1
10X0
11X0

1

Q+

ispMACH 4A Family 13

Output Switch Matrix

The output switch matrix allows macrocells to be connected to any of several I/O cells within a P AL block.
This provides high flexibility in deter mining pinout and allows design changes to occur without effecting
pinout.

In ispMACH 4A devices with 2:1 Macrocell-I/O cell ratio, each PAL block has twice as many macrocells
as I/O cells. The ispMACH 4A output switch matrix allows for half of the macrocells to drive I/O cells
within a P AL block, in combinations according to Figure 9. Each I/O cell can choose from eight macrocells;
each macrocell has a choice of four I/O cells. The ispMACH 4A devices with 1:1 Macrocell-I/O cell ratio
allow each macrocell to drive one of eight I/O cells (Figure 9).

macrocells

Each I/O cell can

choose one of 8

macrocells in

all ispMACH 4A

devices.

MUX

M0
M1
M2
M3
M4
M5
M6
M7

I/O cell

M8

M9
M10
M11
M12
M13
M14
M15

Each macrocell can drive

one of 4 I/O cells in

ispMACH 4A devices with

2:1 macrocell-I/O cell ratio.

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7

M0
M1
M2
M3
M4
M5
M6
M7
M8

M9
M10
M11
M12
M13
M14
M15

Each macrocell can drive

one of 8 I/O cells in

ispMACH 4A devices with 1:1

macrocell-I/O cell ratio except

M4A(3, 5)-32/32 devices.

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15

M0
M1
M2
M3
M4
M5
M6
M7

M8

M9
M10
M11
M12
M13
M14
M15

Each macrocell can drive

one of 8 I/O cells in

M4A(3, 5)-32/32 devices.

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7

I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15

Figure 9. ispMACH 4A Output Switch Matrix

Table 10. Output Switch Matrix Combinations for ispMACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio

Macrocell Routable to I/O Cells

M0, M1 I/O0, I/O5, I/O6, I/O7
M2, M3 I/O0, I/O1, I/O6, I/O7
M4, M5 I/O0, I/O1, I/O2, I/O7
M6, M7 I/O0, I/O1, I/O2, I/O3
M8, M9 I/O1, I/O2, I/O3, I/O4

M10, M11 I/O2, I/O3, I/O4, I/O5

14 ispMACH 4A Family

Table 10. Output Switch Matrix Combinations for ispMACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio

Macrocell Routable to I/O Cells

M12, M13 I/O3, I/O4, I/O5, I/O6
M14, M15 I/O4, I/O5, I/O6, I/O7

I/O Cell Available Macrocells

I/O0 M0, M1, M2, M3, M4, M5, M6, M7
I/O1 M2, M3, M4, M5, M6, M7, M8, M9
I/O2 M4, M5, M6, M7, M8, M9, M10, M11
I/O3 M6, M7, M8, M9, M10, M11, M12, M13
I/O4 M8, M9, M10, M11, M12, M13, M14, M15
I/O5 M0, M1, M10, M11, M12, M13, M14, M15
I/O6 M0, M1, M2, M3, M12, M13, M14, M15
I/O7 M0, M1, M2, M3, M4, M5, M14, M15

Table 11. Output Switch Matrix Combinations for M4A3-256/160 and M4A3-256/192

Macrocell Routable to I/O Cells

M0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M1 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M2 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M3 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M4 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M5 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M6 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M7 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M8 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15

M9 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M10 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M11 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M12 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M13 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M14 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
M15 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15

I/O Cell Available Macrocells

I/O0 M0 M1 M2 M3 M4 M5 M6 M7
I/O1 M0 M1 M2 M3 M4 M5 M6 M7
I/O2 M0 M1 M2 M3 M4 M5 M6 M7
I/O3 M0 M1 M2 M3 M4 M5 M6 M7
I/O4 M0 M1 M2 M3 M4 M5 M6 M7
I/O5 M0 M1 M2 M3 M4 M5 M6 M7
I/O6 M0 M1 M2 M3 M4 M5 M6 M7
I/O7 M0 M1 M2 M3 M4 M5 M6 M7

ispMACH 4A Family 15

Table 11. Output Switch Matrix Combinations for M4A3-256/160 and M4A3-256/192

Macrocell Routable to I/O Cells

I/O8 M8 M9 M10 M11 M12 M13 M14 M15
I/O9 M8 M9 M10 M11 M12 M13 M14 M15

I/O10 M8 M9 M10 M11 M12 M13 M14 M15
I/O11 M8 M9 M10 M11 M12 M13 M14 M15
I/O12 M8 M9 M10 M11 M12 M13 M14 M15
I/O13 M8 M9 M10 M11 M12 M13 M14 M15
I/O14 M8 M9 M10 M11 M12 M13 M14 M15
I/O15 M8 M9 M10 M11 M12 M13 M14 M15

Table 12. Output Switch Matrix Combinations for M4A(3,5)-32/32

Macrocell Routable to I/O Cells

M0, M1, M2, M3, M4, M5, M6, M7 I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7

M8, M9, M10, M11, M12, M13, M14, M15 I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15

I/O Cell Available Macrocells

I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7 M0, M1, M2, M3, M4, M5, M6, M7

I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15 M8, M9, M10, M11, M12, M13, M14, M15

Table 13. Output Switch Matrix Combinations for M4A3-64/64

Macrocell Routable to I/O Cells

MO, M1 I/O0, I/O1, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15

M2, M3 I/O0, I/O1, I/O2, I/O3, I/O12, I/O13, I/O14, I/O15
M4, M5 I/O0, I/O1, I/O2,I/O3, I/O4,I/O5, I/O14, I/O15
M6, M7 I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7

M8, M9 I/O2, I/O3, I/O4, I/O5, I/O6, I/O7, I/O8, I/O9
M10, M11 I/O4, I/O5, I/O6, I/O7, I/O8, I/O9, I/O10, I/O11
M12, M13 I/O6, I/O7, I/O8, I/O9, I/O10, I/O11, I/O12, I/O13
M14, M15 I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15

I/O Cell Available Macrocells

I/O0, I/O1 M0, M1, M2, M3, M4, M5, M6, M7
I/O2, I/O3 M2, M3, M4, M5, M6, M7, M8, M9
I/O4, I/O5 M4, M5, M6, M7, M8, M9, M10, M11
I/O6, I/O7 M6, M7, M8, M9, M10, M11, M12, M13
I/O8, I/O9 M8, M9, M10, M11, M12, M13, M14, M15

I/O10, I/O11 M0, M1, M10, M11, M12, M13, M14, M15
I/O12, I/O13 M0, M1, M2, M3, M12, M13, M14, M15
I/O14, I/O15 M0, M1, M2, M3, M4, M5, M14, M15

16 ispMACH 4A Family

I/O Cell

The I/O cell (Figures 10 and 11) simply consists of a programmable output enable, a feedback path, and
flip-flop (except ispMACH 4A devices with 1:1 macrocell-I/O cell ratio). An individual output enable
product term is provided for each I/O cell. The feedback signal drives the input switch matrix.

Individual

Output Enable

Product Term
From Output

Switch Matrix

To Input

Switch
Matrix

D/L

Q

Block CLK0
Block CLK1
Block CLK2
Block CLK3

Power-up reset

17466G-017 17466G-018

Figure 10. I/O Cell for ispMACH 4A Devices with 2:1

Macrocell-I/O Cell Ratio

Figure 11. I/O Cell for ispMACH 4A Devices with 1:1

Individual

Output Enable

Product Term

From Output

Switch Matrix

To Input

Switch
Matrix

Macrocell-I/O Cell Ratio

The I/O cell (Figure 10) contains a flip-flop, which provides the capability for storing the input in a D-type
register or latch. The clock can be any of the PAL bloc k clocks. Both the direct and registered versions of
the input are sent to the input switch matrix. This allows for such functions as “time-domain-multiplex ed”
data comparison, where the first data value is stored, and then the second data value is put on the I/O pin
and compared with the previous stored value.

Note that the flip-flop used in the ispMACH 4A I/O cell is independent of the flip-flops in the macrocells.
It powers up to a logic low.

Zero-Hold-Time Input Register

The ispMACH 4A devices have a zero-hold-time (ZHT) fuse whic h controls the time delay associated with
loading data into all I/O cell registers and latches. When programmed, the ZHT fuse increases the data path
setup delays to input storage elements, matching equiv alent delays in the clock path. When the fuse is erased,
the setup time to the input storage element is minimized. This feature facilitates doing worst-case designs
for which data is loaded from sources which hav e low (or zero) minimum output propagation delays from
clock edges.

ispMACH 4A Family 17

Input Switch Matrix

The input switch matrix (Figures 12 and 13) optimizes routing of inputs to the central switch matrix.
Without the input switch matrix, each input and feedback signal has only one wa y to enter the central switch
matrix. The input switch matrix provides additional ways for these signals to enter the central switch matrix.

From Input Cell

Direct

From Macrocell 2

From Macrocell 1

Registered/Latched

From Macrocell

From I/O Pin

To Central Switch Matrix

17466G-002 17466G-003

Figure 12. ispMACH 4A with 2:1 Macrocell-I/O Cell

Ratio - Input Switch Matrix

To Central Switch Matrix

Figure 13. ispMACH 4A with 1:1 Macrocell-I/O Cell

Ratio - Input Switch Matrix

18 ispMACH 4A Family

PAL Block Clock Generation

Each ispMACH 4A device has four clock pins that can also be used as inputs. These pins drive a clock
generator in each PAL block (Figure 14). The clock generator provides four clock signals that can be used
anywhere in the PAL block. These four PAL block clock signals can consist of a large number of
combinations of the true and complement edges of the global clock signals. Table 14 lists the possible
combinations.

GCLK0

GCLK1

GCLK2

GCLK3

Figure 14. PAL Block Clock Generator

1. M4A(3,5)-32/32 and M4A(3,5)-64/32 have only two clock pins, GCLK0 and GCLK1. GCLK2 is tied to GCLK0, and GCLK3 is tied to GCLK1.

Table 14. PAL Block Clock Combinations

Block CLK0 Block CLK1 Block CLK2 Block CLK3

GCLK0
GCLK1
GCLK0
GCLK1

X
X
X
X

GCLK1
GCLK1
GCLK0
GCLK0

X
X
X
X

Block CLK0
(GCLK0 or GCLK1)

Block CLK1
(GCLK1 or GCLK0)

Block CLK2
(GCLK2 or GCLK3)

Block CLK3
(GCLK3 or GCLK2)

1

1

X
X
X

X
GCLK2 (GCLK0)
GCLK3

(GCLK1)
GCLK2 (GCLK0)
GCLK3

(GCLK1)

17466G-004

X
X
X

X
GCLK3 (GCLK1)
GCLK3 (GCLK1)

(GCLK0)

GCLK2
GCLK2

(GCLK0)

Note:

1. Values in parentheses are for the M4A(3,5)-32/32 and M4A(3,5)-64/32.

This feature provides high flexibility for partitioning state machines and dual-phase clocks. It also allows
latches to be driven with either polarity of latch enable, and in a master-slave configuration.

ispMACH 4A Family 19