Lattice LIF-MD6000 User Manual

Evaluation Board User Guide

FPGA-EB-02018 Version 1.0

June 2018

CrossLink LIF-MD6000 Master Link Board Revision C

CrossLink LIF-MD6000 Master Link Board - Revision C Evaluation Board User Guide

Contents

Acronyms in This Document ................................................................................................................................................. 4

1. Introduction .................................................................................................................................................................. 5

2. Headers and Test Connections ..................................................................................................................................... 7

3. Programming Circuit ..................................................................................................................................................... 8

3.1. Bridging Circuit .................................................................................................................................................... 8

3.2. I2C Expander ........................................................................................................................................................ 9

4. Power Supply .............................................................................................................................................................. 10

5. Status Indicators ......................................................................................................................................................... 12

6. SMA IO Link Board ...................................................................................................................................................... 13

7. Breakout IO Link Board ............................................................................................................................................... 15

8. Ordering Information .................................................................................................................................................. 18

References .......................................................................................................................................................................... 19

Technical Support Assistance............................................................................................................................................... 19

Appendix A. LIF-MD6000-ML-EVN-BRD Schematics ........................................................................................................... 20

Appendix B. LIF-MD6000-ML-EVN-BRD Bill of Materials .................................................................................................... 28

Appendix C. SMA-IOL-EVN-BRD Schematics ....................................................................................................................... 34

Appendix D. SMA-IOL-EVN-BRD Bill of Materials................................................................................................................ 35

Appendix E. B-IOL-EVN-BRD Schematics............................................................................................................................. 36

Appendix F. B-IOL-EVN-BRD Bill of Materials ..................................................................................................................... 37

Revision History ................................................................................................................................................................... 38

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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CrossLink LIF-MD6000 Master Link Board - Revision C Evaluation Board User Guide

Figures

Figure 1.1. Top View of Master Link Board and its Key Components ................................................................................... 6

Figure 1.2. Bottom View of Master Link Board..................................................................................................................... 6

Figure 3.1. Programming Block ............................................................................................................................................. 8

Figure 3.2. Bridging Block ..................................................................................................................................................... 9

Figure 3.3. I2C Expander Block .............................................................................................................................................. 9

Figure 4.1. Power Supply Block........................................................................................................................................... 10

Figure 6.1. Top View of SMA IO Link Board ........................................................................................................................ 14

Figure 6.2. Bottom View of SMA IO Link Board .................................................................................................................. 14

Figure 7.1. Top View of Breakout IO Link Board ................................................................................................................. 17

Figure 7.2. Bottom View of Breakout IO Link Board ........................................................................................................... 17

Tables

Table 2.1. Headers and Test Connectors .............................................................................................................................. 7

Table 4.1. Power LEDs ........................................................................................................................................................ 10

Table 4.2. Device Power Rail Summary and Test Points ..................................................................................................... 11

Table 5.1. Status LED I/O Map ............................................................................................................................................ 12

Table 6.1. Headers and Test Connectors ............................................................................................................................ 13

Table 6.2. U1 Connector Description .................................................................................................................................. 13

Table 7.1. Headers and Test Connectors ............................................................................................................................ 15

Table 7.2. U1 Connector Description .................................................................................................................................. 15

Table 7.3. J2 Header Description ........................................................................................................................................ 16

Table 8.1. Ordering Information ......................................................................................................................................... 18

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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CrossLink LIF-MD6000 Master Link Board - Revision C

Acronym

Definition

CMOS

Complementary Metal-Oxide Semiconductor

CSI-2

Camera Serial Interface

DSI

Display Serial Interface

FTDI

Future Technology Devices International

I2C

Inter-Integrated Circuit

Input/Output

LVDS

Low-Voltage Differential Signaling

MIPI

Mobile Industry Processor Interface

SPI

Serial Peripheral Interface

Evaluation Board User Guide

Acronyms in This Document

A list of acronyms used in this document.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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CrossLink LIF-MD6000 Master Link Board - Revision C Evaluation Board User Guide

1. Introduction

This document describes the Lattice Semiconductor CrossLink™ LIF-MD6000 Master Link Board –Revision C (Rev C) that supports a variety of demos, encompassing different signaling logic standards bridging with MIPI® CSI-2/DSI interface. The board‘s key component is the CrossLink Family device that features built in MIPI D-PHY hard blocks to support different bridging solutions.

For the latest information about this board, including optional Tx/Rx Link boards, demo files, further documentation and more, see the Lattice website at: www.latticesemi.com/masterlink.

For details about the CrossLink device, refer to CrossLink Family Data Sheet (FPGA-DS-02007).

The content of this user guide includes descriptions of on-board jumper settings, programming circuit, a complete set of schematics, and bill of materials for LIF-MD6000 Master Link Rev C board.

Refer to Appendix A, B, C, D, E, F for the schematic and BOM of the CrossLink LIF-MD6000 Master Link Rev C board and the schematics and BOMs of the Breakout IO Link and SMA IO Link boards that are included in the demo kit.

Circuits on the development kit board:

 Programming Circuit

 Mini USB Type-B connector to FTDI  FTDI to CrossLink using SPI  FTDI to CrossLink using I  FTDI to XO3LF device using JTAG

 CrossLink

 MIPI CSI-2/DSI hard block  Bridging of multiple signaling standards  SPI flash configuration  General Purpose Input/Output  LED display

 LCMXO3LF-1300E

 I

C muxing

Figure 1.1 shows the top view of the LIF-MD6000 Master Link Rev C board and its key components. Figure 1.2 shows

the bottom view of the board.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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CrossLink LIF-MD6000 Master Link Board - Revision C

Tx Connectors 1 and 2 (U9, U7)

Power Switch (SW1)

External Power Input

External Power Jack (J3)

LCMXO3L-1300E (U19)

USB 2.0 Mini-B (J2)

JTAG Header (J1)

FTDI Chip (U1)

SPI Flash Device (U14)

Rx Connectors (U11, U12)

Power LEDs

LIF-MD6000-CSFBGA81

Programming Header (J18)

Debug and Configuration LEDs

Reset and wake-up buttons Switch (SW2/SW4/SW5)

Clock Source Selection (J26, J27)

Bank 1, 2 Voltage Selection

Headers (J24, J25)

External Clock SMA Inputs

MachXO3 Reset (SW3)

Debug Header (J28)

Debug Header (J31)

Evaluation Board User Guide

Figure 1.1. Top View of Master Link Rev C Board and its Key Components

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

6 FPGA-EB-02018-1.0

Figure 1.2. Bottom View of Master Link Rev C Board

CrossLink LIF-MD6000 Master Link Board - Revision C

Part

Description

Setting

External JTAG interface - For LCMX03 only

—

mini-B USB connector

—

External 12V power jack

—

External clock input for MIPI D-PHY reference clock

—

SW2 selector

OPEN-NOP, SHORT-CONFIGURATION RESET

External 12 V terminal block

Open

External 5 V terminal block

Open

J16

SPI/I2C programming selector for LIF-MD6000

1-2 (SPI), 2-3 (I2C)

J18

External SP/I2C access for LIF-MD6000

—

J19

SPI Flash chip select

OPEN-OFF, SHORT-ON

J22

External reference clock input for MIPI D-PHY reference clock

—

J23

LCMXO3L debug header

—

J24

VCCIO1 Bank voltage selector

1-2 (2.5 V), 2-3 (3.3 V), 2-4 (1.2 V)

J25

VCCIO2 Bank voltage selector

1-2 (2.5 V), 2-3 (3.3 V), 2-4 (1.2 V)

J26

Internal/External clock and I2C SDA Mux

1-2 (CLK_INT), 2-3 (CLK_EXT), 2-4 (SDA)

J27

Internal/External reference clock and I2C SCL Mux

1-2 (CLK_INT_REF), 2-3 (CLK_EXT_REF), 2-4 (SCL)

J28

Reveal analyzer signal connector

—

J29

Reset signal voltage selector

1-2 (VCCIO2), 2-3 (VCCIO0)

J31

External SPI/I2C access for LCMXO3L

—

J32

LCMXO3L configuration header

—

J35

SPI/I2C programming selector for LIF-MD6000

1-2 (SPI), 2-3 (I2C)

J36

SPI/I2C programming selector for LIF-MD6000

1-2 (SPI), 2-3 (I2C)

J37

FT2232H reset

OPEN-NORMAL OP, SHORT-RESET

SW1

External adaptor power ON/OFF

—

SW2

Configuration reset for LIF-MD6000

—

SW3

External reset for LCMXO3L

—

SW4*

External reset for LIF-MD6000

—

SW5

PMU WAKEUP Switch for LIF-MD6000

—

Tx Connectors for external interface

—

Tx Connectors for external interface

—

U11

Rx Connectors for external interface

—

U12

Rx Connectors for external interface

—

Evaluation Board User Guide

2. Headers and Test Connections

Figure 1.1 shows the top view of the Master Link Rev C board. The headers and test connections on the board provide

access to LIF-MD6000 Master Link Rev C board circuits. Table 2.1 lists the headers and test connectors.

Table 2.1. Headers and Test Connectors

*Note: Some CrossLink demos utilize this reset signal to ball G9 of Bank 2 while it is configured as a 1.2 V Bank. However, LVCMOS12

inputs are no longer supported across all 3 Banks. Lattice Diamond® Software 3.9 and later will not allow this signal to be placed on a

1.2 V Bank. If it is necessary to recompile one of these demo projects, the necessary modifications should be made to the project and the board to move this reset signal to a non-1.2 V Bank on CrossLink.

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CrossLink LIF-MD6000 Master Link Board - Revision C

USB Mini-B

(J2)

FTDI Chip (U1)

SPI Flash (U14)

LIF-MD6000

CSFBGA81 (U8)

LCMXO3LF-1300E

MG121 (U19)

JTAG

SPI

SPI/I2C

Evaluation Board User Guide

3. Programming Circuit

The Mini-B USB connector is used for programming the board by using Lattice Diamond Programmer software.

Figure 3.1 shows the programming block of LIF-MD6000 Master Link Rev C board.

The Mini-B USB connector interfaces to the FTDI FT2232H IC. The FTDI IC works with Diamond Programmer software to provide interfaces for:

 JTAG – to program MachXO3 LCMXO3LF-1300E  SPI – to program CrossLink and/or SPI Flash Memory

 I

C – to program CrossLink

Figure 3.1. Programming Block

3.1. Bridging Circuit

Figure 3.2 shows the block diagram of bridging of different standard interfaces. The CrossLink device is used as a

bridging device that supports a variety of I/O standards. This demo board supports development of the following interface bridges:

 1:1 MIPI DSI Display Interface Bridge  1:2 MIPI DSI Display Interface Bridge  2:1 MIPI CSI-2 Image Sensor Aggregator Bridge  CMOS to MIPI CSI-2 Image Sensor Interface Bridge  MIPI CSI-2 to CMOS Image Sensor Interface Bridge  MIPI DSI to CMOS Display Interface Bridge  OpenLDI LVDS to MIPI DSI Display Interface Bridge  CMOS to MIPI DSI Display Interface Bridge

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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CrossLink LIF-MD6000 Master Link Board - Revision C

LIF-MD6000

CSFBGA81 (U8)

Rx Connector 1

Rx Connector 2

D-PHY I/F/

CMOS

D-PHY Rx/

LVDS/CMOS

D-PHY Rx/

LVDS/CMOS

Tx Connector 2

Tx Connector 1

D-PHY I/F/

CMOS

LCMXO3LF-1200E-

MG121 (U19)

Rx Connector 1

Rx Connector 2

LIF-MD6000

CSFBGA81 (U8)

H e a d e

I2C

2 X I2C

Evaluation Board User Guide

Figure 3.2. Bridging Block

3.2. I

C Expander

Figure 3.3 shows the block diagram of the I2C expander. The LCMXO3LF-1200E device is used as an I2C expander and it

supports a single master and multiple slave devices connected to the board. The master I2C interface is connected to the Tx header and the slave device I2C interface is connected to the Rx connectors supporting any slave device access from the master based on the slave address.

Figure 3.3. I2C Expander Block

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CrossLink LIF-MD6000 Master Link Board - Revision C

12 V to 5 V

converter

LDO

Power adaptor

Mini-B USB

5 V

U15

U17

12 V

U18

1.2 V

3.3 V

2.5 V

1.8 V

Voltage Rail

LEDs

Color

D26

Green

3.3

D25

Green

2.5

D29

Green

1.8

D28

Green

1.2

D27

Green

Evaluation Board User Guide

4. Power Supply

The power supply to the development kit is provided by the Mini-B USB connector or from an external adaptor.

Figure 4.1 shows the power supply block of the CrossLink LIF-MD6000 Master Link Rev C board. The external adaptor

provides 12 V power source through voltage regulators on the board to CrossLink and LCMXO3LF-1300E, as well as to the external boards connected to Tx and Rx Headers. The Mini-B USB connector provides 5 V to the various voltage regulators and is also used for device programming. Each I/O and core voltage rail on the board is accessible by a test point on the board. The current flowing to each rail can be measured using a 1 Ω resistor placed in the path of each voltage rail.

Table 4.1 lists the device power rails. There are five voltage regulators on the board used to supply the 5 V, 3.3 V, 2.5V

1.8 V, and 1.2 V rails. The input to these regulators is either from the Mini-B USB connector (J2), an external 12 V adaptor (J3), or an external power supply to the terminal blocks of J8 or J9. Switch SW1 is used to connect or disconnect power to the board.

Table 4.1. Power LEDs

Table 4.2 lists the board voltage rails, including the rail source voltage, test point number, and current sense resistor

number.

Figure 4.1. Power Supply Block

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CrossLink LIF-MD6000 Master Link Board - Revision C

Voltage Rail

Source Rail

Current Sense Resistor

Test Points

12 V — —

12V0

5 V

12 V — 5V0

+3.3 V

5 V — 3V3

+2.5 V

5 V — 2V5

+1.8 V

5 V — —

+1.2 V

5 V — 1V2

VCC_CORE

+1.2 V

R19

VCC_CORE1

VCCIO0

+2.5 V / +3.3 V

R20 / R24

VCCIO0

VCCIO1

+1.2 V / +2.5 V / +3.3 V

R21 / R25 / R434 / R448

VCCIO1

VCCIO2

+1.2 V / +2.5 V / +3.3 V

R28 / R33 / R435 / R449

VCCIO2

VCC_DPHY

+1.2 V

R417

VCC_DPHY

1K_VCC_CORE

+1.2 V

R190

1K_VCC_CORE1

1K_VCCIO0

+2.5 V / +3.3 V

R410 / R411

1K_VCCIO0

1K_VCCIO1

+2.5 V / +3.3 V

R184 / R185

1K_VCCIO1

1K_VCCIO2

+2.5 V / +3.3 V

R186 / R187

1K_VCCIO2

1K_VCCIO3

+2.5 V / +3.3 V

R188 / R189

1K_VCCIO3

Evaluation Board User Guide

Table 4.2. Device Power Rail Summary and Test Points

FPGA-EB-02018-1.0 11

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

CrossLink LIF-MD6000 Master Link Board - Revision C

Device

LED

Net Name

Color

CrossLink

CMOS_IO_1

Blue

CrossLink

CMOS_IO_2

Blue

CrossLink

CMOS_IO_3

Blue

CrossLink

CMOS_IO_4

Blue

CrossLink

D10

CDONE

Green

LCMX03LF-1300E

D23

DONE

Red

LCMX03LF-1300E

D30

LED1

Blue

LCMX03LF-1300E

D31

LED2

Blue

LCMX03LF-1300E

D32

LED3

Blue

LCMX03LF-1300E

D33

LED4

Blue

Evaluation Board User Guide

5. Status Indicators

The LED status indicators on the board show power, configuration, and application status. Table 5.1 lists the status LED I/O map.

Table 5.1. Status LED I/O Map

12 FPGA-EB-02018-1.0

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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Lattice LIF-MD6000 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Acronyms in This Document

1. Introduction

2. Headers and Test Connections

3. Programming Circuit

3.1. Bridging Circuit

4. Power Supply

5. Status Indicators