LATTICE LC 4032V-75TN48C Datasheet

®

Coolest Power

TM

ispMACH 4000V/B/C/Z Family

3.3V/2.5V/1.8V In-System Programmable
SuperFAST High Density PLDs

May 2009 Data Sheet DS1020

Features

Coolest Price

 High Performance

•f

= 400MHz maximum operating frequency

MAX

•t

= 2.5ns propagation delay

PD

• Up to four global clock pins with programmable
clock polarity control

• Up to 80 PTs per output

 Ease of Design

• Enhanced macrocells with individual clock,
reset, preset and clock enable controls

• Up to four global OE controls

• Individual local OE control per I/O pin

• Excellent First-Time-Fit

• Fast path, SpeedLocking

TM

and refit

TM

Path, and wide-PT

path

• Wide input gating (36 input logic blocks) for fast
counters, state machines and address decoders

 Zero Power (ispMACH 4000Z) and Low

Power (ispMACH 4000V/B/C)

• Typical static current 10µA (4032Z)

• Typical static current 1.3mA (4000C)

• 1.8V core low dynamic power

• ispMACH 4000Z operational down to 1.6V V

CC

 Broad Device Offering

• Multiple temperature range support
– Commercial: 0 to 90°C junction (T
– Industrial: -40 to 105°C junction (T
– Extended: -40 to 130°C junction (T

• For AEC-Q100 compliant devices, refer to

LA-ispMACH 4000V/Z Automotive Data Sheet

 Easy System Integration

• Superior solution for power sensitive consumer
applications

• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O

• Operation with 3.3V (4000V), 2.5V (4000B) or

1.8V (4000C/Z) supplies

• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI
interfaces

• Hot-socketing

• Open-drain capability

• Input pull-up, pull-down or bus-keeper

• Programmable output slew rate

• 3.3V PCI compatible

• IEEE 1149.1 boundary scan testable

• 3.3V/2.5V/1.8V In-System Programmable
(ISP™) using IEEE 1532 compliant interface

• I/O pins with fast setup path

• Lead-free package options

TM

)

j

)

j

)

j

Table 1. ispMACH 4000V/B/C Family Selection Guide

ispMACH

4032V/B/C

Macrocells 32 64 128 256 384 512

I/O + Dedicated Inputs 30+2/32+4 30+2/32+4/

t

(ns) 2.52.52.73.03.53.5

PD

t

(ns) 1.81.81.82.02.02.0

S

t

(ns) 2.22.22.72.72.72.7

CO

f

(MHz) 400 400 333 322 322 322

MAX

Supply Voltages (V) 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V

Pins/Package 44 TQFP

48 TQFP

1. 3.3V (4000V) only.

2. 128-I/O and 160-I/O configurations.

3. Use 256 ftBGA package for all new designs. Refer to PCN#14A-07 for 256 fpBGA package discontinuance.

© 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

ispMACH

4064V/B/C

64+10

44 TQFP
48 TQFP

100 TQFP 100 TQFP

ispMACH

4128V/B/C

64+10/92+4/

96+4

128 TQFP

144 TQFP

64+10/96+14/

128+4/160+4

1

ispMACH

4256V/B/C

100 TQFP

144 TQFP

176 TQFP

256 ftBGA

fpBGA

2, 3

ispMACH

4384V/B/C

128+4/192+4 128+4/208+4

1

176 TQFP

2

/

256 ftBGA/

fpBGA

3

ispMACH

4512V/B/C

176 TQFP

256 ftBGA/

fpBGA

3

www.latticesemi.com 1 DS1020_23.1

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

Table 2. ispMACH 4000Z Family Selection Guide

ispMACH 4032ZC ispMACH 4064ZC ispMACH 4128ZC ispMACH 4256ZC

Macrocells 32 64 128 256

I/O + Dedicated Inputs 32+4/32+4 32+4/32+12/

tPD (ns) 3.5 3.7 4.2 4.5

t

(ns) 2.2 2.5 2.7 2.9

S

tCO (ns) 3.0 3.2 3.5 3.8

f

(MHz) 267 250 220 200

MAX

Supply Voltage (V) 1.8 1.8 1.8 1.8

Max. Standby Icc (µA) 20 25 35 55

Pins/Package 48 TQFP

56 csBGA

64+10/64+10

48 TQFP
56 csBGA
100 TQFP

132 csBGA

64+10/96+4 64+10/96+6/

100 TQFP

132csBGA

128+4

100 TQFP

132 csBGA

176 TQFP

ispMACH 4000 Introduction

The high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend
of Lattice’s two most popular architectures: the ispLSI

®

2000 and ispMACH 4A. Retaining the best of both families,
the ispMACH 4000 architecture focuses on significant innovations to combine the highest performance with low
power in a flexible CPLD family.

The ispMACH 4000 combines high speed and low power with the flexibility needed for ease of design. With its
robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil­ity, routing, pin-out retention and density migration.

The ispMACH 4000 family offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O com­binations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA) and Fine Pitch Thin BGA (ftBGA) packages
ranging from 44 to 256 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key
parameters.

The ispMACH 4000 family has enhanced system integration capabilities. It supports 3.3V (4000V), 2.5V (4000B)
and 1.8V (4000C/Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely
driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The ispMACH
4000 also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up
resistors, pull-down resistors, open drain outputs and hot socketing. The ispMACH 4000 family members are 3.3V/

2.5V/1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary
scan testing capability also allows product testing on automated test equipment. The 1532 interface signals TCK,
TMS, TDI and TDO are referenced to V

(logic core).

CC

Overview

The ispMACH 4000 devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected
by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which
contain multiple I/O cells. This architecture is shown in Figure 1.

2

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

Figure 1. Functional Block Diagram

V

I/O

Block

I/O Bank 0

I/O

Block

CCO0

GND

GOE0

GOE1

16

16

VCCGND

Generic

Logic
Block

Generic

Logic
Block

CLK0/I

CLK1/I

CLK2/I

CLK3/I

ORP ORP

ORP ORP

Generic

16

Logic
Block

Generic

16 16

Logic
Block

16

16

36

36

36

Global Routing Pool

36

16

TCK

TMS

TDI

TDO

CCO1

V

I/O

Block

I/O

Block

GND

I/O Bank 1

The I/Os in the ispMACH 4000 are split into two banks. Each bank has a separate I/O power supply. Inputs can
support a variety of standards independent of the chip or bank power supply. Outputs support the standards com­patible with the power supply provided to the bank. Support for a variety of standards helps designers implement
designs in mixed voltage environments. In addition, 5V tolerant inputs are specified within an I/O bank that is con­nected to V

of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces.

CCO

ispMACH 4000 Architecture

There are a total of two GLBs in the ispMACH 4032, increasing to 32 GLBs in the ispMACH 4512. Each GLB has
36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into the GRP to be
connected to the inputs of any other GLB on the device. Even if feedback signals return to the same GLB, they still
must go through the GRP. This mechanism ensures that GLBs communicate with each other with consistent and
predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them to the associ­ated I/O cells in the I/O block.

Generic Logic Block

The ispMACH 4000 GLB consists of a programmable AND array, logic allocator, 16 macrocells and a GLB clock
generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O pins are decou­pled from macrocells through the ORP. Figure 2 illustrates the GLB.

3

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

Logic Allocator

36 Inputs

from GRP

16 Macrocells

To ORP

To GRP

To

Product Term

Output Enable

Sharing

1+OE

16 MC Feedback Signals

Clock

Generator

1+OE

1+OE

1+OE

1+OE

1+OE

1+OE

CLK0

CLK1

CLK2

CLK3

1+OE

AND Array

36 Inputs,

83 Product Terms

Figure 2. Generic Logic Block

AND Array

The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are
used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con­nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic
allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and
Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being
fed to the macrocells.

Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0.
There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND
Array.

4

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

PT0
PT1

Cluster 0

PT2
PT3
PT4

In[0]
In[34]
In[35]

Note:
Indicates programmable fuse.

PT80

PT81
PT82

Shared PT Clock

Shared PT Initialization
Shared PTOE

PT76
PT77
PT78
PT79

PT75

Cluster 15

Figure 3. AND Array

Enhanced Logic Allocator

Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term
cluster is associated with a macrocell. The cluster size for the ispMACH 4000 family is 4+1 (total 5) product terms.
The software automatically considers the availability and distribution of product term clusters as it fits the functions
within a GLB. The logic allocator is designed to provide three speed paths: 5-PT fast bypass path, 20-PT Speed
Locking path and an up to 80-PT path. The availability of these three paths lets designers trade timing variability for
increased performance.

The enhanced Logic Allocator of the ispMACH 4000 family consists of the following blocks:

• Product Term Allocator

• Cluster Allocator

• Wide Steering Logic

Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB.

Figure 4. Macrocell Slice

n

Cluster

Individual Product

Term Allocator

to

n-1ton-2

to

n+1

5-PT

from

Cluster

Allocator

5

from

n-1

n+2

from

n-4

From

n-4

from

n+1

1-80

PTs

To XOR (MC)

To n+4

SuperWIDE™
Steering Logic

Fast 5-PT
Path

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

Product Term Allocator

The product term allocator assigns product terms from a cluster to either logic or control applications as required
by the design being implemented. Product terms that are used as logic are steered into a 5-input OR gate associ­ated with the cluster. Product terms that used for control are steered either to the macrocell or I/O cell associated
with the cluster. Table 3 shows the available functions for each of the five product terms in the cluster. The OR gate
output connects to the associated I/O cell, providing a fast path for narrow combinatorial functions, and to the logic
allocator.

Table 3. Individual PT Steering

Product Term Logic Control

PTn Logic PT Single PT for XOR/OR

PT

n+1 Logic PT Individual Clock (PT Clock)

PT

n+2 Logic PT Individual Initialization or Individual Clock Enable (PT Initialization/CE)

PT

n+3 Logic PT Individual Initialization (PT Initialization)

PT

n+4 Logic PT Individual OE (PTOE)

Cluster Allocator

The cluster allocator allows clusters to be steered to neighboring macrocells, thus allowing the creation of functions
with more product terms. Table 4 shows which clusters can be steered to which macrocells. Used in this manner,
the cluster allocator can be used to form functions of up to 20 product terms. Additionally, the cluster allocator
accepts inputs from the wide steering logic. Using these inputs, functions up to 80 product terms can be created.

Table 4. Available Clusters for Each Macrocell

Macrocell Available Clusters

M0 — C0 C1 C2

M1 C0 C1 C2 C3

M2 C1 C2 C3 C4

M3 C2 C3 C4 C5

M4 C3 C4 C5 C6

M5 C4 C5 C6 C7

M6 C5 C6 C7 C8

M7 C6 C7 C8 C9

M8 C7 C8 C9 C10

M9 C8 C9 C10 C11

M10 C9 C10 C11 C12

M11 C10 C11 C12 C13

M12 C11 C12 C13 C14

M13 C12 C13 C14 C15

M14 C13 C14 C15 —

M15 C14 C15 — —

Wide Steering Logic

The wide steering logic allows the output of the cluster allocator n to be connected to the input of the cluster alloca­tor n+4. Thus, cluster chains can be formed with up to 80 product terms, supporting wide product term functions
and allowing performance to be increased through a single GLB implementation. Table 5 shows the product term
chains.

6

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

Table 5. Product Term Expansion Capability

Expansion

Chains

Macrocells Associated with Expansion Chain

(with Wrap Around)

Max PT/

Macrocell

Chain-0 M0 M4 M8 M12 M0 75

Chain-1 M1 M5 M9 M13 M1 80

Chain-2 M2 M6 M10 M14 M2 75

Chain-3 M3 M7 M11 M15 M3 70

Every time the super cluster allocator is used, there is an incremental delay of t

. When the super cluster alloca-

EXP

tor is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super clus­ter is steered to M (n+4), then M (n) is ground).

Macrocell

The 16 macrocells in the GLB are driven by the 16 outputs from the logic allocator. Each macrocell contains a pro­grammable XOR gate, a programmable register/latch, along with routing for the logic and control functions.
Figure 5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input
from the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable
delay in this path allows designers to choose between the fastest possible set-up time and zero hold time.

Figure 5. Macrocell

Power-up

Initialization

Shared PT Initialization

PT Initialization (optional)

PT Initialization/CE (optional)

Single PT

From Logic Allocator

Block CLK0
Block CLK1
Block CLK2
Block CLK3

PT Clock (optional)

Shared PT Clock

Delay

RP

D/T/L Q

CE

From I/O Cell

To ORP

To GRP

Enhanced Clock Multiplexer

The clock input to the flip-flop can select any of the four block clocks along with the shared PT clock, and true and
complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The
eight sources for the clock multiplexer are as follows:

• Block CLK0

• Block CLK1

7

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

• Block CLK2

• Block CLK3

• PT Clock

• PT Clock Inverted

• Shared PT Clock

•Ground

Clock Enable Multiplexer

Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the fol­lowing four sources:

• PT Initialization/CE

• PT Initialization/CE Inverted

• Shared PT Clock

• Logic High

Initialization Control

The ispMACH 4000 family architecture accommodates both block-level and macrocell-level set and reset capability.
There is one block-level initialization term that is distributed to all macrocell registers in a GLB. At the macrocell
level, two product terms can be “stolen” from the cluster associated with a macrocell to be used for set/reset func­tionality. A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing
flexibility.

Note that the reset/preset swapping selection feature affects power-up reset as well. All flip-flops power up to a
known state for predictable system initialization. If a macrocell is configured to SET on a signal from the block-level
initialization, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a
signal from the block-level initialization or is not configured for set/reset, then that macrocell will RESET on power­up. To guarantee initialization values, the V

rise must be monotonic, and the clock must be inactive until the reset

CC

delay time has elapsed.

GLB Clock Generator

Each ispMACH 4000 device has up to four clock pins that are also routed to the GRP to be used as inputs. These
pins drive a clock generator in each GLB, as shown in Figure 6. The clock generator provides four clock signals that
can be used anywhere in the GLB. These four GLB clock signals can consist of a number of combinations of the
true and complement edges of the global clock signals.

Figure 6. GLB Clock Generator

CLK0

Block CLK0

CLK1

CLK2

Block CLK1

Block CLK2

CLK3

Block CLK3

8

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

Output Routing Multiplexer

OE Routing Multiplexer

ORP
Bypass
Multiplexer

From Macrocell

From PTOE

To I/O

Cell

To I/O

Cell

Output

OE

5-PT Fast Path

Output Routing Pool (ORP)

The Output Routing Pool allows macrocell outputs to be connected to any of several I/O cells within an I/O block.
This provides greater flexibility in determining the pinout and allows design changes to occur without affecting the
pinout. The output routing pool also provides a parallel capability for routing macrocell-level OE product terms. This
allows the OE product term to follow the macrocell output as it is switched between I/O cells. Additionally, the out­put routing pool allows the macrocell output or true and complement forms of the 5-PT bypass signal to bypass the
output routing multiplexers and feed the I/O cell directly. The enhanced ORP of the ispMACH 4000 family consists
of the following elements:

• Output Routing Multiplexers

• OE Routing Multiplexers

• Output Routing Pool Bypass Multiplexers

Figure 7 shows the structure of the ORP from the I/O cell perspective. This is referred to as an ORP slice. Each
ORP has as many ORP slices as there are I/O cells in the corresponding I/O block.

Figure 7. ORP Slice

Output Routing Multiplexers

The details of connections between the macrocells and the I/O cells vary across devices and within a device
dependent on the maximum number of I/Os available. Tables 5-9 provide the connection details.

Table 6. ORP Combinations for I/O Blocks with 8 I/Os

I/O Cell Available Macrocells

I/O 0 M0, M1, M2, M3, M4, M5, M6, M7

I/O 1 M2, M3, M4, M5, M6, M7, M8, M9

I/O 2 M4, M5, M6, M7, M8, M9, M10, M11

I/O 3 M6, M7, M8, M9, M10, M11, M12, M13

I/O 4 M8, M9, M10, M11, M12, M13, M14, M15

I/O 5 M10, M11, M12, M13, M14, M15, M0, M1

I/O 6 M12, M13, M14, M15, M0, M1, M2, M3

I/O 7 M14, M15, M0, M1, M2, M3, M4, M5

9

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

Table 7. ORP Combinations for I/O Blocks with 16 I/Os

I/O Cell Available Macrocells

I/O 0 M0, M1, M2, M3, M4, M5, M6, M7

I/O 1 M1, M2, M3, M4, M5, M6, M7, M8

I/O 2 M2, M3, M4, M5, M6, M7, M8, M9

I/O 3 M3, M4, M5, M6, M7, M8, M9, M10

I/O 4 M4, M5, M6, M7, M8, M9, M10, M11

I/O 5 M5, M6, M7, M8, M9, M10, M11, M12

I/O 6 M6, M7, M8, M9, M10, M11, M12, M13

I/O 7 M7, M8, M9, M10, M11, M12, M13, M14

I/O 8 M8, M9, M10, M11, M12, M13, M14, M15

I/O 9 M9, M10, M11, M12, M13, M14, M15, M0

I/O 10 M10, M11, M12, M13, M14, M15, M0, M1

I/O 11 M11, M12, M13, M14, M15, M0, M1, M2

I/O 12 M12, M13, M14, M15, M0, M1, M2, M3

I/O 13 M13, M14, M15, M0, M1, M2, M3, M4

I/O 14 M14, M15, M0, M1, M2, M3, M4, M5

I/O 15 M15, M0, M1, M2, M3, M4, M5, M6

Table 8. ORP Combinations for I/O Blocks with 4 I/Os

I/O Cell Available Macrocells

I/O 0 M0, M1, M2, M3, M4, M5, M6, M7

I/O 1 M4, M5, M6, M7, M8, M9, M10, M11

I/O 2 M8, M9, M10, M11, M12, M13, M14, M15

I/O 3 M12, M13, M14, M15, M0, M1, M2, M3

Table 9. ORP Combinations for I/O Blocks with 10 I/Os

I/O Cell Available Macrocells

I/O 0 M0, M1, M2, M3, M4, M5, M6, M7

I/O 1 M2, M3, M4, M5, M6, M7, M8, M9

I/O 2 M4, M5, M6, M7, M8, M9, M10, M11

I/O 3 M6, M7, M8, M9, M10, M11, M12, M13

I/O 4 M8, M9, M10, M11, M12, M13, M14, M15

I/O 5 M10, M11, M12, M13, M14, M15, M0, M1

I/O 6 M12, M13, M14, M15, M0, M1, M2, M3

I/O 7 M14, M15, M0, M1, M2, M3, M4, M5

I/O 8 M2, M3, M4, M5, M6, M7, M8, M9

I/O 9 M10, M11, M12, M13, M14, M15, M0, M1

10

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

GOE 0

From ORP

*Global fuses

From ORP

To Macrocell

To GRP

GOE 1
GOE 2
GOE 3

VCC

V

CCO

V

CCO

**

*

Table 10. ORP Combinations for I/O Blocks with 12 I/Os

I/O Cell Available Macrocells

I/O 0 M0, M1, M2, M3, M4, M5, M6, M7

I/O 1 M1, M2, M3, M4, M5, M6, M7, M8

I/O 2 M2, M3, M4, M5, M6, M7, M8, M9

I/O 3 M4, M5, M6, M7, M8, M9, M10, M11

I/O 4 M5, M6, M7, M8, M9, M10, M11, M12

I/O 5 M6, M7, M8, M9, M10, M11, M12, M13

I/O 6 M8, M9, M10, M11, M12, M13, M14, M15

I/O 7 M9, M10, M11, M12, M13, M14, M15, M0

I/O 8 M10, M11, M12, M13, M14, M15, M0, M1

I/O 9 M12, M13, M14, M15, M0, M1, M2, M3

I/O 10 M13, M14, M15, M0, M1, M2, M3, M4

I/O 11 M14, M15, M0, M1, M2, M3, M4, M5

ORP Bypass and Fast Output Multiplexers

The ORP bypass and fast-path output multiplexer is a 4:1 multiplexer and allows the 5-PT fast path to bypass the
ORP and be connected directly to the pin with either the regular output or the inverted output. This multiplexer also
allows the register output to bypass the ORP to achieve faster t

CO

.

Output Enable Routing Multiplexers

The OE Routing Pool provides the corresponding local output enable (OE) product term to the I/O cell.

I/O Cell

The I/O cell contains the following programmable elements: output buffer, input buffer, OE multiplexer and bus
maintenance circuitry. Figure 8 details the I/O cell.

Figure 8. I/O Cell

Each output supports a variety of output standards dependent on the V
also be configured for open drain operation. Each input can be programmed to support a variety of standards, inde­pendent of the V

supplied to its I/O bank. The I/O standards supported are:

CCO

supplied to its I/O bank. Outputs can

CCO

11

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

Shared PTOE
(Block 0)

Shared PTOE
(Block n)

Global
Fuses

GOE (0:3)
to I/O cells

Internal Global OE

PT Bus

(4 lines)

4-Bit

Global OE Bus

Global OE

Fuse connection
Hard wired

• LVTTL • LVCMOS 1.8

• LVCMOS 3.3 • 3.3V PCI Compatible

• LVCMOS 2.5

All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, Pull-up Resistor or Pull-down
Resistor. A fourth option is to provide none of these. The selection is done on a global basis. The default in both
hardware and software is such that when the device is erased or if the user does not specify, the input structure is
configured to be a Pull-up Resistor.

Each ispMACH 4000 device I/O has an individually programmable output slew rate control bit. Each output can be
individually configured for fast slew or slow slew. The typical edge rate difference between fast and slow slew set­ting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reflec­tions, less noise and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the
fast slew rate can be used to achieve the highest speed.

Global OE Generation

Most ispMACH 4000 family devices have a 4-bit wide Global OE Bus, except the ispMACH 4032 device that has a
2-bit wide Global OE Bus. This bus is derived from a 4-bit internal global OE PT bus and two dual purpose I/O or
GOE pins. Each signal that drives the bus can optionally be inverted.

Each GLB has a block-level OE PT that connects to all bits of the Global OE PT bus with four fuses. Hence, for a
256-macrocell device (with 16 blocks), each line of the bus is driven from 16 OE product terms. Figures 9 and 10
show a graphical representation of the global OE generation.

Figure 9. Global OE Generation for All Devices Except ispMACH 4032

12

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

Shared PTOE
(Block 0)

Shared PTOE
(Block 1)

Global
Fuses

GOE (3:0)

to I/O cells

Internal Global OE

PT Bus

(2 lines)

4-Bit

Global OE Bus

Global OE

Fuse connection
Hard wired

Figure 10. Global OE Generation for ispMACH 4032

Zero Power/Low Power and Power Management

The ispMACH 4000 family is designed with high speed low power design techniques to offer both high speed and
low power. With an advanced E
approach), the ispMACH 4000 family offers SuperFAST pin-to-pin speeds, while simultaneously delivering low
standby power without needing any “turbo bits” or other power management schemes associated with a traditional
sense-amplifier approach.

The zero power ispMACH 4000Z is based on the 1.8V ispMACH 4000C family. With innovative circuit design
changes, the ispMACH 4000Z family is able to achieve the industry’s “lowest static power”.

2

low power cell and non sense-amplifier design approach (full CMOS logic

IEEE 1149.1-Compliant Boundary Scan Testability

All ispMACH 4000 devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows
functional testing of the circuit board on which the device is mounted through a serial scan path that can access all
critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto
test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked
into a board-level serial scan path for more board-level testing. The test access port operates with an LVCMOS
interface that corresponds to the power supply voltage.

I/O Quick Configuration

To facilitate the most efficient board test, the physical nature of the I/O cells must be set before running any continu­ity tests. As these tests are fast, by nature, the overhead and time that is required for configuration of the I/Os’
physical nature should be minimal so that board test time is minimized. The ispMACH 4000 family of devices allows
this by offering the user the ability to quickly configure the physical nature of the I/O cells. This quick configuration
takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lattice's ispVM
System programming software can either perform the quick configuration through the PC parallel port, or can gen­erate the ATE or test vectors necessary for a third-party test system.

®

13

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

IEEE 1532-Compliant In-System Programming

Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inven­tory levels, higher quality and the ability to make in-field modifications. All ispMACH 4000 devices provide In-Sys­tem Programming (ISP™) capability through the Boundary Scan Test Access Port. This capability has been
implemented in a manner that ensures that the port remains complaint to the IEEE 1149.1 standard. By using IEEE

1149.1 as the communication interface through which ISP is achieved, users get the benefit of a standard, well­defined interface. All ispMACH 4000 devices are also compliant with the IEEE 1532 standard.

The ispMACH 4000 devices can be programmed across the commercial temperature and voltage range. The PC­based Lattice software facilitates in-system programming of ispMACH 4000 devices. The software takes the
JEDEC file output produced by the design implementation software, along with information about the scan chain,
and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain
via the parallel port of a PC. Alternatively, the software can output files in formats understood by common auto­mated test equipment. This equipment can then be used to program ispMACH 4000 devices during the testing of a
circuit board.

User Electronic Signature

The User Electronic Signature (UES) allows the designer to include identification bits or serial numbers inside the
device, stored in E
user to store unique data such as ID codes, revision numbers or inventory control codes.

2

CMOS memory. The ispMACH 4000 device contains 32 UES bits that can be configured by the

Security Bit

A programmable security bit is provided on the ispMACH 4000 devices as a deterrent to unauthorized copying of
the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a
device programmer, securing proprietary designs from competitors. Programming and verification are also
defeated by the security bit. The bit can only be reset by erasing the entire device.

Hot Socketing

The ispMACH 4000 devices are well-suited for applications that require hot socketing capability. Hot socketing a
device requires that the device, during power-up and down, can tolerate active signals on the I/Os and inputs with­out being damaged. Additionally, it requires that the effects of I/O pin loading be minimal on active signals. The isp­MACH 4000 devices provide this capability for input voltages in the range 0V to 3.0V.

Density Migration

The ispMACH 4000 family has been designed to ensure that different density devices in the same package have
the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration
from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design tar­geted for a high density device to a lower density device. However, the exact details of the final resource utilization
will impact the likely success in each case.

14

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

Absolute Maximum Ratings

1, 2, 3

ispMACH 4000C/Z ispMACH 4000B ispMACH 4000V

(1.8V) (2.5V) (3.3V)

Supply Voltage (V

Output Supply Voltage (V

Input or I/O Tristate Voltage Applied

) . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V. . . . . . . . . . . -0.5 to 5.5V

CC

) . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V. . . . . . . . . . . -0.5 to 4.5V

CCO

4, 5

. . . . . . . . . -0.5 to 5.5V . . . . . . . . . .-0.5 to 5.5V. . . . . . . . . . . -0.5 to 5.5V

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . -65 to 150C. . . . . . . . . -65 to 150C . . . . . . . . . .-65 to 150C

Junction Temperature (T

1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied.

2. Compliance with Lattice Thermal Management

3. All voltages referenced to GND.

4. Undershoot of -2V and overshoot of (V

5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed.

) with Power Applied . . .-55 to 150C . . . . . . . . . -55 to 150C . . . . . . . . . .-55 to 150C

j

document is required.

(MAX) + 2V), up to a total pin voltage of 6.0V, is permitted for a duration of < 20ns.

IH

Recommended Operating Conditions

Symbol Parameter Min. Max. Units

ispMACH 4000C 1.65 1.95 V

Supply Voltage for 1.8V Devices

V

CC

Supply Voltage for 2.5V Devices 2.3 2.7 V

Supply Voltage for 3.3V Devices 3.0 3.6 V

Junction Temperature (Commercial) 0 90 C

T

j

Junction Temperature (Industrial) -40 105 C

Junction Temperature (Extended) -40 130 C

1. Devices operating at 1.6V can expect performance degradation up to 35%.

2. Applicable for devices with 2004 date codes and later. Contact factory for ordering instructions.

ispMACH 4000Z 1.7 1.9 V

ispMACH 4000Z, Extended Functional Voltage
Operation

1.6

1, 2

1.9 V

Erase Reprogram Specifications

Parameter Min. Max. Units

Erase/Reprogram Cycle 1,000 — Cycles

Note: Valid over commercial temperature range.

Hot Socketing Characteristics

Symbol Parameter Condition Min. Typ. Max. Units

I

DK

1. Insensitive to sequence of VCC or V

2. 0 < V

3. I

DK

Input or I/O Leakage Current

However, assumes monotonic rise/fall rates for VCC and V

< VCC (MAX), 0 < V

CC

is additive to IPU, IPD or IBH. Device defaults to pull-up until fuse circuitry is active.

CCO

< V

CCO.

CCO

(MAX).

1,2,3

 3.0V, Tj = 105°C — ±30 ±150 µA

0  V

IN

0  VIN  3.0V, Tj = 130°C — ±30 ±200 µA

provided (VIN - V

CCO,

CCO

)  3.6V.

15

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

I/O Recommended Operating Conditions

1

(V)

V

CCO

Standard

Min. Max.

LV TT L 3 .0 3 .6

LVCMOS 3.3 3.0 3.6

Extended LVCMOS 3.3

2

2.7 3.6

LVCMOS 2.5 2.3 2.7

LVCMOS 1.8 1.65 1.95

PCI 3.3 3.0 3.6

1. Typical values for V

2. ispMACH 4000Z only.

are the average of the min. and max. values.

CCO

DC Electrical Characteristics

Over Recommended Operating Conditions

Symbol Parameter Condition Min. Typ. Max. Units

Input Leakage Current (ispMACH

1, 4

I

, I

IL

IH

4000Z)

1

I

IH

, I

I

IL

1,2

I

IH

Input High Leakage Current (isp­MACH 4000Z)

Input Leakage Current (ispMACH

1

IH

4000V/B/C)

Input High Leakage Current (isp­MACH 4000V/B/C)

I/O Weak Pull-up Resistor Current

I

PU

(ispMACH 4000Z)

I/O Weak Pull-up Resistor Current
(ispMACH 4000V/B/C)

I

PD

I

BHLS

I

BHHS

I

BHLO

I

BHHO

V

BHT

C

1

C

2

C

3

1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not

2. 5V tolerant inputs and I/O should only be placed in banks where 3.0V

3. T

4. I

I/O Weak Pull-down Resistor Current VIL (MAX)  VIN  VIH (MIN) 30 — 150 µA

Bus Hold Low Sustaining Current VIN = VIL (MAX) 30 — — µA

Bus Hold High Sustaining Current VIN = 0.7 V

Bus Hold Low Overdrive Current 0V  VIN  V

Bus Hold High Overdrive Current V

Bus Hold Trip Points — V

I/O Capacitance

Clock Capacitance

Global Input Capacitance

measured with the output driver active. Bus maintenance circuits are disabled.

= 25°C, f = 1.0MHz

A

excursions of up to 1.5µA maximum per pin above the spec limit may be observed for certain voltage conditions on no more than 10% of

IH

the device’s I/O pins.

3

3

3

< V

0  V

IN

CCO

< VIN  5.5V — — 10 µA

V

CCO

—0.51µA

0  VIN  3.6V, Tj = 105°C — — 10 µA

0  V

 3.6V, Tj = 130°C — — 15 µA

IN

3.6V < V

3.0V  V

3.6V < V

3.0V  V

0  VIN  0.7V

0  V

BHT

V

CCO

VCC = 1.8V, VIO = 0 to VIH (MAX) — —

V

CCO

V

CC

V

CCO

V

CC

 5.5V, Tj = 105°C

IN

 3.6V

CCO

 5.5V, Tj = 130°C

IN

 3.6V

CCO

CCO

 0.7V

IN

 VIN  V

CCO

CCO

BHT

CCO

= 3.3V, 2.5V, 1.8V —

= 3.3V, 2.5V, 1.8V —

= 1.8V, VIO = 0 to VIH (MAX) — —

= 3.3V, 2.5V, 1.8V —

= 1.8V, VIO = 0 to VIH (MAX) — —

 V

 3.6V.

CCO

——20µA

——50µA

-30 — -150 µA

-30 — -200 µA

-30 — — µA

— — 150 µA

——-150µA

* 0.35 — V

CCO

CCO

8

6

6

—

—

—

* 0.65 V

pf

pf

pf

16

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

Supply Current, ispMACH 4000V/B/C

Over Recommended Operating Conditions

Symbol Parameter Condition Min. Typ. Max. Units

ispMACH 4032V/B/C

Vcc = 3.3V — 11.8 — mA

1,2,3

ICC

4

ICC

ispMACH 4064V/B/C

1,2,3

ICC

5

ICC

ispMACH 4128V/B/C

1,2,3

ICC

4

ICC

ispMACH 4256V/B/C

1,2,3

I

CC

4

I

CC

ispMACH 4384V/B/C

1,2,3

I

CC

4

I

CC

ispMACH 4512V/B/C

1,2,3

I

CC

Operating Power Supply Current

Standby Power Supply Current

Operating Power Supply Current

Standby Power Supply Current

Operating Power Supply Current

Standby Power Supply Current

Operating Power Supply Current

Standby Power Supply Current

Operating Power Supply Current

Standby Power Supply Current

Operating Power Supply Current

Vcc = 2.5V — 11.8 — mA

Vcc = 1.8V — 1.8 — mA

Vcc = 3.3V — 11.3 — mA

Vcc = 2.5V — 11.3 — mA

Vcc = 1.8V — 1.3 — mA

Vcc = 3.3V — 12 — mA

Vcc = 2.5V — 12 — mA

Vcc = 1.8V — 2 — mA

Vcc = 3.3V — 11.5 — mA

Vcc = 2.5V — 11.5 — mA

Vcc = 1.8V — 1.5 — mA

Vcc = 3.3V — 12 — mA

Vcc = 2.5V — 12 — mA

Vcc = 1.8V — 2 — mA

Vcc = 3.3V — 11.5 — mA

Vcc = 2.5V — 11.5 — mA

Vcc = 1.8V — 1.5 — mA

Vcc = 3.3V — 12.5 — mA

Vcc = 2.5V — 12.5 — mA

Vcc = 1.8V — 2.5 — mA

Vcc = 3.3V — 12 — mA

Vcc = 2.5V — 12 — mA

Vcc = 1.8V — 2 — mA

Vcc = 3.3V — 13.5 — mA

Vcc = 2.5V — 13.5 — mA

Vcc = 1.8V — 3.5 — mA

Vcc = 3.3V — 12.5 — mA

Vcc = 2.5V — 12.5 — mA

Vcc = 1.8V — 2.5 — mA

Vcc = 3.3V — 14 — mA

Vcc = 2.5V — 14 — mA

Vcc = 1.8V — 4 — mA

17

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

Supply Current, ispMACH 4000V/B/C (Cont.)

Over Recommended Operating Conditions

Symbol Parameter Condition Min. Typ. Max. Units

Vcc = 3.3V — 13 — mA

4

I

CC

1. TA = 25°C, frequency = 1.0 MHz.

2. Device configured with 16-bit counters.

3. I

varies with specific device configuration and operating frequency.

CC

4. T

= 25°C

A

Standby Power Supply Current

Vcc = 2.5V — 13 — mA

Vcc = 1.8V — 3 — mA

Supply Current, ispMACH 4000Z

Over Recommended Operating Conditions

Symbol Parameter Condition Min. Typ. Max. Units

ispMACH 4032ZC

= 25°C — 50 — µA

A

= 70°C — 58 — µA

A

= 125°C — 70 — µA

A

= 25°C — 10 — µA

A

= 85°C — 15 25 µA

A

= 125°C — 22 — µA

A

= 25°C — 80 — µA

A

= 70°C — 89 — µA

A

= 125°C — 109 — µA

A

= 25°C — 11 — µA

A

= 85°C — 18 35 µA

A

= 125°C — 37 — µA

A

= 25°C — 168 — µA

A

= 70°C — 190 — µA

A

= 125°C — 212 — µA

A

= 25°C — 12 — µA

A

= 85°C — 19 50 µA

A

= 125°C — 42 — µA

A

ICC

ICC

1, 2, 3, 5

4, 5

Operating Power Supply Current

Standby Power Supply Current

ispMACH 4064ZC

ICC

ICC

1, 2, 3, 5

4, 5

Operating Power Supply Current

Standby Power Supply Current

ispMACH 4128ZC

ICC

ICC

1, 2, 3, 5

4, 5

Operating Power Supply Current

Standby Power Supply Current

Vcc = 1.8V, T

Vcc = 1.9V, T

Vcc = 1.9V, TA = 85°C — 60 — µA

Vcc = 1.9V, T

Vcc = 1.8V, T

Vcc = 1.9V, TA = 70°C — 13 20 µA

Vcc = 1.9V, T

Vcc = 1.9V, T

Vcc = 1.8V, T

Vcc = 1.9V, T

Vcc = 1.9V, TA = 85°C — 92 — µA

Vcc = 1.9V, T

Vcc = 1.8V, T

Vcc = 1.9V, TA = 70°C — 15 25 µA

Vcc = 1.9V, T

Vcc = 1.9V, T

Vcc = 1.8V, T

Vcc = 1.9V, T

Vcc = 1.9V, TA = 85°C — 195 — µA

Vcc = 1.9V, T

Vcc = 1.8V, T

Vcc = 1.9V, TA = 70°C — 16 35 µA

Vcc = 1.9V, T

Vcc = 1.9V, T

18

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

Supply Current, ispMACH 4000Z (Cont.)

Over Recommended Operating Conditions

Symbol Parameter Condition Min. Typ. Max. Units

ispMACH 4256ZC

= 25°C — 341 — µA

A

= 70°C — 361 — µA

A

= 125°C — 468 — µA

A

= 25°C — 13 — µA

A

= 85°C — 43 90 µA

A

= 125°C — 135 — µA

A

1, 2, 3, 5

ICC

4, 5

ICC

1. TA = 25°C, frequency = 1.0 MHz.

2. Device configured with 16-bit counters.

3. I

CC

4. V

CCO

5. Includes V

Operating Power Supply Current

Standby Power Supply Current

varies with specific device configuration and operating frequency.

= 3.6V, VIN = 0V or V

current without output loading.

CCO

bus maintenance turned off. VIN above V

CCO,

Vcc = 1.8V, T

Vcc = 1.9V, T

Vcc = 1.9V, TA = 85°C — 372 — µA

Vcc = 1.9V, T

Vcc = 1.8V, T

Vcc = 1.9V, TA = 70°C — 32 55 µA

Vcc = 1.9V, T

Vcc = 1.9V, T

will add transient current above the specified standby ICC.

CCO

19

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

I/O DC Electrical Characteristics

Over Recommended Operating Conditions

V

IL

Standard

LVTTL -0.3 0.80 2.0 5.5

LVCMOS 3.3 -0.3 0.80 2.0 5.5

LVCMOS 2.5 -0.3 0.70 1.70 3.6

LVC M OS 1. 8
(4000V/B)

LVC M OS 1. 8
(4000C/Z)

-0.3 0.63 1.17 3.6

-0.3 0.35 * V

CC

0.65 * V

PCI 3.3 (4000V/B) -0.3 1.08 1.5 5.5 0.1 V

PCI 3.3 (4000C/Z) -0.3 0.3 * 3.3 * (V

1. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of
the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND
connections or between the last GND in a bank and the end of a bank.

1.8) 0.5 * 3.3 * (V

CC /

V

IH

CC

1.8) 5.5 0.1 V

CC /

3.6

V

OL

Max (V)

0.40 V

0.20 V

0.40 V

0.20 V

0.40 V

0.20 V

0.40 V

0.20 V

0.40 V

0.20 V

CCO

CCO

V

OH

Min (V)

- 0.40 8.0 -4.0

CCO

- 0.20 0.1 -0.1

CCO

- 0.40 8.0 -4.0

CCO

- 0.20 0.1 -0.1

CCO

- 0.40 8.0 -4.0

CCO

- 0.20 0.1 -0.1

CCO

- 0.45 2.0 -2.0

CCO

- 0.20 0.1 -0.1

CCO

- 0.45 2.0 -2.0

CCO

- 0.20 0.1 -0.1

CCO

0.9 V

CCO

0.9 V

CCO

I

(mA)

1.5 -0.5

1.5 -0.5

OL

1

1

I

OH

(mA)Min (V) Max (V) Min (V) Max (V)

20

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

VO Output Voltage (V)

Typical I/O Output Current (mA)

3.3V V

CCO

VO Output Voltage (V)

0

0

0

20

40

60

80

100

10

20

30

40

50

60

0

10

20

30

40

50

60

70

2.01.51.00.5

0 2.0 2.5 3.0 3.51.51.00.5

0 2.0 2.51.51.00.5

Typical I/O Output Current (mA)

1.8V V

CCO

VO Output Voltage (V)

I

OH

Typical I/O Output Current (mA)

2.5V V

CCO

I

OL

I

OH

I

OL

I

OH

I

OL

21

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C External Switching Characteristics

Over Recommended Operating Conditions

-25 -27 -3 -35

Parameter Description

t

PD

t

PD_MC

t

S

t

ST

t

SIR

t

SIRZ

t

H

t

HT

t

HIR

t

HIRZ

t

CO

t

R

t

RW

t

PTOE/DIS

t

GPTOE/DIS

t

GOE/DIS

t

CW

t

GW

t

WIR

4

f

MAX

f

(Ext.)

MAX

1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards. Timing v.3.2

2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.

3. Pulse widths and clock widths less than minimum will cause unknown behavior.

4. Standard 16-bit counter using GRP feedback.

5-PT bypass combinatorial propagation
delay

20-PT combinatorial propagation delay
through macrocell

GLB register setup time before clock 1.8 — 1.8 — 2.0 — 2.0 — ns

GLB register setup time before clock
with T-type register

GLB register setup time before clock,
input register path

GLB register setup time before clock
with zero hold

GLB register hold time after clock 0.0 — 0.0 — 0.0 — 0.0 — ns

GLB register hold time after clock with
T-type register

GLB register hold time after clock, input
register path

GLB register hold time after clock, input
register path with zero hold

GLB register clock-to-output delay — 2.2 — 2.7 — 2.7 — 2.7 ns

External reset pin to output delay — 3.5 — 4.0 — 4.4 — 4.5 ns

External reset pulse duration 1.5 — 1.5 — 1.5 — 1.5 - ns

Input to output local product term output
enable/disable

Input to output global product term
output enable/disable

Global OE input to output enable/disable — 3.0 — 3.5 — 4.0 — 4.5 ns

Global clock width, high or low 1.1 — 1.3 — 1.3 — 1.3 — ns

Global gate width low (for low
transparent) or high (for high transparent)

Input register clock width, high or low 1.1 — 1.3 — 1.3 — 1.3 — ns

Clock frequency with internal feedback — 400 — 333 — 322 — 322 MHz

Clock frequency with external feedback,

+ tCO)]

[1/ (t

S

1, 2, 3

—2.5—2.7—3.0—3.5ns

—3.2—3.5—3.8—4.2ns

2.0 — 2.0 — 2.2 — 2.2 — ns

0.7 — 1.0 — 1.0 — 1.0 — ns

1.7 — 2.0 — 2.0 — 2.0 — ns

0.0 — 0.0 — 0.0 — 0.0 — ns

0.9 — 1.0 — 1.0 — 1.0 — ns

0.0 — 0.0 — 0.0 — 0.0 — ns

—4.0—4.5—5.0—5.5ns

—5.0—6.5—8.0—8.0ns

1.1 — 1.3 — 1.3 — 1.3 — ns

— 250 — 222 — 212 — 212 MHz

UnitsMin. Max. Min. Max. Min. Max. Min. Max.

22

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C External Switching Characteristics (Cont.)

Over Recommended Operating Conditions

-5 -75 -10

Parameter Description

t

PD

t

PD_MC

t

S

t

ST

t

SIR

t

SIRZ

t

H

t

HT

t

HIR

t

HIRZ

t

CO

t

R

t

RW

t

PTOE/DIS

t

GPTOE/DIS

t

GOE/DIS

t

CW

t

GW

t

WIR

4

f

MAX

f

(Ext.) Clock frequency with external feedback, [1/ (tS + tCO)] —156—111— 86MHz

MAX

1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards. Timing v.3.2

2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.

3. Pulse widths and clock widths less than minimum will cause unknown behavior.

4. Standard 16-bit counter using GRP feedback.

5-PT bypass combinatorial propagation delay — 5.0 — 7.5 — 10.0 ns

20-PT combinatorial propagation delay through macrocell — 5.5 — 8.0 — 10.5 ns

GLB register setup time before clock 3.0 — 4.5 — 5.5 — ns

GLB register setup time before clock with T-type register 3.2 — 4.7 — 5.5 — ns

GLB register setup time before clock, input register path 1.2 — 1.7 — 1.7 — ns

GLB register setup time before clock with zero hold 2.2 — 2.7 — 2.7 — ns

GLB register hold time after clock 0.0 — 0.0 — 0.0 — ns

GLB register hold time after clock with T-type register 0.0 — 0.0 — 0.0 — ns

GLB register hold time after clock, input register path 1.0 — 1.0 — 1.0 — ns

GLB register hold time after clock, input register path with
zero hold

GLB register clock-to-output delay — 3.4 — 4.5 — 6.0 ns

External reset pin to output delay — 6.3 — 9.0 — 10.5 ns

External reset pulse duration 2.0 — 4.0 — 4.0 — ns

Input to output local product term output enable/disable — 7.0 — 9.0 — 10.5 ns

Input to output global product term output enable/disable — 9.0 — 10.3 — 12.0 ns

Global OE input to output enable/disable — 5.0 — 7.0 — 8.0 ns

Global clock width, high or low 2.2 — 2.8 — 4.0 — ns

Global gate width low (for low transparent) or high (for
high transparent)

Input register clock width, high or low 2.2 — 2.8 — 4.0 ns

Clock frequency with internal feedback — 227 — 168 — 125 MHz

1, 2, 3

0.0 — 0.0 — 0.0 — ns

2.2 — 2.8 — 4.0 — ns

UnitsMin. Max. Min. Max. Min. Max.

23

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z External Switching Characteristics

Over Recommended Operating Conditions

-35 -37 -42

Parameter Description

t

PD

t

PD_MC

t

S

t

ST

t

SIR

t

SIRZ

t

H

t

HT

t

HIR

t

HIRZ

t

CO

t

R

t

RW

t

PTOE/DIS

t

GPTOE/DIS

t

GOE/DIS

t

CW

t

GW

t

WIR

4

f

MAX

(Ext.)

f

MAX

1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards. Timing v.2.2

2. Measured using standard switching GRP loading of 1 and 1 output switching.

3. Pulse widths and clock widths less than minimum will cause unknown behavior.

4. Standard 16-bit counter using GRP feedback.

5-PT bypass combinatorial propagation delay — 3.5 — 3.7 — 4.2 ns

20-PT combinatorial propagation delay
through macrocell

GLB register setup time before clock 2.2 — 2.5 — 2.7 — ns

GLB register setup time before clock with
T-type register

GLB register setup time before clock, input
register path

GLB register setup time before clock with zero
hold

GLB register hold time after clock 0.0 — 0.0 — 0.0 — ns

GLB register hold time after clock with T-type
register

GLB register hold time after clock, input
register path

GLB register hold time after clock, input
register path with zero hold

GLB register clock-to-output delay — 3.0 — 3.2 — 3.5 ns

External reset pin to output delay — 5.0 — 6.0 — 7.3 ns

External reset pulse duration 1.5 — 1.7 — 2.0 — ns

Input to output local product term output
enable/disable

Input to output global product term output
enable/disable

Global OE input to output enable/disable — 4.5 — 4.5 — 4.8 ns

Global clock width, high or low 1.0 — 1.5 — 1.8 — ns

Global gate width low (for low transparent) or
high (for high transparent)

Input register clock width, high or low 1.0 — 1.5 — 1.8 — ns

Clock frequency with internal feedback — 267 — 250 — 220 MHz

clock frequency with external feedback,
[1 / (tS + tCO)]

1, 2, 3

—4.4—4.7—5.7 ns

2.4 — 2.7 — 2.9 — ns

1.0 — 1.1 — 1.3 — ns

2.0 — 2.1 — 2.6 — ns

0.0 — 0.0 — 0.0 — ns

1.0 — 1.0 — 1.3 — ns

0.0 — 0.0 — 0.0 — ns

—7.0—8.0—8.0 ns

—6.5—7.0—8.0 ns

1.0 — 1.5 — 1.8 — ns

—192—175—161MHz

UnitsMin. Max. Min. Max. Min. Max.

24

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z External Switching Characteristics (Cont.)

Over Recommended Operating Conditions

-45 -5 -75

Parameter Description

t

PD

t

PD_MC

t

S

t

ST

t

SIR

t

SIRZ

t

H

t

HT

t

HIR

t

HIRZ

t

CO

t

R

t

RW

t

PTOE/DIS

t

GPTOE/DIS

t

GOE/DIS

t

CW

t

GW

t

WIR

4

f

MAX

(Ext.)

f

MAX

1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards. Timing v.2.2

2. Measured using standard switching GRP loading of 1 and 1 output switching.

3. Pulse widths and clock widths less than minimum will cause unknown behavior.

4. Standard 16-bit counter using GRP feedback.

5-PT bypass combinatorial propagation delay — 4.5 — 5.0 — 7.5 ns

20-PT combinatorial propagation delay
through macrocell

GLB register setup time before clock 2.9 — 3.0 — 4.5 — ns

GLB register setup time before clock with T­type register

GLB register setup time before clock, input
register path

GLB register setup time before clock with zero
hold

GLB register hold time after clock 0.0 — 0.0 — 0.0 — ns

GLB register hold time after clock with T-type
register

GLB register hold time after clock, input regis­ter path

GLB register hold time after clock, input regis­ter path with zero hold

GLB register clock-to-output delay — 3.8 — 4.2 — 4.5 ns

External reset pin to output delay — 7.5 — 7.5 — 9.0 ns

External reset pulse duration 2.0 — 2.0 — 4.0 — ns

Input to output local product term output
enable/disable

Input to output global product term output
enable/disable

Global OE input to output enable/disable — 5.5 — 6.0 — 7.0 ns

Global clock width, high or low 1.8 — 2.0 — 2.8 — ns

Global gate width low (for low transparent) or
high (for high transparent)

Input register clock width, high or low 1.8 — 2.0 — 2.8 — ns

Clock frequency with internal feedback — 200 — 200 — 168 MHz

clock frequency with external feedback, [1 /
(tS + tCO)]

1, 2, 3

—5.8—6.0—8.0 ns

3.1 — 3.2 — 4.7 — ns

1.3 — 1.3 — 1.4 — ns

2.6 — 2.6 — 2.7 — ns

0.0 — 0.0 — 0.0 — ns

1.3 — 1.3 — 1.3 — ns

0.0 — 0.0 — 0.0 — ns

—8.2—8.5—9.0 ns

— 10.0 — 10.0 — 10.5 ns

1.8 — 2.0 — 2.8 — ns

—150—139—111MHz

UnitsMin. Max. Min. Max. Min. Max.

25

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

DATA

MC Reg.

C.E.

S/R

Q

SCLK

IN

OE

In/Out

Delays

In/Out

Delays

Control

Delays

Register/Latch

Delays

Routing/GLB Delays

Out

Note: Italicized items are optional delay adders.

t

FBK

Feedback

From

Feedback

t

BUF

t

PDb

t

MCELL

t

PTCLK

t

BCLK

t

PTSR

t

BSR

t

GPTOE

t

PTOE

t

EXP

t

ROUTE

t

BLA

t

INREG

t

INDIO

t

IN

t

IOI

t

GCLK_IN

t

IOI

t

GOE

t

IOI

t

PDi

t

IOO

t

ORP

t

EN

t

DIS

Timing Model

The task of determining the timing through the ispMACH 4000 family, like any CPLD, is relatively simple. The timing
model provided in Figure 11 shows the specific delay paths. Once the implementation of a given function is deter­mined either conceptually or from the software report file, the delay path of the function can easily be determined
from the timing model. The Lattice design tools report the timing delays based on the same timing model for a par­ticular design. Note that the internal timing parameters are given for reference only, and are not tested. The exter­nal timing parameters are tested and guaranteed for every device. For more information on the timing model and
usage, refer to TN1004, ispMACH 4000 Timing Model Design and Usage Guidelines

Figure 11. ispMACH 4000 Timing Model

.

26

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C Internal Timing Parameters

Over Recommended Operating Conditions

Parameter Description -2.5 -2.7 -3 -3.5 Units

In/Out Delays

t

IN

t

GOE

t

GCLK_IN

t

BUF

t

EN

t

DIS

Routing/GLB Delays

t

ROUTE

t

MCELL

t

INREG

t

FBK

t

PDb

t

PDi

Register/Latch Delays

t

S

t

S_PT

t

ST

t

ST_PT

t

H

t

HT

t

SIR

t

SIR_PT

t

HIR

t

HIR_PT

t

COi

t

CES

t

CEH

t

SL

t

SL_PT

t

HL

t

GOi

Input Buffer Delay — 0.60 — 0.60 — 0.70 — 0.70 ns

Global OE Pin Delay — 2.04 — 2.54 — 3.04 — 3.54 ns

Global Clock Input Buffer Delay — 0.78 — 1.28 — 1.28 — 1.28 ns

Delay through Output Buffer — 0.85 — 0.85 — 0.85 — 0.85 ns

Output Enable Time — 0.96 — 0.96 — 0.96 — 0.96 ns

Output Disable Time — 0.96 — 0.96 — 0.96 — 0.96 ns

Delay through GRP — 0.61 — 0.81 — 1.01 — 1.01 ns

Macrocell Delay — 0.45 — 0.55 — 0.55 — 0.65 ns

Input Buffer to Macrocell Register
Delay

— 0.11 — 0.31 — 0.31 — 0.31 ns

Internal Feedback Delay — 0.00 — 0.00 — 0.00 — 0.00 ns

5-PT Bypass Propagation Delay — 0.44 — 0.44 — 0.44 — 0.94 ns

Macrocell Propagation Delay — 0.64 — 0.64 — 0.64 — 0.94 ns

D-Register Setup Time
(Global Clock)

D-Register Setup Time
(Product Term Clock)

T-Register Setup Time
(Global Clock)

T-Register Setup Time
(Product Term Clock)

0.92 — 1.12 — 1.02 — 0.92 — ns

1.42 — 1.32 — 1.32 — 1.32 — ns

1.12 — 1.32 — 1.22 — 1.12 — ns

1.42 — 1.32 — 1.32 — 1.32 — ns

D-Register Hold Time 0.88 — 0.68 — 0.98 — 1.08 — ns

T-Register Hold Time 0.88 — 0.68 — 0.98 — 1.08 — ns

D-Input Register Setup Time
(Global Clock)

D-Input Register Setup Time
(Product Term Clock)

D-Input Register Hold Time
(Global Clock)

D-Input Register Hold Time
(Product Term Clock)

Register Clock to Output/Feedback
MUX Time

0.82 — 1.37 — 1.27 — 1.27 — ns

1.45 — 1.45 — 1.45 — 1.45 — ns

0.88 — 0.63 — 0.73 — 0.73 — ns

0.88 — 0.63 — 0.73 — 0.73 — ns

— 0.52 — 0.52 — 0.52 — 0.52 ns

Clock Enable Setup Time 2.25 — 2.25 — 2.25 — 2.25 — ns

Clock Enable Hold Time 1.88 — 1.88 — 1.88 — 1.88 — ns

Latch Setup Time
(Global Clock)

Latch Setup Time (Product Term
Clock)

0.92 — 1.12 — 1.02 — 0.92 — ns

1.42 — 1.32 — 1.32 — 1.32 — ns

Latch Hold Time 1.17 — 1.17 — 1.17 — 1.17 — ns

Latch Gate to Output/Feedback
MUX Time

— 0.33 — 0.33 — 0.33 — 0.33 ns

27

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C Internal Timing Parameters (Cont.)

Over Recommended Operating Conditions

Parameter Description -2.5 -2.7 -3 -3.5 Units

Propagation Delay through

t

PDLi

t

SRi

t

SRR

Transparent Latch to Output/
Feedback MUX

Asynchronous Reset or Set to
Output/Feedback MUX Delay

Asynchronous Reset or Set
Recovery Time

Control Delays

t

BCLK

t

PTCLK

t

BSR

t

PTSR

t

GPTOE

t

PTOE

Note: Internal Timing Parameters are not tested and are for reference only. Refer to the Timing Model in this data sheet for further details.

GLB PT Clock Delay — 1.12 — 1.12 — 1.12 — 1.12 ns

Macrocell PT Clock Delay — 0.87 — 0.87 — 0.87 — 0.87 ns

Block PT Set/Reset Delay — 1.83 — 1.83 — 1.83 — 1.83 ns

Macrocell PT Set/Reset Delay — 1.11 — 1.41 — 1.51 — 1.61 ns

Global PT OE Delay — 2.83 — 4.13 — 5.33 — 5.33 ns

Macrocell PT OE Delay — 1.83 — 2.13 — 2.33 — 2.83 ns

— 0.25 — 0.25 — 0.25 — 0.25 ns

0.28 — 0.28 — 0.28 — 0.28 — ns

1.67 — 1.67 — 1.67 — 1.67 — ns

Timing v.3.2

28

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C Internal Timing Parameters

Over Recommended Operating Conditions

-5 -75 -10

Parameter Description

In/Out Delays

t

IN

t

GOE

t

GCLK_IN

t

BUF

t

EN

t

DIS

Input Buffer Delay — 0.95 — 1.50 — 2.00 ns

Global OE Pin Delay — 4.04 — 6.04 — 7.04 ns

Global Clock Input Buffer Delay — 1.83 — 2.28 — 3.28 ns

Delay through Output Buffer — 1.00 — 1.50 — 1.50 ns

Output Enable Time — 0.96 — 0.96 — 0.96 ns

Output Disable Time — 0.96 — 0.96 — 0.96 ns

Routing/GLB Delays

t

ROUTE

t

MCELL

t

INREG

t

FBK

t

PDb

t

PDi

Delay through GRP — 1.51 — 2.26 — 3.26 ns

Macrocell Delay — 1.05 — 1.45 — 1.95 ns

Input Buffer to Macrocell Register Delay — 0.56 — 0.96 — 1.46 ns

Internal Feedback Delay — 0.00 — 0.00 — 0.00 ns

5-PT Bypass Propagation Delay — 1.54 — 2.24 — 3.24 ns

Macrocell Propagation Delay — 0.94 — 1.24 — 1.74 ns

Register/Latch Delays

t

S

t

S_PT

t

ST

t

ST_PT

t

H

t

HT

t

SIR

t

SIR_PT

t

HIR

t

HIR_PT

t

COi

t

CES

t

CEH

t

SL

t

SL_PT

t

HL

t

GOi

t

PDLi

t

SRi

t

SRR

D-Register Setup Time (Global Clock) 1.32 — 1.57 — 1.57 — ns

D-Register Setup Time (Product Term Clock) 1.32 — 1.32 — 1.32 — ns

T-Register Setup Time (Global Clock) 1.52 — 1.77 — 1.77 — ns

T-Register Setup Time (Product Term Clock) 1.32 — 1.32 — 1.32 — ns

D-Register Hold Time 1.68 — 2.93 — 3.93 — ns

T-Register Hold Time 1.68 — 2.93 — 3.93 — ns

D-Input Register Setup Time (Global Clock) 1.52 — 1.57 — 1.57 — ns

D-Input Register Setup Time (Product Term Clock) 1.45 — 1.45 — 1.45 — ns

D-Input Register Hold Time (Global Clock) 0.68 — 1.18 — 1.18 — ns

D-Input Register Hold Time (Product Term Clock) 0.68 — 1.18 — 1.18 — ns

Register Clock to Output/Feedback MUX Time — 0.52 — 0.67 — 1.17 ns

Clock Enable Setup Time 2.25 — 2.25 — 2.25 — ns

Clock Enable Hold Time 1.88 — 1.88 — 1.88 — ns

Latch Setup Time (Global Clock) 1.32 — 1.57 — 1.57 — ns

Latch Setup Time (Product Term Clock) 1.32 — 1.32 — 1.32 — ns

Latch Hold Time 1.17 — 1.17 — 1.17 — ns

Latch Gate to Output/Feedback MUX Time — 0.33 — 0.33 — 0.33 ns

Propagation Delay through Transparent Latch to Output/
Feedback MUX

Asynchronous Reset or Set to Output/Feedback MUX
Delay

Asynchronous Reset or Set Recovery Time 1.67 — 1.67 — 1.67 — ns

Control Delays

t

BCLK

t

PTCLK

t

BSR

t

PTSR

GLB PT Clock Delay — 1.12 — 1.12 — 0.62 ns

Macrocell PT Clock Delay — 0.87 — 0.87 — 0.87 ns

GLB PT Set/Reset Delay — 1.83 — 1.83 — 1.83 ns

Macrocell PT Set/Reset Delay — 2.51 — 3.41 — 3.41 ns

— 0.25 — 0.25 — 0.25 ns

0.28 — 0.28 — 0.28 — ns

UnitsMin. Max. Min. Max. Min. Max.

29

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C Internal Timing Parameters (Cont.)

Over Recommended Operating Conditions

-5 -75 -10

Parameter Description

t

GPTOE

t

PTOE

Note: Internal Timing Parameters are not tested and are for reference only. Refer to the Timing Model in this data sheet for further details.

Global PT OE Delay — 5.58 — 5.58 — 5.78 ns

Macrocell PT OE Delay — 3.58 — 4.28 — 4.28 ns

UnitsMin. Max. Min. Max. Min. Max.

Timing v.3.2

30