Lattice LatticeMico8 User Manual
LatticeMico8 Microcontroller
User’s Guide
May 2006 Reference Design RD1026
Introduction
The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with
32 General Purpose registers, the LatticeMico8 is a flexible Verilog reference design suitable for a wide variety of
markets, including communications, consumer, computer, medical, industrial, and automotive. The core consumes
minimal device resources, less than 200 Look Up Tables (LUTs) in the smallest configuration, while maintaining a
broad feature set.
Features
• 8-bit Data Path
• 18-bit Wide Instructions
• 32 General Purpose Registers
• 32 bytes of Internal Scratch Pad Memory
• Input/Output is Performed Using “Ports” (Up to 256 Port Numbers)
• Optional 256 bytes of External Scratch Pad RAM
• Two Cycles Per Instruction
• Lattice UART Reference Design Peripheral
Functional Description
The following figure shows a block diagram of LatticeMico8 microcontroller.
Figure 1. LatticeMico8 Microcontroller Block Diagram
16 Deep Call Stack
Program Flow Control and PC
Interrupt
value
op A
op B
Immediate
value
Program
Memory
(EBR)
instr
17:0
rd
rb
From Mem
Register File
32 8-bit
Registers
Internal
32-byte Scratch
Pad Memory
Interrupt Ack
Flags
CY, Z
ALU
Optional External
Scratch Pad
(up to 256 Bytes)
From I/O Port
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ALU Op
To I/O Port
rd1026_01.2
LatticeMico8 Microcontroller
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Register File
The register file is implemented using dual ported distributed RAM. It contains 32 8-bit entries. Two values can be
simultaneously read from the register file.
Scratch Pad RAM (Internal)
The internal scratch pad memory has 32 entries. It can be addressed directly or indirectly (via a register). Indirect
addressing mode is not available if external scratch pad memory is attached.
Optional External Scratch Pad
The external scratch pad provides an additional 256 bytes of memory. It can be implemented using either distributed RAM or using an EBR. The external scratch pad memory can be addressed via indirect addressing only.
Hardware (Circular) Call Stack
When a call instruction is executed, the address of the next instruction is pushed into the call stack, a ret
(return) instruction will pop the stack and continue execution from the location at the top of the stack.
An interrupt also causes the address of the instruction that would have executed next to be pushed into the call
stack. The reti (return from interrupt) instruction will pop the stack and continue from the location at the top of the
stack.
The stack is implemented as a circular buffer and any program execution will continue from an undefined location in
case of a stack overflow or underflow.
Interrupt Handling
The microcontroller has one interrupt source, which is level sensitive. The interrupt can be enabled or disabled by
software ( cli = clear interrupt, sti = set interrupt). When an interrupt is received, the address of the next instruction is pushed into the call stack and the microcontroller continues execution from the interrupt vector (address 0).
The flags (carry and zero) are copied to shadow locations. The interrupt ack line is set high and the acknowledge line is held high for the entire duration of interrupt handling. Once the interrupt has been acknowledged the
interrupt line should be set to 0.
A reti instruction will pop the call stack and transfer control to the address on top of the stack. The Flags (carry
and zero) are restored from the shadow locations. The interrupt acknowledge line is set to low.
The microcontroller cannot handle nested interrupts.
Input/Output
Input and output are done via “ports”. Up to 256 port numbers are allowed. The lower 32 ports can be addressed
directly (using the import and export instructions), or indirectly (using the importi and exporti instructions).
The upper 224 ports can be accessed by indirect addressing only (by the importi and exporti instructions).
The port number (0-31 of import , export and 0-255 for importi and exporti instructions) is presented at the
external interface for two cycles.
For import and importi instructions, the ext_io_rd signal is strobed in the same cycle as the input values are
sampled. The address signal is ext_addr and the input signals are ext_io_din . Both the address and the I/O
read strobe are driven in the second cycle. In the case of the importi instruction, the ext_addr signal is driven
from the register file; otherwise, for the import instruction, it is driven directly from the instruction. Figure 2 shows
the waveform corresponding to a read.
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Figure 2. Microcontroller Read Cycle Using import , importi
For export and exporti instructions, the ext_io_wr signal is strobed in the same cycle as the data out is
driven. Both the ext_io_wr and the ext_dout are driven in the second cycle of instruction execution. Figure 3
shows the waveform corresponding to a write. In the case of the exporti instruction, the ext_addr signal is
driven from the register file; otherwise, for the export instruction, it is driven directly from the instruction.
Figure 3. Microcontroller Write Cycle Using export , exporti
Scratch Pad Memory Access (External)
An optional scratch pad memory of up to 256 bytes can be attached externally to the processor. If external memory
is attached, the internal scratch pad can be accessed by direct addressing only ( LSP and SSP instructions). The
external memory can be accessed by indirect addressing only ( LSPI and SSPI instructions).
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Instruction Sets
Please note that for all Branch and Call instructions, the signed offset is represented as binary 2’s complement.
ADD RD, Rb
17 16 15 14 13 12 11 10 9 8 76543210
0 1 0 0 Rd Rd Rd Rd Rd Rb Rb Rb Rb Rb 0 0 0
0
CY Flag Updated Zero Flag Updated
Ye s
Rd = Rd + Rb (add registers)
The carry flag is updated with the carry out from the addition. The zero flag is set to 1 if all the bits of the result are
0.
ADDI Rd, C
Ye s
17 16 15 14 13 12 11 10 9 8 76543210
0 1 0 1 Rd Rd Rd Rd Rd C C C C C C C C
0
CY Flag Updated Zero Flag Updated
Ye s
Ye s
Rd = Rd + CCCCCCCC (add constant to register)
The carry flag is updated with the carry out from the addition. The zero flag is set to 1 if all the bits of the result are
0.
ADDC Rd, Rb
17 16 15 14 13 12 11 10 9 8 76543210
0
0 1 1 0 Rd Rd Rd Rd Rd Rb Rb Rb Rb Rb 0 0 0
CY Flag Updated Zero Flag Updated
Ye s
Ye s
Rd = Rd + Rb + Carry Flag (add registers and carry flag)
The carry flag is updated with the carry out from the addition. The zero flag is set to 1 if all the bits of the result are
0.
ADDIC Rd, CC
17 16 15 14 13 12 11 10 9 8 76543210
0
0 1 1 1 Rd Rd Rd Rd Rd C C C C C C C C
CY Flag Updated Zero Flag Updated
Ye s
Ye s
Rd = Rd + CCCCCCCC + Carry Flag (add register, constant and carry flag)
The carry flag is updated with the carry out from the addition. The zero flag is set to 1 if all the bits of the result are
0.
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SUB Rd, Rb
17 16 15 14 13 12 11 10 9 8 76543210
00000RdRdRdRdRdRbRbRbRbRb000
CY Flag Updated Zero Flag Updated
Ye s Ye s
Rd = Rd - Rb (subtract register from register)
The carry flag is set to 1 if the result is negative. The zero flag is set to 1 if all the bits of the result are 0.
SUBI Rd, C
17 16 15 14 13 12 11 10 9 8 76543210
0
0 0 0 1 Rd Rd Rd Rd Rd C C C C C C C C
CY Flag Updated Zero Flag Updated
Ye s
Ye s
Rd = Rd - CCCCCCCC (subtract constant from register)
The carry flag is set to 1 if the result is negative. The zero flag is set to 1 if all the bits of the result are 0.
SUBC Rd, Rb
17 16 15 14 13 12 11 10 9 8 76543210
0
0 0 1 0 Rd Rd Rd Rd Rd Rb Rb Rb Rb Rb 0 0 0
CY Flag Updated Zero Flag Updated
Ye s
Ye s
Rd = Rd - Rb - Carry Flag (subtract register with carry from register)
The carry flag is set to 1 if the result is negative. The zero flag is set to 1 if all the bits of the result are 0.
SUBIC Rd, C
17 16 15 14 13 12 11 10 9 8 76543210
0 0 0 1 1 Rd Rd Rd Rd Rd C C C C C C C C
CY Flag Updated Zero Flag Updated
Ye s Ye s
Rd = Rd - CCCCCCCC - Carry Flag (subtract constant with carry from register)
The carry flag is set to 1 if the result is negative. The zero flag is set to 1 if all the bits of the result are 0.
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MOV Rd, Rb
17 16 15 14 13 12 11 10 9 8 76543210
0 1 0 0 0 Rd Rd Rd Rd Rd Rb Rb Rb Rb Rb 0 0 0
CY Flag Updated Zero Flag Updated
No Ye s
Rd = Rb (move register to register)
The zero flag is set to 1 if all the bits of the result are 0.
MOVI Rd, C
17 16 15 14 13 12 11 10 9 8 76543210
01001RdRdRdRdRdCCCCCCCC
CY Flag Updated Zero Flag Updated
No Yes
Rd = CCCCCCCC (move constant into register)
The zero flag is set to 1 if all the bits of the result are 0.
AND Rd, Rb
17 16 15 14 13 12 11 10 9 8 76543210
0 1 0 1 0 Rd Rd Rd Rd Rd Rb Rb Rb Rb Rb 0 0 0
CY Flag Updated Zero Flag Updated
No Ye s
Rd = Rd and Rb (bitwise AND registers)
The zero flag is set to 1 if all the bits of the result are 0.
ANDI Rd, C
17 16 15 14 13 12 11 10 9 8 76543210
0 1 0 1 1 Rd Rd Rd Rd Rd C C C C C C C C
CY Flag Updated Zero Flag Updated
No Ye s
Rd = Rd and CCCCCCCC (bitwise AND register with constant)
The zero flag is set to 1 if all the bits of the result are 0.
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OR Rd, Rb
17 16 15 14 13 12 11 10 9 8 76543210
0 1 1 0 0 Rd Rd Rd Rd Rd Rb Rb Rb Rb Rb 0 0 0
CY Flag Updated Zero Flag Updated
No Ye s
Rd = Rd | Rb (bitwise OR registers)
The zero flag is set to 1 if all the bits of the result are 0.
ORI Rd, C
17 16 15 14 13 12 11 10 9 8 76543210
0 1 1 0 1 Rd Rd Rd Rd Rd C C C C C C C C
CY Flag Updated Zero Flag Updated
No Ye s
Rd = Rd | CCCCCCCC (bitwise OR register with constant)
The zero flag is set to 1 if all the bits of the result are 0.
XOR Rd, Rb
17 16 15 14 13 12 11 10 9 8 76543210
0 1 1 1 0 Rd Rd Rd Rd Rd Rb Rb Rb Rb Rb 0 0 0
CY Flag Updated Zero Flag Updated
No Ye s
Rd = Rd and Rb (bitwise XOR registers)
The zero flag is set to 1 if all the bits of the result are 0.
XORI Rd, CC
17 16 15 14 13 12 11 10 9 8 76543210
0 1 1 1 1 Rd Rd Rd Rd Rd C C C C C C C C
CY Flag Updated Zero Flag Updated
No Ye s
Rd = Rd and CC (bitwise XOR register with constant)
The zero flag is set to 1 if all the bits of the result are 0.
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