Lattice LatticeECP2 User Manual
LatticeECP2™ Standard Evaluation Board
User’s Guide
Revision: ebdug18_01.3
May 2007
LatticeECP2 Standard Evaluation Board
Lattice Semiconductor User’s Guide
Introduction
The LatticeECP2 Standard Evaluation Board is a complete, integrated design, featuring a LatticeECP2 FPGA and
a variety of both application-specific and general-purpose peripheral interfaces. This board provides a convenient
platform to evaluate, test, and debug user designs, including designs requiring PCI/PCI-X. This board includes the
following features:
• LatticeECP2 FPGA device in 484 fpBGA package
• SPI Serial Flash device included for low-cost, non-volatile configuration storage
• PCI/PCI-X edge connector (188-pin) supporting Master or Target
– PCI 2.2 - 32/64 bit, 33/66 MHz, 3.3V
– PCI-X - 32/64 bit, 66/133 MHz, parity or ECC, 3.3V (Mode 1)
• RS-232 connector
• 33.33 MHz oscillator
• RJ-45 connector
• LCD connector
• Compact Flash connector
• Prototyping area with access to over 210 I/O pins
• Optional SMA/SMB connectors (up to eight) for high-speed clock and data interfacing
• 7-segment display, eight general purpose switches, two momentary switches, eight user LEDs, and various sta-
tus LEDs
• Required voltages supplied by PCI/PCI-X or one external 5V DC supply
• ispVM
Figure 1. Lattice ECP2 Standard Evaluation Board
®
System programming support
Electrical, Mechanical, and Environmental Specifications
The nominal board dimensions are 9.75 inches by 4.2 inches. The environmental specifications are as follows:
• Operating temperature: 0ºC to 55ºC
• Storage temperature: -40ºC to 75ºC
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Lattice Semiconductor User’s Guide
• Humidity: < 95% without condensation
• 5VDC input (+/- 10%) up to 4A, or 3.3V input from PCI/PCI-X backplane
Additional Resources
Additional resources relating to the LatticeECP2 Standard Evaluation Board (including updated documentation,
and sample programs) can be found at the following URL:
www.latticesemi.com/products/developmenthardware/fpgafspcboards/ecp2stardevaluationboard.cfm
Features
LatticeECP2 Device
This board features a LatticeECP2 FPGA with a 1.2V DC core in a 484-ball fpBGA package. A complete description of this device can be found in the LatticeECP2 Family Data Sheet available on the Lattice web site at www.latticesemi.com/ecp2.
On-Board Oscillator
The 3.3V oscillator socket at Y1 accepts both full-size (14-pin) and half-size (8-pin) oscillators, and will route the
oscillator output to a LatticeECP2 primary clock input or a PLL input, depending on the oscillator’s position in the
socket (see Figure 2).
When a full size oscillator is installed such that pin 1 of the oscillator aligns with pin 1 of the socket, the output of
the oscillator drives the primary clock at LatticeECP2 pin J21 (this is the default position). When pin 1 of the oscillator is aligned to pin 2 of the socket, the clock is routed to LatticeECP2 pin J21. When using a half size oscillator,
align pin 1 of the oscillator to pin 1 of the socket to drive the primary clock, or align pin 1 of the oscillator to pin 5 of
the socket to drive the PLL. Note that pin 1 of the oscillator is expected to be a no-connect pin.
Figure 2. Oscillator Options
GND
GND
Pin-1 Pin-1
Default
Position
Pin-1
33.33 MHz
Full-Size
33.33 MHz
Full-Size
Pin-16 Pin-16
3.3V
Primary Clock
(J21)
PLL Clock
(N21)
3.3V
Primary Clock
(J21)
PLL Clock
(N21)
GND
Pin-1Pin-16
GND
33.33 MHz
Half-Size
33.33 MHz
Half-Size
Pin-16
3.3V
Primary Cloc
(J21)
PLL Clock
(N21)
3.3V
Primary Cloc
(J21)
PLL Clock
(N21)
SPI Serial Flash
SPI Serial Flash are available in three package styles, two of those packages, 8-pin SO and 16-pin SO, are supported by this board. In general, the 8-pin devices support densities up to 16Mb, while the 16-pin devices support
larger densities. The device chosen for inclusion on this board depends on the density of the installed LatticeECP2,
but the SPI Serial Flash will be large enough to allow two bitstreams to be stored simultaneously in order to support
SPIm mode.
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The 8-pin device footprint is at U4; the 16-pin device footprint is at U5. Only one location can be populated at a
time.
Configuration/Programming Headers
Two programming headers are provided on the evaluation board, providing access to the LatticeECP2 JTAG port
and sysCONFIG™ port. The JTAG connector is a 1x10 header and the sysCONFIG connector is a 2x17 header.
Both the JTAG and the sysCONFIG ports are also provided with loop-through connectors to allow for easy daisy
chaining of multiple boards. With proper jumper selection (see the next section) standard IDC ribbon cable can be
used without the need to swap wires on the cable.
See the Configuring/Programming The Board section of this document for more information on this topic.
The pinouts for these headers are provided in the following tables.
Note: A parallel port ispDOWNLOAD
using a parallel port (1x8) ispDOWNLOAD cable, connect pin 1 of the cable to pin 1 of the 1x10 JTAG header. For
more information on the ispDOWNLOAD Cable, see the ispDOWNLOAD Cables Data Sheet available on the Lattice web site at www.latticesemi.com.
®
cable is included with each LatticeECP2 Standard Evaluation Board. When
Table 1. JTAG Programming Header Pinout
Function
Vcc (3.3V)
1
TDO
TDI 3
PROGN
1
N/C 5
TMS 6
Ground 7
1
TCK
DONE 9
INIT Chain
1. See section below on jumpers.
Table 2. JTAG Loop-Through Header Pinout
Function
N/C
TDO Chain
TDI Chain
PROGN
N/C 5
TMS 6
Ground 7
TCK
DONE 9
INIT Chain
1. See section below on jumpers.
1
1
J4 (1x10)
1
2
4
8
1
10
J5 (1x10)
1
1
1
2
3
4
8
1
10
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Table 3. sysCONFIG Header Pinout (J40)
Function Pin Function
CCLK
BUSY / SISPI
1
DI/D0
D7 / DOUT
DONE
D7
D6
D5
D4
D3
D2
D1
D0
CSN
CS1N
Vcc Bank8
Ground
1. See section below on jumpers.
1
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
1
1
27 28
29 30
31 32
33 34
1 2
3 4
5 6
7 8
9 10
Ground
D6
Vcc Bank8
INITN
PROGRAMN
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
WRITEN
CFG0
CFG1
CFG2
Table 4. sysCONFIG Loop-Through Header Pinout (J41)
Function Pin Function
CCLK
N/C 3 4 N/C
DOUT / CSSON 5 6 N/C
N/C 7 8 INITN
DONE 9 10 PROGRAMN
D7 11 12 Ground
D6 13 14 Ground
D5 15 16 Ground
D4 17 18 Ground
D3 19 20 Ground
D2 21 22 Ground
D1 23 24 Ground
D0 25 26 Ground
CSN / N/C
CS1N / N/C
N/C 31 32 N/C
Ground 33 34 N/C
1. See section below on jumpers.
1
1
1 2 Ground
27
29
28 WRITEN
30 N/C
JTAG and sysCONFIG Jumpers
There are several JTAG and sysCONFIG cabling options that can be selected using jumpers.
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Lattice Semiconductor User’s Guide
Default Jumpers Settings
This table lists the default settings for all of the jumpers on the LatticeECP2 Standard Evaluation Board. For a complete description of each jumper refer to the next sections.
Table 5. Default Jumper Settings
JTAG Jumpers
Table 6. TDO Chain Jumper
Location
J1
J3 1 to 2 J30
J7 2 to 3 J31 Open
J8 1 to 2 J32 Open
J9 Open J33 1 to 2
J10 Open J34 2 to 3
J11 Open J35 Open
J13 Open J36 Open
J17 1 to 2 J37 1 to 2
J18 1 to 2 J38 Open
J19 Open J39 1 to 2
J22 Open J43
J23 Open J44 1 to 2
J24 Open
Position Location Position
1 to 2 J29 1 to 2
1 to 2
3 to 4
5 to 6
1 to 2
3 to 4
5 to 6
Location
J7
Determines the JTAG TDO path.
Position Function Default
1 to 2 Multiple boards, but not the last board in the chain
2 to 3
Single board, or the last board in a chain X
Table 7. TCK Pull-Down
Location
There should be only one TCK pull-down on a JTAG chain.
Position Function Default
1 to 2
Open
Pull-down, 4.7K to ground X
No pull-down
Table 8. PROGRAMN Pin to JTAG
Location
J10
This jumper is normally not installed.
Position Function Default
1 to 2 Connects PROGRAMN pin to the JTAG chain
Open
Disconnects PROGRAMN pin from JTAG chain X
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Table 9. INITN Pin to JTAG
Location
J11
This jumper is normally not installed.
Position Function Default
1 to 2 Connects INITN pin to the JTAG chain
Open
Disconnects INITN pin from the JTAG chain X
sysCONFIG Jumpers
Table 10. CS1N
Location
J31
Position Function Default
1 to 2 Pulls CS1N high
2 to 3 Pulls CS1N low
Open
No pull-up or pull-down on CS1N X
Table 11. CSN
Location Position Function Default
1 to 2 Pulls CSN high
J32
2 to 3 Pulls CSN low
Open
No pull-up or pull-down on CSN X
Table 12. DI/D[0]
Location Position Function Default
J33
1 to 2
2 to 3 Routes data bit D[0] to J40-5 for SPIFAST support
Routes DI to J40-5 to support serial mode X
Table 13. D[7]/DOUT
Location Position Function Default
J34
1 to 2 Routes D[7] to J40-7 for SPI sysCONFIG support
2 to 3
Routes DOUT to J40-7 to support serial mode X
Table 14. CSON to CS1N (Loop-Through)
Location Position Function Default
J35
1 to 2 CSON drives CS1N on the loop-through connector
Open
CS1N on the loop-through connector is open X
Table 15. CSON to CSN (Loop-Through)
Location Position Function Default
J36
1 to 2 CSON drives CSN on the loop-through connector
Open
CSN on the loop-through connector is open X
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Lattice Semiconductor User’s Guide
Table 16. Configuration Mode (J43)
Configuration
Mode
SPI (default)
Reserved Jumper (0) Jumper (0) Open (1)
SPIm Jumper (0) Open (1) Jumper (0)
Reserved Jumper (0) Open (1) Open (1)
Reserved Open (1) Jumper (0) Jumper (0)
Slave Serial Open (1) Jumper (0) Open (1)
Reserved Open (1) Open (1) Jumper (0)
Slave Parallel Open (1) Open (1) Open (1)
CFG[2],
1 to 2
Jumper (0) Jumper (0) Jumper (0)
CFG[1],
3 to 4
CFG[0],
5 to 6
Table 17. SPIFAST
Location
J44
All SPI Serial Flash shipped with this board support fast read. This jumper must be removed when using the sysCONFIG parallel port.
Position Function Default
1 to 2
Open
SPI fast read, enables read op-code 0x0B X
SPI normal read, enables read op-code 0x03
Table 18. Jumper Settings for sysCONFIG Parallel
Location
J31
J32 Open See schematic
J33 1 to 2
J34 2 to 3
J43 All Open
J44 Open
J35, J36 Open Bypass Overflow
J35, J36 1 to 2 Flow-through Overflow
Position Notes
Open See schematic
Table 19. Jumper Settings for sysCONFIG Serial
Location
J31
J32 Open
J33 1 to 2
J34 2 to 3
J43
J44 Don’t Care
J35, J36 Open Bypass Overflow
J35, J36 1 to 2 Not allowed
Position Notes
Open
Open
3 to 4 Open if driven by cable
Open
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Lattice Semiconductor User’s Guide
Table 20. Jumper Settings for SPI Emulation via J40
Location
J31
J32 Open
J33 2 to 3
J34 1 to 2
J43
J44 Open
J35, J36 Open Bypass Overflow
J35, J36 1 to 2 Not allowed
Position Notes
Open
1 to 2 Open if driven by cable
3 to 4 Open if driven by cable
5 to 6 Open if driven by cable
Power Setup
For stand-alone board operation, i.e. outside of a PCI/PCI-X backplane, the evaluation board must be supplied with
a single 5V DC power supply. 5V DC power may be applied using an AC adapter, such as the Condor Electronics
S-5V0-4A0-U11-206IP (or similar), plugged into the power jack at J47, or via the banana jacks at J45 (ground) and
J46 (5V DC).
Table 21. AC Adaptor Specifications
Voltage 5VDC +/- 10%
Current Capacity Up to 4A
Polarity Positive Center
Connector I.D. 0.1” (2.5mm)
Connector O.D. 0.218” (5.5mm)
When the board is inserted into a PCI/PCI-X backplane, the on-board 3.3V regulator is automatically disabled; all
onboard power will be derived from the PCI/PCI-X 3.3V power rail.
Additional on-board regulators supply 1.2V, an adjustable voltage, and 5V (for the optional LCD panel). The adjustable voltage is set by the potentiometer R36, on the right side of the board, and can be set to any value between
1.22V and 2.5V.
The header at J30 allows a current measuring device to be inserted between 1.2V and the FPGA core. To measure
current remove power from the board, remove all of the jumpers at J30, install a meter between the odd pins and
the even pins, for example between pins 1 and 2, and apply power to the board. When measurement is complete,
remove power from the board and re-install all three jumpers.
Table 22. 1.2V to V
Location
J30
The header at J29 allows a current measuring device to be inserted between 3.3V and the FPGA’s V
Core
CC
Position Function Default
1 to 2
3 to 4 X
5 to 6 X
Connects 1.2V to the FPGA Core
X
CCAUX.
To
measure current, remove power from the board, remove the jumper at J29, install a meter between pins 1 and 2,
and apply power to the board. When measurement is complete, remove power from the board and re-install the
jumper.
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Lattice Semiconductor User’s Guide
Table 23. 3.3V to V
Location
J29
CCAUX
Position Function Default
1 to 2 Connects 3.3V to VCCAUX X
The LatticeECP2 is divided into 10 banks of I/Os (see Table 24), and each of these banks has a separate and independent V
Each bank supports voltages from 1.2V to 3.3V. However, because some banks, such as banks 4
CC.
and 5, which connect to PCI/PCI-X, require a fixed voltage, not all of the banks on this evaluation board are adjustable. The jumpers listed in Table 24 allow the user to select the voltage (V
) applied to the adjustable banks.
CCIO
Note that if the LatticeECP2 will be configured from the SPI Serial Flash, bank 8 must be set to 3.3V (because SPI
Serial Flash is 3.3V). Also, if the board is plugged into a PCI/PCI-X connector, bank 6 must be set to 3.3V (because
the PCI clock is routed to bank 6 on this board).
Table 24. Bank Voltage Selection
Bank
0 I/O — 3.3V Only
1 I/O — 3.3V Only
2 I/O J37
3 I/O — 3.3V Only
4 I/O — 3.3V Only
5 I/O — 3.3V Only
6 I/O J18
7 I/O J17
8 sysCONFIG J39
V
CCJ
J17, 18, 37, and 39 must have no more than one jumper installed.
Function Jumper Settings
1 - 2 = 3.3V
3 - 4 = ADJ
5 - 6 = 1.2V
1 - 2 = 3.3V
3 - 4 = ADJ
5 - 6 = 1.2V
1 - 2 = 3.3V
3 - 4 = ADJ
5 - 6 = 1.2V
1 - 2 = 3.3V
3 - 4 = ADJ
5 - 6 = 1.2V
ispJTAG™
— 3.3V Only
The following tables detail the various I/O standards supported by the LatticeECP2 sysIO™ structures. More information can be found in Lattice technical note TN1102, LatticeECP2 sysIO Usage Guide, available on the Lattice
web site at www.latticesemi.com.
Table 25. Mixed Voltage I/O Support
Input sysIO Standards
V
CCIO
1.2V
1.5V Ye s Ye s Ye s Ye s Ye s
1.8V Ye s Ye s Ye s Ye s Ye s
2.5V Ye s Ye s Ye s Ye s
3.3V Ye s Ye s Ye s Ye s
For example, if V
1.2V 1.5V 1.8V 2.5V 3.3V 1.2V 1.5V 1.8V 2.5V 3.3V
Ye s Ye s Ye s Ye s
is 3.3V, then signals from devices powered by 1.2V, 2.5V, or 3.3V can be input and the
CCIO
thresholds will be correct, assuming the user has also selected the desired input level using ispLEVER
Output levels are tied directly to V
CCIO.
10
Output sysIO Standards
®
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LatticeECP2 Standard Evaluation Board
Lattice Semiconductor User’s Guide
Table 26. sysIO Standards Supported per Bank
Top Side,
Description
Types of I/O Buffers
Output Standards
Supported
Banks 0-1
Single-ended Single-ended and
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I, II
SSTL25 Class I, II
SSTL33 Class I, II
HSTL15 Class I
HSTL18_I, II
SSTL18D Class I, II
SSTL25D Class I, II
SSTL33D Class I, II
HSTL15D Class I
HSTL18D Class I, II
PCI33
LVDS25E
LVPECL
BLVDS
RSDS
1
1
1
1
Inputs All Single-ended, Differ-
ential
Clock Inputs All Single-ended, Differ-
ential
Right Side,
Banks 2-3
Differential
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I, II
SSTL25 Class I, II
SSTL33 Class I, II
HSTL15 Class I
HSTL18 Class I, II
SSTL18D Class I, II
SSTL25D Class I, II
SSTL33D Class I, II
HSTL15D Class I, II
HSTL18D Class I, II
PCI33
LVDS
LVDS25E
LVPECL
BLVDS
RSDS
1
1
1
1
All Single-ended,
Differential
All Single-ended,
Differential
Bottom Side,
Banks 4-5
Left Side,
Banks 6-7
Single-ended Single-ended and
Differential
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I
SSTL2 Class I, II
SSTL3 Class I, II
HSTL15 Class I
HSTL18 Class I, II
SSTL18D Class I, II
SSTL25D Class I, II,
SSTL33D Class I, II
HSTL15D Class I
HSTL18D Class I, II
PCI33
LVDS25E
LVPECL
BLVDS
RSDS
1
1
1
1
All Single-ended,
Differential
All Single-ended,
Differential
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I
SSTL2 Class I, II
SSTL3 Class I, II
HSTL15 Class I, III
HSTL18 Class I, II, III
SSTL18D Class I,
SSTL25D Class I, II,
SSTL33D_I, II
HSTL15D Class I
HSTL18D Class I, II
PCI33
LVDS
LVDS25E
LVPECL
BLVDS
RSDS
1
1
1
1
All Single-ended,
Differential
All Single-ended,
Differential
PCI Support PCI33 no clamp PCI33 no clamp PCI33 with clamp PCI33 no clamp
LVDS Output Buffers LVDS (3.5mA) Buffers
1. These differential standards are implemented by using complementary LVCMOS drivers and external resistors.
2. Available on 50% of the I/Os in the Bank.
2
LVDS (3.5mA) Buffers
2
PCI/PCI-X
The LatticeECP2 Standard Evaluation Board is designed to be compatible with PCI (PCI SIG 2.2 specification) and
PCI-X (Mode 1). All necessary signals required for 64-bit PCI/PCI-X operation are provided, as shown in Table 27
and Table 28.
Table 27. PCI Connections - Solder Side
J48 Signal Name LatticeECP2 Pin sysIO Bank Note
1 PCI_TRSTN - - TP10, PD if master
2 +12V - - Decoupling cap
3 PCI_TMS - - TP11, PU if master
4 PCI_TDI - - TP12, J14-4, J13
5 +5V - - NC
6 PCI_INTA_N - - J19
7 PCI_INTC_N - - J19
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