Lattice ispPAC-POWR604 User Manual

ispPAC-POWR604

In-System Programmable Power Supply

Sequencing Controller and Monitor

August 2004 Data Sheet

Features

■

Monitor and Control Multiple Power
Supplies

• Simultaneously monitors and sequences up to six
power supplies

• Sequence controller for power-up conditions

• Provides four output control signals

• Programmable digital and analog circuitry

■

Embedded PLD for Sequence Control

• Implements state machine and input conditional
events

• In-System Programmable (ISP™) through JTAG
and on-chip E2CMOS

■

Embedded Programmable Timers

•Two Programmable 8-bit timers (32µs to 524ms)

• Programmable time delay for pulse stretching or
other power supply management

■

Analog Comparators for Monitoring

• Six analog comparators for monitoring

• 192 precise programmable threshold levels
spanning 1.03V to 5.72V

• Each comparator can be independently config­ured around standard logic supply voltages of

1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5V

• Other user-defined voltages possible

• Six direct comparator outputs

■

Embedded Oscillator

• Built-in clock generator, 250kHz

• Programmable clock frequency

• Programmable timer pre-scaler

• External clock support

■

Programmable Open-Drain Outputs

•Four digital outputs for logic and power supply
control

• Expandable with ispMACH™ 4000 CPLD

■

2.25V to 5.5V Supply Range

• In-system programmable at 3.0V to 5.5V

• Industrial temperature range: -40°C to +85°C

•Automotive temperature range: -40°C to +125°C

• 44-pin TQFP package

• Lead-free package option

®

Application Block Diagram

Voltage Monitor 6
Voltage Monitor 5

2.5-5V Supply

OUT5
OUT6
OUT7
OUT8

Comp1
Comp2
Comp3
Comp4
Comp5
Comp6

POR

CREF

0.1uF1.0uF

Digital
Logic

CPU_RESETN

BROWNOUT_INT

LOAD_ENABLE

POWER_OK

0.1uF

CPU/ASIC

Card etc.

V

DD

CARD_RESETN

WDT_IN

INT_ACK

DONE

6 Analog Inputs

VMON1
VMON2
VMON3
VMON4
VMON5
VMON6

CLK

RESET

IN1
IN2
IN3
IN4

VDD VDDINP

ispPAC-POWR604

Power Sequence

Controller

Description

The Lattice ispPAC
system programmable logic and in-system programma­ble analog circuits to perform special functions for
power supply sequencing and monitoring. The ispPAC­POWR604 device has the capability to be configured
through software to control up to four outputs for power
supply sequencing and six comparators monitoring sup­ply voltage limits, along with four digital inputs for inter­facing to other control circuits or digital logic. Once
configured, the design is downloaded into the device
through a standard JTAG interface. The circuit configu-
ration and routing are stored in non-volatile E
PAC-Designer,
software package, gives users the ability to design the
logic and sequences that control the power supplies or
regulator circuits. The user has control over timing func­tions, programmable logic functions and comparator
threshold values as well as I/O configurations.

®

-POWR604 incorporates both in-

2

®

an easy-to-use Windows-compatible

CMOS.

© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com

1

pwr604_02.1

Lattice Semiconductor ispPAC-POWR604 Data Sheet

Power Supply Sequence Controller and Monitor

The ispPAC-POWR604 device is specifically designed as a fully-programmable power supply sequencing controller
and monitor for managing up to four separate power supplies, as well as monitoring up to six analog inputs or sup­plies. The ispPAC-POWR604 device contains an internal PLD that is programmable by the user to implement digi­tal logic functions and control state machines. The internal PLD connects to two programmable timers, special
purpose I/O and the programmable monitoring circuit blocks. The internal PLD and timers can be clocked by either
an internal programmable clock oscillator or an external clock source.

The voltage monitors are arranged as six independent comparators each with 192 programmable trip point set­tings. Monitoring levels are set around the following standard voltages: 1.2V, 1.5V, 1.8V, 2.5V, 3.3V or 5.0V.

All six voltages can be monitored simultaneously (i.e., continuous-time operation). Other non-standard voltage lev­els can be accounted for using various scale factors.

For added robustness, the comparators feature a variable hysteresis that scales with the voltage they monitor.
Generally, a larger hysteresis is better. However, as power supply voltages get smaller, that hysteresis increasingly
affects trip-point accuracy. Therefore, the hysteresis is +/-16mV for 5V supplies and scales down to +/-3mV for 1.2V
supplies, or about 0.3% of the trip point.

The programmable logic functions consist of a block of 20 inputs with 41 product terms and eight macrocells. The
architecture supports the sharing of product terms to enhance the overall usability.

The four output pins are open-drain outputs. These outputs can be used to drive enable lines for DC/DC converters
or other control logic associated with power supply control. The four outputs are driven from the macrocells.

Figure 1. ispPAC-POWR604 Block Diagram

ispPAC-POWR604

VMON1
VMON2
VMON3

VMON4
VMON5
VMON6

IN1
IN2

IN3
IN4

RESET

Analog

Inputs

Digital
Inputs

5

6

6

Sequence
Controller

CPLD

20 I/P & 8

Macrocell

GLB

250kHz

Internal

OSC

2 Timers

Comparator

Outputs

4

Logic

Outputs

COMP1
COMP2
COMP3
COMP4
COMP5
COMP6

OUT5
OUT6
OUT7
OUT8

CLKIO

2

Lattice Semiconductor ispPAC-POWR604 Data Sheet

Pin Descriptions

Number Name Pin Type Voltage Range Description

1NC— — No Connect

2NC— — No Connect

3NC— — No Connect

4NC— — No Connect

5 VDD Power 2.25V-5.5V Main Power Supply

6 IN1 CMOS Input VDDINP

7 IN2 CMOS Input VDDINP

8 IN3 CMOS Input VDDINP

9 IN4 CMOS Input VDDINP

10 RESET

CMOS input VDD

11 VDDINP Power 2.25V-5.5V

12 OUT5

13 OUT6

14 OUT7

15 OUT8

8

O/D Output 2.25V-5.5V

8

O/D Output 2.25V-5.5V

8

O/D Output 2.25V-5.5V

8

O/D Output 2.25V-5.5V

1, 3

1, 3

1, 3

1, 3

6

3

2

2

2

2

16 NC — — No Connect

17 NC — — No Connect

18 COMP6 O/D Output 2.25V-5.5V

19 COMP5 O/D Output 2.25V-5.5V

20 COMP4 O/D Output 2.25V-5.5V

21 COMP3 O/D Output 2.25V-5.5V

22 COMP2 O/D Output 2.25V-5.5V

23 COMP1 O/D Output 2.25V-5.5V

2

2

2

2

2

2

24 TCK TTL/LVCMOS Input VDD Test Clock (JTAG Pin)

25 POR

26 CLK Bi-directional I/O VDD

O/D Output 2.25V-5.5V Power-On-Reset Output

2, 5

27 GND Ground Ground

28 TDO TTL/LVCMOS Output VDD Test Data Out (JTAG Pin)

29 TRST

TTL/LVCMOS Input VDD

30 TDI TTL/LVCMOS Input VDD Test Data In, 50k Ohm Pull-up (JTAG Pin)

31 TMS TTL/LVCMOS Input VDD

32 VMON1 Analog Input 0V-5.72V

33 VMON2 Analog Input 0V-5.72V

34 VMON3 Analog Input 0V-5.72V

35 VMON4 Analog Input 0V-5.72V

36 VMON5 Analog Input 0V-5.72V

37 VMON6 Analog Input 0V-5.72V

4

4

4

4

4

4

38 NC — — No Connect

39 CREF Reference 1.17V

7

40 NC — — No Connect

41 NC — — No Connect

Input 1

Input 2

Input 3

Input 4

PLD Reset Input, Active Low

Digital Inputs Power Supply

Open-Drain Output

Open-Drain Output

Open-Drain Output

Open-Drain Output

VMON6 Comparator Output (Open-Drain)

VMON5 Comparator Output (Open-Drain)

VMON4 Comparator Output (Open-Drain)

VMON3 Comparator Output (Open-Drain)

VMON2 Comparator Output (Open-Drain)

VMON1 Comparator Output (Open-Drain)

Clock Output (Open-Drain) or Clock Input

Test Reset, Active Low, 50k Ohm Internal Pull-up
(JTAG Pin, Optional Use)

Test Mode Select, 50k Ohm Internal Pull-up (JTAG
Pin)

Voltage Monitor Input 1

Voltage Monitor Input 2

Voltage Monitor Input 3

Voltage Monitor Input 4

Voltage Monitor Input 5

Voltage Monitor Input 6

Reference for Internal Use, Decoupling Capacitor
(.1uf Required, CREF to GND)

3

Lattice Semiconductor ispPAC-POWR604 Data Sheet

Pin Descriptions (Continued)

Number Name Pin Type Voltage Range Description

42 NC — — No Connect

43 NC — — No Connect

44 NC — — No Connect

1. IN1...IN4 are digital inputs to the PLD. The thresholds for these pins are referenced by the voltage on VDDINP.

2. The open-drain outputs can be powered independently of VDD and pulled up as high as +6.0V (referenced to ground). Exception, CLK pin
26 can only be pulled as high as VDD.

3. VDDINP can be chosen independent of V

4. The six VMON inputs can be biased independently of VDD. The six VMON inputs can be as high as 7.0V Max (referenced to ground).

5. CLK is the PLD clock output in master mode. It is re-routed as an input in slave mode. The clock mode is set in software during design
time. In output mode it is an open-drain type pin and requires an external pull-up resistor (pullup voltage must be
POWR604 devices can be tied together with one acting as the master, the master can use the internal clock and the slave can be clocked
by the master. The slave needs to be set up using the clock as an input.

6. RESET

7. The CREF pin requires a 0.1µF capacitor to ground, near the device pin. This reference is used internally by the device. No additional

8. The four digital outputs (pins 12-15) are named OUT5-OUT8 to match ispPAC-POWR1208 pin names and to allow easy design migration.

is an active low INPUT pin, external pull-up resistor required. When driven low it resets all internal PLD flip-flops to zero, and may
turn “ON” or “OFF” the output pins, depending on the polarity configuration of the outputs in the PLD. If a reset function is needed for the
other devices on the board, the PLD inputs and outputs can be used to generate these signals. The RESET connected to the POR pin can
be used if multiple ispPAC-POWR604 devices are cascaded together in expansion mode or if a manual reset button is needed to reset the
PLD logic to the initial state. While using the ispPAC-POWR604 in hot-swap applications it is recommended that either the RESET pin be
connected to the POR pin, or connect a capacitor to ground (such that the time constant is 10 ms with the pull-up resistor) from the RESET
pin.

external circuitry should be connected to this pin.

It applies only to the four logic inputs IN1-IN4.

DD.

). Multiple ispPAC-

≤ V

DD

Absolute Maximum Ratings

Absolute maximum ratings are shown in the table below. Stresses above those listed values may cause permanent
damage to the device. Functional operation of the device at these or any other conditions above those indicated in
the operating sections of this specification is not implied.

Symbol Parameter Conditions Min. Max. Units

VDD Core supply voltage at pin — -0.5 6.0 V

VDD

V

VMON Input voltage applied, V

V

T

T

T

1. V

2. Digital inputs are tolerant up to 5.5V, independent of the V

1

INP

2

IN

TRI

S

A

SOL

DDINP

supply voltage for the given input logic range.

Digital input supply voltage for IN1-IN4 — -0.5 6.0 V

Input voltage applied, digital inputs — -0.5 6.0 V

MON

Tr istated or open drain output, external voltage applied

≤

(CLK pin 26 pull-up

VDD).

Storage temperature — -65 150 °C

Ambient temperature with power applied — -55 125 °C

Maximum soldering temperature (10 sec. at 1/16 in.) — — 260 °C

is the supply pin that controls logic inputs IN1-IN4 only. Place 0.1µF capacitor to ground and supply the V

voltage monitor inputs — -0.5 7.0 V

— -0.5 6.0 V

pin with appropriate

DDINP

voltage.

DDINP

4

Lattice Semiconductor ispPAC-POWR604 Data Sheet

Recommended Operating Conditions

Symbol Parameter Conditions Min. Max. Units

V

DD

V

DDPROG

V

DDINP

V

IN

V

MON

1

2

3

Erase/Program
Cycles

T

APROG

T

A

1. The ispPAC-POWR604 device must be powered from 3.0V to 5.5V during programming of the E

2. V

3. Digital inputs are tolerant up to 5.5V, independent of the V

is the supply pin that controls logic inputs IN1-IN4 only. Place 0.1µF capacitor to ground and supply the V

DDINP

supply voltge for the given input logic range.

Core supply voltage at pin 2.25 5.5 V

Core supply voltage at pin During E

2

cell programming 3.0 5.5 V

Digital input supply voltage for IN1-IN4 2.25 5.5 V

Input voltage digital inputs 0 5.5 V

Voltage monitor inputs V

MON1

- V

MON6

0 6.0 V

EEPROM, programmed at
V

Ambient temperature during
programming

Ambient temperature

DDINP

= 3.0V to 5.5V

DD

-40°C to +85°C

Power applied - Industrial -40 +85 °C

Power applied - Automotive -40 +125 °C

2

CMOS memory.

voltage.

1000 — Cycles

-40 +85 °C

pin with appropriate

DDINP

Analog Specifications

Over Recommended Operating Conditions

Symbol Parameter Conditions Min. Typ. Max. Units

I

DD

Supply Current Internal Clock = 250kHz — 5 10 mA

Reference

Symbol Parameter Conditions Min. Typ. Max. Units

1

V

REF

1. CREF pin requires a 0.1µF capacitor to ground.

Reference voltage at CREF pin T = 25°C — 1.17 — V

Voltage Monitors

Symbol Parameter Conditions Min. Typ. Max. Units

R

IN

V

Range Programmable voltage monitor trip

MON

V

Accuracy Absolute accuracy of any trip point T = 25 °C,

MON

V

Tempco

MON

HYST Hysteresis of V

PSR Trip point sensitivity to V

1. See typical performance curves.

Input impedance 70 100 130 k

point (192 steps)

V

= 3.3V

1

Temperature drift of any trip point -40°C to +85°C 50 ppm/ °C

DD

1.03 5.72 V

-0.9 +0.9 %

-40°C to +125°C 76 ppm/ °C

V

HYST

= HYST*V

MON

input,

(+/-3 to +/-13mV)

MON

DD

V

= 3.3V, 25°C +/- 0.3% of

DD

trip point

setting

V

= 3.3V 0.06 %/V

DD

Ω

%

5

Lattice Semiconductor ispPAC-POWR604 Data Sheet

Power-on-Reset

Symbol Parameter Conditions Min. Typ. Max. Units

V

supply threshold beyond which POR

V

LPOR

V

HPOR

1. POR tests run with 10k

DD

output is guaranteed to be driven low

V

supply threshold above which POR

DD

output is guaranteed driven high, and device
initializes

Ω resistor pulled up to V

DD.

V

ramping up

DD

ramping up

V

DD

1

1

——1.15 V

——2.1 V

AC/Transient Characteristics

Over Recommended Operating Conditions

Symbol Parameter Conditions Min. Typ. Max. Units.

Voltage Monitors

t

PD5

t

PD20

Propagation Delay. Output
transitions after a step input.

Propagation Delay. Output
transitions after a step input.

Oscillators

f

CLK

PLDCLK
Range

Internal master clock frequency Note 2 230 — 330 kHz

Programmable frequency range
of PLD clock (8 binary steps)

PLDCLKext Max frequency of applied

external clock source

Timers

Timeout
Range

1. See Typical Performance Graphs.

2. f

frequency deviation with respect to VDD, 0.4%/volt, typical.

CLK

Range of programmable
time-out duration (15 steps)

Glitch filter set to 5µs.
Input V

+ 100mV to V

TRIP

Glitch filter set to 20us.
Input V

+ 100mV to V

TRIP

Internal Osc 250kHz

External clock applied

Internal Osc 250kHz

1

1

TRIP

TRIP

- 100mV

- 100mV

—5—µs

—20—µs

1.95 — 250 kHz

—— 1MHz

0.03 — 524 ms

Digital Specifications

Over Recommended Operating Conditions

Symbol Parameter Conditions Min. Typ. Max. Units

≤

V

≤

I

I

IL,

IH

I

PU

V

OL

I

SINKOUT

Input or I/O leakage current, no pull-up0V

25 °C

Input pull-up current (TMS, TDI,
TRST

)

Open-drain output set LOW I

Maximum sink current for logic out-

25 °C 70 µA

SINKOUT

(Note 1)
puts [OUT5-OUT8], [COMP1­COMP6]

I

SINKTOTAL

1. [OUT5-OUT8] and [COMP1-COMP6] can sink up to 20mA max. per pin for LEDs, etc. However, output voltage levels may exceed VOL. Total
combined sink currents from all outputs (OUT, COMP) should not exceed I

Total combined sink currents from all
outputs [OUT, COMP]

(Note 1)

V

IN

DDINP

or V

DD

+/-10 µA

= 4mA 0.4 V

20 mA

80 mA

SINKTOTAL

.

6

Lattice Semiconductor ispPAC-POWR604 Data Sheet

DC Input Levels: IN1-IN4

VIL (V) VIH (V)

Standard

Min. Max. Min. Max.

CMOS, LVCMOS3.3, LVTTL, TTL -0.3 0.8 2.0 5.5

LVCMOS2.5 -0.3 0.7 1.7 5.5

Note: V
V

DDINP.

is the input supply pin for IN1-IN4 digital logic input pins. The logic threshold trip point of IN1-IN4 is dependent on the voltage at

DDINP

Transient Characteristics

Over Recommended Operating Conditions

Symbol Parameter Conditions Min. Typ. Max. Units

PLD Timing

Digital Glitch
Filter

t

CO

t

SU

t

H

t

PD

t

RST

1. External clock 1MHz. Open drain outputs with 2k pull-up resistor to VDD.

Note: All the above parameters apply to signal paths from the digital inputs [IN1-IN4].

Minimum pulse width to transition through
glitch filter.

Clock to Out Delay. Rising edge of clock to
output transition.

Time that input needs to be present when
using a registered function with the clock.

Time that input needs to be held valid after
the clock edge when using a registered

Applied to IN1-IN4

Stable input before
clock edge (Note 1)

Data valid before clock
(Note 1)

Hold data after clock

20 µs

300 ns

20 µs

0 µs

function with the clock.

Propagation delay internal to the
embedded PLD

90 ns

RESET pulse width 25 µs

7

Lattice Semiconductor ispPAC-POWR604 Data Sheet

Timing for JTAG Operations

Symbol Parameter Conditions Min Typ. Max Units

t

CKMIN

t

CKH

t

CKL

t

MSS

t

MSH

t

DIS

t

DIH

t

DOZX

t

DOV

t

DOXZ

t

RSTMIN

t

PWP

t

PWE

1. t

represents programming pulse width for a single row of E2CMOS cells.

PWP

Minimum clock period 1 µs

TCK high time 200 ns

TCK low time 200 ns

TMS setup time 15 ns

TMS hold time 50 ns

TDI setup time 15 ns

TDI hold time 50 ns

TDO float to valid delay 200 ns

TDO valid delay 200 ns

TDO valid to float delay 200 ns

Minimum reset pulse width 40 ns

Time for a programming operation

1

40 100 ms

Time for an erase operation 40 100 ms

t

t

CKH

CKL

t

CK

t

MSS

MSH

t

MS

t

DIStDIH

t

DI

t

DOZH

t

DO

t

DOV

t

CKMIN

t

DOXZ

t

CK

t

MSS

t

MS

Program and Erase cycles

executed in Run-Test/Idle

t

PWP, tPWE

t

MSSt

8

Lattice Semiconductor ispPAC-POWR604 Data Sheet

Typical Performance Graphs

7000

6000

5000

4000

Count

3000

2000

1000

0

Trip Point Error 25°C

MON

3

Typical V

Accuracy vs. Temperature

Comparator Trip Point

MON

Propagation Delay vs. OverdriveV

125

100

Glitch Filter = 20µs

75

50

Propagation Delay (µs)

25

Glitch Filter = 5µs

0

10-1 -0.8 -0.6 -0.4 -0.2 0 10.2 0.4 0.6 0.8 20 50 100 200

Input Overdrive (mV)Trip Point Error %

Note: Typical propagation delay of V
as a function of overdrive beyond selected trip point.

inputs to outputs

MON

2.5

2

1.5

% Error

1

0.5

0

-0.5

-50 0 50 100 150

Temperature (°C)

9