Lattice ispPAC-POWR1220AT8 User Manual

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®

ispPAC-POWR1220AT8

In-System Programmable Power Supply

Monitoring, Sequencing and Margining Controller

August 2007 Data Sheet DS1015

Features

Monitor, Control, and Margin Multiple
Power Supplies

• Simultaneously monitors up to 12 power
supplies

• Provides up to 20 output control signals

• Provides up to eight analog outputs for
margining/trimming power supply voltages

• Programmable digital and analog circuitry

Power Supply Margin and Trim Functions

• Trim and margin up to eight power supplies

• Dynamic voltage control through I

• Four hardware selectable voltage profiles

• Independent Digital Closed-Loop Trim function
for each output

Embedded PLD for Sequence Control

• 48-macrocell CPLD implements both state
machines and combinatorial logic functions

Embedded Programmable Timers

• Four independent timers

• 32µs to 2 second intervals for timing sequences

Analog Input Monitoring

• 12 independent analog monitor inputs

• Differential inputs for remote ground sense

• Two programmable threshold comparators per
analog input

• Hardware window comparison

• 10-bit ADC for I

2

C monitoring

High-Voltage FET Drivers

• Power supply ramp up/down control

• Programmable current and voltage output

• Independently configurable for FET control or
digital output

2-Wire (I

• Comparator status monitor

• ADC readout

• Direct control of inputs and outputs

• Power sequence control

• Dynamic trimming/margining control

2

C/SMBus™ Compatible) Interface

2

C

Application Block Diagram

Primary

Supply

Primary

Supply

Primary

Supply

Primary

Supply

Primary

Supply

3.3V

2.5V

1.8V

POL#1

POL#N

Power Supply

Margin/Trim

Control Block

ADC

12 Analog Inputs

and Voltage Monitors

ispPAC-POWR1220AT8

8 Analog

Trim

Outputs

4 Timers

n

igraM/

m

ir
T

Enables

16 Digital

Outputs

48 Macrocells

6 Digital

Inputs

Other Control/Supervisory

Signals

4 MOSFET

Drivers

CPLD

83 Inputs

2

C

I

Interface

I

Bus

2

Voltage

C

itry

u

Other Board Circ

Monitoring

CPU

Digital Monitoring

Description

Lattice’s Power Manager II ispPAC-POWR1220AT8 is a
general-purpose power-supply monitor, sequence and
margin controller, incorporating both in-system pro­grammable logic and in-system programmable analog
functions implemented in non-volatile E
nology. The ispPAC-POWR1220AT8 device provides 12
independent analog input channels to monitor up to 12
power supply test points. Each of these input channels
offers a differential input to support remote ground
sensing, and has two independently programmable
comparators to support both high/low and in-bounds/
out-of-bounds (window-compare) monitor functions. Six
general-purpose digital inputs are also provided for mis­cellaneous control functions.

2

CMOS

®

tech-

3.3V Operation, Wide Supply Range 2.8V to

3.96V

• In-system programmable through JTAG

• Industrial temperature range: -40°C to +85°C

• 100-pin TQFP package, lead-free option

© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.

www.latticesemi.com

The ispPAC-POWR1220AT8 provides 20 open-drain
digital outputs that can be used for controlling DC-DC
converters, low-drop-out regulators (LDOs) and opto­couplers, as well as for supervisory and general-pur­pose logic interface functions. Four of these outputs

1

DS1015_01.4

Lattice Semiconductor ispPAC-POWR1220AT8 Data Sheet

(HVOUT1-HVOUT4) may be configured as high-voltage MOSFET drivers. In high-voltage mode these outputs can
provide up to 10V for driving the gates of n-channel MOSFETs so that they can be used as high-side power
switches controlling the supplies with a programmable ramp rate for both ramp up and ramp down.

The ispPAC-POWR1220AT8 incorporates a 48-macrocell CPLD that can be used to implement complex state
machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. The status
of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as
inputs by the CPLD array, and all digital outputs may be controlled by the CPLD. Four independently programmable
timers can create delays and time-outs ranging from 32µs to 2 seconds. The CPLD is programmed using Logi­Builder™, an easy-to-learn language integrated into the PAC-Designer
monitor the status of any of the analog input channel comparators or the digital inputs.

In addition to the sequence control functions, the ispPAC-POWR1220AT8 incorporates eight DACs for generating
trimming voltage to control the output voltage of a DC-DC converter. The trimming voltage can be set to four hard­ware selectable preset values (voltage profiles) or can be dynamically loaded in to the DAC through the I
Additionally, each power supply output voltage can be maintained typically within 0.5% tolerance across various
load conditions using the Digital Closed Loop Control mode. The operating voltage profile can either be selected
using external hardware pins or through the PLD outputs.

The on-chip 10-bit A/D converter can both be used to monitor the V
implementing digital closed loop mode for maintaining the output voltage of all power supplies controlled by the
monitoring and trimming section of the ispPAC-POWR1220AT8 device.

2

The I

C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the V

inputs, read back the status of each of the V

comparator and PLD outputs, control logic signals IN2 to IN5, con-

MON

trol the output pins, and load the DACs for the generation of the trimming voltage of the external DC-DC converter.

®

software. Control sequences are written to

voltage through the I

MON

2

C bus as well as for

2

C bus.

MON

Figure 1. ispPAC-POWR1220AT8 Block Diagram

VPS0

VPS1

VMON1+

VMON1GS

VMON2+

VMON2GS

VMON3+

VMON3GS

VMON4+

VMON4GS

VMON5+

VMON5GS

VMON6+

VMON6GS

VMON7+

VMON7GS

VMON8+

VMON8GS

VMON9+

VMON9GS

VMON10+

VMON10GS

VMON11+

VMON11GS

VMON12+

VMON12GS

IN1
IN2
IN3
IN4
IN5
IN6

A
N
D

V
O
L
T
A

E G

N O M
I

T
O

R
S

6

I

N

D

P

I

G
I

T

T U

A

S

L

VCCINP

1
2

A
N
A
L
O
G

I

N
P

S T U

VCCD (3)

VCCA

V
C
C
P
R
O
G

ADC

JTAG LOGIC

V

T

T

T

C

C

D

K

C

O

S M

J

OSCILLATOR

S

A

T

E

D

T
D

L

I

T

I

D
I

MARGIN/TRIM

CONTROL LOGIC

CPLD

48 MACROCELLS

83 INPUTS

CLOCK

P

M

L

C
L

C D

K

L
K

R

T E S E
b

TIMERS

(4)

VOLTAGE OUTPUT

DACS (8)

DAC

DAC

DAC

DAC

DAC

O
U
T

P
U

P

T

O

R

O

O

L

U
T

G N I

I2C

INTERFACE

S

S
C
L

GNDA (2)
D
A

DAC

DAC

DAC

TRIM1
TRIM2
TRIM3
TRIM4
TRIM5
TRIM6
TRIM7
TRIM8

D
R
I

V
R E

S

G I D
T I

L A
O

T U
P
U
T
S

4
F

E
T

1
6

O
P
E
N

­D

R
I A

N

GNDD (6)

HVOUT1
HVOUT2
HVOUT3
HVOUT4

OUT5/SMBA
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
OUT17
OUT18
OUT19
OUT20

2

Lattice Semiconductor ispPAC-POWR1220AT8 Data Sheet

Pin Descriptions

Number Name Pin Type Voltage Range Description

89 VPS0 Digital Input VCCD Trim Select Input 0 Registered by MCLK

90 VPS1 Digital Input VCCD Trim Select Input 1 Registered by MCLK

97 IN1

1IN2

2IN3

4IN4

6IN5

7IN6

2

3

3

3

3

3

Digital Input VCCINP

Digital Input VCCINP

Digital Input VCCINP

Digital Input VCCINP

Digital Input VCCINP

Digital Input VCCINP

47 VMON1 Analog Input -0.3V to 5.75V

46 VMON1GS Analog Input -0.2V to 0.3V

50 VMON2 Analog Input -0.3V to 5.75V

48 VMON2GS Analog Input -0.2V to 0.3V

52 VMON3 Analog Input -0.3V to 5.75V

51 VMON3GS Analog Input -0.2V to 0.3V

54 VMON4 Analog Input -0.3V to 5.75V

53 VMON4GS Analog Input -0.2V to 0.3V

56 VMON5 Analog Input -0.3V to 5.75V

55 VMON5GS Analog Input -0.2V to 0.3V

58 VMON6 Analog Input -0.3V to 5.75V

57 VMON6GS Analog Input -0.2V to 0.3V

62 VMON7 Analog Input -0.3V to 5.75V

61 VMON7GS Analog Input -0.2V to 0.3V

64 VMON8 Analog Input -0.3V to 5.75V

63 VMON8GS Analog Input -0.2V to 0.3V

66 VMON9 Analog Input -0.3V to 5.75V

65 VMON9GS Analog Input -0.2V to 0.3V

68 VMON10 Analog Input -0.3V to 5.75V

67 VMON10GS Analog Input -0.2V to 0.3V

70 VMON11 Analog Input -0.3V to 5.75V

69 VMON11GS Analog Input -0.2V to 0.3V

72 VMON12 Analog Input -0.3V to 5.75V

71 VMON12GS Analog Input -0.2V to 0.3V

3, 22, 36,

43, 88, 98

45, 87 GNDA

13, 38, 94 VCCD

60 VCCA

GNDD

8

8

7

7

Ground Ground Digital Ground

Ground Ground Analog Ground

Power 2.8V to 3.96V Core VCC, Main Power Supply

Power 2.8V to 3.96V Analog Power Supply

5 VCCINP Power 2.25V to 3.6VVCC for IN[1:6] Inputs

33 VCCJ Power 2.25V to 3.6VVCC for JTAG Logic Interface Pins

39 VCCPROG Power 3.0V to 3.6V

6

0V to 10V Open-Drain Output 1

12.5µA to 100µA Source
100µA to 3000µA Sink

86 HVOUT1

Open Drain Output

Current Source/Sink

1

1

1

1

1

1

4

5

4

5

4

5

4

5

4

5

4

5

4

5

4

5

4

5

4

5

4

5

4

5

PLD Logic Input 1 Registered by MCLK

PLD Logic Input 2 Registered by MCLK

PLD Logic Input 3 Registered by MCLK

PLD Logic Input 4 Registered by MCLK

PLD Logic Input 5 Registered by MCLK

PLD Logic Input 6 Registered by MCLK

Voltage Monitor 1 Input

Voltage Monitor 1 Ground Sense

Voltage Monitor 2 Input

Voltage Monitor 2 Ground Sense

Voltage Monitor 3 Input

Voltage Monitor 3 Ground Sense

Voltage Monitor 4 Input

Voltage Monitor 4 Ground Sense

Voltage Monitor 5 Input

Voltage Monitor 5 Ground Sense

Voltage Monitor 6 Input

Voltage Monitor 6 Ground Sense

Voltage Monitor 7 Input

Voltage Monitor 7 Ground Sense

Voltage Monitor 8 Input

Voltage Monitor 8 Ground Sense

Voltage Monitor 9 Input

Voltage Monitor 9 Ground Sense

Voltage Monitor 10 Input

Voltage Monitor 10 Ground Sense

Voltage Monitor 11 Input

Voltage Monitor 11 Ground Sense

Voltage Monitor 12 Input

Voltage Monitor 12 Ground Sense

VCC for E
Not Powered by V

2

Programming when the Device is

CCD

or V

CCA

High-voltage FET Gate Driver 1

3

Lattice Semiconductor ispPAC-POWR1220AT8 Data Sheet

Pin Descriptions (Cont.)

Number Name Pin Type Voltage Range Description

Open Drain Output

85 HVOUT2

Current Source/Sink

Open Drain Output

42 HVOUT3

Current Source/Sink

Open Drain Output

40 HVOUT4

Current Source/Sink

8 OUT5_SMBA Open Drain Output

9 OUT6 Open Drain Output

10 OUT7 Open Drain Output

11 OUT8 Open Drain Output

12 OUT9 Open Drain Output

14 OUT10 Open Drain Output

15 OUT11 Open Drain Output

16 OUT12 Open Drain Output

17 OUT13 Open Drain Output

18 OUT14 Open Drain Output

19 OUT15 Open Drain Output

20 OUT16 Open Drain Output

21 OUT17 Open Drain Output

23 OUT18 Open Drain Output

24 OUT19 Open Drain Output

25 OUT20 Open Drain Output

84 TRIM1 Analog Output

83 TRIM2 Analog Output

82 TRIM3 Analog Output

80 TRIM4 Analog Output

79 TRIM5 Analog Output

75 TRIM6 Analog Output

74 TRIM7 Analog Output

6

0V to 10V Open-Drain Output 2

12.5µA to 100µA Source
100µA to 3000µA Sink

6

0V to 10V Open-Drain Output 3

12.5µA to 100µA Source
100µA to 3000µA Sink

6

0V to 10V Open-Drain Output 4

12.5µA to 100µA Source
100µA to 3000µA Sink

6

0V to 5.5V

6

0V to 5.5V Open-Drain Output 6

6

0V to 5.5V Open-Drain Output 7

6

0V to 5.5V Open-Drain Output 8

6

0V to 5.5V Open-Drain Output 9

6

0V to 5.5V Open-Drain Output 10

6

0V to 5.5V Open-Drain Output 11

6

0V to 5.5V Open-Drain Output 12

6

0V to 5.5V Open-Drain Output 13

6

0V to 5.5V Open-Drain Output 14

6

0V to 5.5V Open-Drain Output 15

6

0V to 5.5V Open-Drain Output 16

6

0V to 5.5V Open-Drain Output 17

6

0V to 5.5V Open-Drain Output 18

6

0V to 5.5V Open-Drain Output 19

6

0V to 5.5V Open-Drain Output 20

High-voltage FET Gate Driver 2

High-voltage FET Gate Driver 3

High-voltage FET Gate Driver 4

Open-Drain Output 5, (SMBUS Alert Active
Low)

-320mV to +320mV
from Programmable

Trim DAC Output 1

DAC Offset

-320mV to +320mV
from Programmable

Trim DAC Output 2

DAC Offset

-320mV to +320mV
from Programmable

Trim DAC Output 3

DAC Offset

-320mV to +320mV
from Programmable

Trim DAC Output 4

DAC Offset

-320mV to +320mV
from Programmable

Trim DAC Output 5

DAC Offset

-320mV to +320mV
from Programmable

Trim DAC Output 6

DAC Offset

-320mV to +320mV
from Programmable

Trim DAC Output 7

DAC Offset

4

Lattice Semiconductor ispPAC-POWR1220AT8 Data Sheet

Pin Descriptions (Cont.)

Number Name Pin Type Voltage Range Description

73 TRIM8 Analog Output

91 RESETb

9

Digital I/O 0V to 3.96V Device Reset (Active Low)

95 PLDCLK Digital Output 0V to 3.96V

96 MCLK Digital I/O 0V to 3.96V 8MHz Clock I/O (Tristate), CMOS Drive

34 TDO Digital Output 0V to 5.5V JTAG Test Data Out

37 TCK Digital Input 0V to 5.5V JTAG Test Clock Input

28 TMS Digital Input 0V to 5.5V JTAG Test Mode Select

31 TDI Digital Input 0V to 5.5V JTAG Test Data In, TDISEL pin = 1

30 ATDI Digital Input 0V to 5.5V JTAG Test Data In (Alternate), TDISEL Pin = 0

32 TDISEL Digital Input 0V to 5.5V Select TDI/ATDI Input

92 SCL Digital Input 0V to 5.5V I

93 SDA Digital I/O 0V to 5.5V I

44, 59 RESERVED Reserved - Do Not Connect

26, 27, 29,
35, 41, 49,
76, 77, 78,

NC No Internal Connection

81, 99, 100

1. [IN1...IN6] are inputs to the PLD. The thresholds for these pins are referenced by the voltage on VCCINP.

2. IN1 pin can also be controlled through JTAG interface.

3. [IN2..IN6] can also be controlled through I

4. The VMON inputs can be biased independently from VCCA. Unused VMONs should be tied to GNDD.

5. The VMONGS inputs are the ground sense line for each given VMON pin. The VMON input pins along with the VMONGS ground sense
pins implement a differential pair for each voltage monitor to allow remote sense at the load. VMONGS lines must be connected and are
not to exceed -0.2V - +0.3V in reference to the GNDA pin.

6. Open-drain outputs require an external pull-up resistor to a supply.

7. VCCD and VCCA pins must be connected together on the circuit board.

8. GNDA and GNDD pins must be connected together on the circuit board.

9. The RESETb pin should only

be used for cascading two or more ispPAC-POWR1220AT8 devices.

2

C/SMBus interface.

-320mV to +320mV
from Programmable
DAC Offset

Trim DAC Output 8

250kHz PLD Clock Output (Tristate), CMOS
Output

2

C Serial Clock Input

2

C Serial Data, Bi-directional Pin

5

Lattice Semiconductor ispPAC-POWR1220AT8 Data Sheet

Absolute Maximum Ratings

Absolute maximum ratings are shown in the table below. Stresses beyond those listed may cause permanent dam­age to the device. Functional operation of the device at these or any other conditions beyond those indicated in the
recommended operating conditions of this specification is not implied.

Symbol Parameter Conditions Min. Max. Units

V

CCD

V

CCA

V

CCINP

V

CCJ

V

CCPROG

V

IN

V

MON+

V

MONGS

V

TRI

I

SINKMAXTOTAL

T

S

T

A

Core supply -0.5 4.5 V

Analog supply -0.5 4.5 V

Digital input supply (IN[1:6]) -0.5 6 V

JTAG logic supply -0.5 6 V

2

E

programming supply -0.5 4 V

Digital input voltage (all digital I/O pins) -0.5 6 V

V

input voltage -0.5 6 V

MON

V

input voltage ground sense -0.5 6 V

MON

Voltage applied to tri-stated pins

HVOUT[1:4] -0.5 11 V

OUT[5:20] -0.5 6 V

Maximum sink current on any output 23 mA

Storage temperature -65 150

Ambient temperature -65 125

o

C

o

C

Recommended Operating Conditions

Symbol Parameter Conditions Min. Max. Units

V

CCD,

V

CCINP

V

CCJ

V

CCPROG

V

IN

V

MON

V

MONGS

V

CCA

Core supply voltage at pin 2.8 3.96 V

Digital input supply for IN[1:6] at pin 2.25 5.5 V

JTAG logic supply voltage at pin 2.25 3.6 V

E2 programming supply at pin During E2 programming 3.0 3.6 V

Input voltage at digital input pins -0.3 5.5 V

Input voltage at V

Input voltage at V

pins -0.3 5.9 V

MON

pins -0.2 0.3 V

MONGS

OUT[5:20] pins -0.3 5.5 V

V

OUT

T

APROG

T

A

Open-drain output voltage

Ambient temperature during
programming

HVOUT[1:4] pins in open­drain mode

-0.3 10.4 V

-40 85

Ambient temperature Power applied -40 85

Analog Specifications

Symbol Parameter Conditions Min. Typ. Max. Units

1

I

CC

I

CCINP

I

CCJ

I

CCPROG

1. Includes currents on V

Supply current 40 mA

Supply current 5mA

Supply current 1mA

Supply current During programming cycle 40 mA

CCD

and V

CCA

supplies.

o

C

o

C

6

Lattice Semiconductor ispPAC-POWR1220AT8 Data Sheet

Voltage Monitors

Symbol Parameter Conditions Min. Typ. Max. Units

R

IN

C

IN

V

Range Programmable trip-point range 0.075 5.734 V

MON

Sense Near-ground sense threshold 70 75 80 mV

V

Z

Accuracy Absolute accuracy of any trip-point

V

MON

HYST

Input resistance 55 65 75 kΩ

Input capacitance 8 pF

1

Hysteresis of any trip-point (relative to
setting)

0.2 0.7 %

1%

CMR Common mode rejection 60 dB

1. Guaranteed by characterization across V

range, operating temperature, process.

CCA

High Voltage FET Drivers

Symbol Parameter Conditions Min. Typ. Max. Units

10V setting 9.6 10 10.4

V

PP

I

OUTSRC

I

OUTSINK

Gate driver output voltage

Gate driver source current
(HIGH state)

Gate driver sink current
(LOW state)

6V setting 5.8 6 6.2

12.5

Four settings in
software

25

50

100

FAST OFF mode 2000 3000

100

Controlled ramp
settings

250

500

V8V setting 7.7 8 8.3

µA

µA

7

Lattice Semiconductor ispPAC-POWR1220AT8 Data Sheet

Margin/Trim DAC Output Characteristics

Symbol Parameter Conditions Min Typ Max Units

Resolution 8(7+sign) bits

FSR Full scale range +/-320 mV

LSB LSB step size 2.5 mV

I

OUT

BPZ

TS

C_LOAD Maximum load capacitance 50 pF

T

UPDATEM

TOSE

1. To 1% of set value with 50pf load connected to trim pins.

2. Total time required to update a single TRIMx output value by setting the associated DAC through the I2C port.

3. This is the total resultant error in the trimmed power supply output voltage referred to any DAC code due to the DAC’s INL, DNL, gain, out­put impedance, offset error and bipolar offset error across the industrial temperature range and the ispPAC-POWR1200AT8 operating V
and V

CCD

Output source/sink current -200 200 µA

Offset 1 0.6

Bipolar zero output voltage
(code=80h)

Offset 2 0.8

Offset 3 1.0

Offset 4 1.25

DAC code changed

TrimCell output voltage settling

1

time

Update time through I2C port

Total open loop supply voltage

3

error

ranges.

from 80H to FFH or
80H to 00H

Single DAC code
change

2

MCLK = 8MHz 260 µs

256 µs

Full scale DAC corre­sponds to ±5% supply

-1% +1% V/V

voltage variation

2.5 ms

V

CCA

ADC Characteristics

Symbol Parameter Conditions Min. Typ. Max. Units

ADC Resolution 10 Bits

T

CONVERT

V

IN

ADC Step Size LSB

Eattenuator Error Due to Attenuator Programmable Attenuator = 3 +/- 0.1 %

1. Maximum voltage is limited by V

ADC Error Budget Across Entire Operating Temperature Range

Symbol Parameter Conditions Min. Typ. Max. Units

TADC Error

1. Total error, guaranteed by characterization, includes INL, DNL, Gain, Offset, and PSR specs of the ADC.

Conversion Time Time from I2C Request 200 µs

Input range Full Scale

Programmable Attenuator = 1 0 2.048 V

Programmable Attenuator = 3 0 5.9

1

Programmable Attenuator = 1 2 mV

Programmable Attenuator = 3 6 mV

pin (theoretical maximum is 6.144V).

MONX

Total Measurement Error at
Any Voltage

1

Measurement Range 600 mV - 2.048V,
VMONxGS > -100mV, Attenuator =1

Measurement Range 600 mV - 2.048V,
VMONxGS > -200mV, Attenuator =1

Measurement Range 0 - 2.048V,
VMONxGS > -200mV, Attenuator =1

-8 +/-4 8 mV

+/-6 mV

+/-10 mV

V

8

Lattice Semiconductor ispPAC-POWR1220AT8 Data Sheet

Power-On Reset

Symbol Parameter Conditions Min. Typ. Max. Units

T

GOOD

V

TL

V

TH

V

T

T

POR

C

L

1. Corresponds to VCCA and VCCD supply voltages.

Power-on reset to valid VMON comparator
output

Threshold below which RESETb is LOW

Threshold above which RESETb is HIGH

Threshold above which RESETb is valid

Minimum duration dropout required to trigger
RESETb

Capacitive load on RESETb for master/slave
operation

1

1

1

2.5 ms

2.3 V

2.7 V

0.8 V

15µs

200 pF

AC/Transient Characteristics

Over Recommended Operating Conditions

Symbol Parameter Conditions Min. Typ. Max. Units

Voltage Monitors

t

PD16

t

PD64

Propagation delay input to
output glitch filter OFF

Propagation delay input to
output glitch filter ON

Oscillators

f

CLK

f

CLKEXT

f

PLDCLK

Internal master clock
frequency (MCLK)

Externally applied master
clock (MCLK)

PLDCLK output frequency f

Timers

Timeout Range

Resolution

Range of programmable
timers (128 steps)

Spacing between available
adjacent timer intervals

Accuracy Timer accuracy f

7.6 8 8.4 MHz

7.2 8.8 MHz

= 8MHz 250 kHz

CLK

f

= 8MHz 0.032 1966 ms

CLK

= 8MHz -6.67 -12.5 %

CLK

16 µs

64 µs

13 %

9

Lattice Semiconductor ispPAC-POWR1220AT8 Data Sheet

Digital Specifications

Over Recommended Operating Conditions

Symbol Parameter Conditions Min. Typ. Max. Units

I

IL,IIH

I

OH-HVOUT

I

PU

V

IL

V

IH

V

OL

V

OH

I

SINKTOTAL

1. VPS[0:1], SCL, SDA referenced to V

Input leakage, no pull-up/pull-down +/-10 µA

HVOUT[1:4] in open

Output leakage current

drain mode and pulled

35 60 µA

up to 10V

Input pull-up current (TMS, TDI,
TDISEL, ATDI, MCLK)

70 µA

VPS[0:1], TDI, TMS,
ATDI, TDISEL, 3.3V

0.8

supply

Voltage input, logic low

1

VPS[0:1], TDI, TMS,
ATDI, TDISEL, 2.5V

0.7

V

supply

SCL, SDA 30% V

IN[1:6] 30% V

CCD

CCINP

VPS[0:1], TDI, TMS,
ATDI, TDISEL, 3.3V

2.0

supply

Voltage input, logic high

1

VPS[0:1], TDI, TMS,
ATDI, TDISEL, 2.5V

1.7

V

supply

HVOUT[1:4] (open drain mode), I

TDO,MCLK,PLDCLK I

TDO, MCLK, PLDCLK I

SCL, SDA 70% V

IN[1:6] 70% V

= 10mA 0.8

SINK

= 20mA 0.8

SINK

= 4mA 0.4

SINK

= 4mA V

SRC

CCD

CCINP

V

CCD

V

CCINP

- 0.4 V

CCD

VOUT[5:20] I

All digital outputs 130 mA

; IN[1:6] referenced to V

CCD

; TDO, TDI, TMS, ATDI, TDISEL referenced to V

CCINP

CCJ

.

10

Lattice Semiconductor ispPAC-POWR1220AT8 Data Sheet

I2C Port Characteristics

100KHz 400KHz

Symbol Definition

F

I2C

T

SU;STA

T

HD;STA

T

SU;DAT

T

SU;STO

T

HD;DAT

T

LOW

T

HIGH

T

F

T

R

T

TIMEOUT

T

POR

T

BUF

1. If F

is less than 50kHz, then the ADC DONE status bit is not guaranteed to be set after a valid conversion request is completed. In this

I2C

case, waiting for the T
readout. When F

I2C clock/data rate 100

After start 4.7 0.6 us

After start 4 0.6 us

Data setup 250 100 ns

Stop setup 4 0.6 us

Data hold; SCL= Vih_min = 2.1V 0.3 3.45 0.3 0.9 us

Clock low period 4.7 1.3 us

Clock high period 4 0.6 us

Fall time; 2.25V to 0.65V 300 300 ns

Rise time; 0.65V to 2.25V 1000 300 ns

Detect clock low timeout 25 35 25 35 ms

Device must be operational after power-on reset 500 500 ms

Bus free time between stop and start condition 4.7 1.3 us

CONVERT

is greater than 50kHz, ADC conversion complete is ensured by waiting for the DONE status bit.

I2C

minimum time after a convert request is made is the only way to guarantee a valid conversion is ready for

1

400

UnitsMin. Max. Min. Max.

1

KHz

11

Lattice Semiconductor ispPAC-POWR1220AT8 Data Sheet

Timing for JTAG Operations

Symbol Parameter Conditions Min. Typ. Max. Units

t

ISPEN

t

ISPDIS

t

HVDIS

t

HVDIS

t

CEN

t

CDIS

t

SU1

t

H

t

CKH

t

CKL

f

MAX

t

CO

t

PWV

t

PWP

Figure 2. Erase (User Erase or Erase All) Timing Diagram

Program enable delay time 10 — — µs

Program disable delay time 30 — — µs

High voltage discharge time, program 30 — — µs

High voltage discharge time, erase 200 — — µs

Falling edge of TCK to TDO active — — 15 ns

Falling edge of TCK to TDO disable — — 15 ns

Setup time 5 — — ns

Hold time 10 — — ns

TCK clock pulse width, high 20 — — ns

TCK clock pulse width, low 20 — — ns

Maximum TCK clock frequency — — 25 MHz

Falling edge of TCK to valid output — — 15 ns

Verify pulse width 30 — — µs

Programming pulse width 20 — — ms

VIH

TMS

VIL

t

SU1

VIH

TCK

VIL

Update-IR Run-Test/Idle (Erase) Select-DR Scan

State

t

t

SU1

H

t

CKH tGKL

t

H

Figure 3. Programming Timing Diagram

VIH

TMS

VIL

TCK

State

t

SU1

VIH

VIL

Update-IR Run-Test/Idle (Program) Select-DR Scan

t

t

SU1

H

t

t

CKL

CKH

CKH

t

SU1

t

SU2

t

t

SU1

H

t

CKL

t

H

t

CKH

t

H

t

CKH

t

SU1

t

H

t

H

t

CKH

t

SU1

t

PWP

t

t

SU1

Instruction, then clock to the Run-Test/Idle state

Clock to Shift-IR state and shift in the Discharge

t

H

CKH

t

t

SU1

H

t

t

CKH

GKL

Run-Test/Idle (Discharge)

t

SU1

t

H

t

CKH

Specified by the Data Sheet

t

Update-IR

Clock to Shift-IR state and shift in the next

Instruction, which will stop the discharge process

12

Lattice Semiconductor ispPAC-POWR1220AT8 Data Sheet

Figure 4. Verify Timing Diagram

VIH

TMS

VIL

t

H

t

CKH

TCK

VIH

VIL

t

t

SU1

t

H

SU1

t

t

CKH

CKL

t

H

t

SU1

t

PWV

t

H

t

CKH

t

SU1

t

t

H

SU1

t

t

CKH

CKL

State

Update-IR Run-Test/Idle (Program) Select-DR Scan

Update-IR

Clock to Shift-IR state and shift in the next Instruction

Figure 5. Discharge Timing Diagram

t

(Actual)

t

SU1

Clock to Shift-IR state and shift in the Verify

Instruction, then clock to the Run-Test/Idle state

HVDIS

t

t

H

SU1

t

t

CKH

CKL

Run-Test/Idle (Verify)

t

H

t

CKH

Specified by the Data Sheet

t

SU1

t

PWV

Actual

t

PWV

t

H

t

CKH

TMS

TCK

State

VIH

VIL

t

H

VIH

VIL

t

t

SU1

t

H

SU1

t

CKH tCKL

Update-IR Run-Test/Idle (Erase or Program)

t

SU1

t

PWP

t

H

t

CKH

Select-DR Scan

Theory of Operation

Analog Monitor Inputs

The ispPAC-POWR1220AT8 provides 12 independently programmable voltage monitor input circuits as shown in
Figure 6. Two individually programmable trip-point comparators are connected to an analog monitoring input. Each
comparator reference has 368 programmable trip points over the range of 0.664V to 5.734V. Additionally, a 75mV
‘zero-detect’ threshold is selectable which allows the voltage monitors to determine if a monitored signal has
dropped to ground level. This feature is especially useful for determining if a power supply’s output has decayed to
a substantially inactive condition after it has been switched off.

13

Lattice Semiconductor ispPAC-POWR1220AT8 Data Sheet

Figure 6. ispPAC-POWR1220AT8 Voltage Monitors

ispPAC-POWR1220AT8

To ADC

Comp A/Window

Select

Window Control

MUX

Glitch
Filter

Glitch
Filter

Filtering

VMONxA

Logic
Signal

VMONxB

Logic

Signal

VMONx Status

I2C Interface

Unit

PLD

Array

VMONx

VMONxGS

Differential

Input Buffer x

Trip Point A

Trip Point B

Comp A

+

–

Comp B

+

–

Analog Input

Figure 6 shows the functional block diagram of one of the 12 voltage monitor inputs - ‘x’ (where x = 1...12). Each
voltage monitor can be divided into three sections: Analog Input, Window Control, and Filtering. The first section
provides a differential input buffer to monitor the power supply voltage through VMONx+ (to sense the positive ter-
minal of the supply) and VMONxGS (to sense the power supply ground). Differential voltage sensing minimizes
inaccuracies in voltage measurement with ADC and monitor thresholds due to the potential difference between the
ispPAC-POWR1220AT8 device ground and the ground potential at the sensed node on the circuit board.

The voltage output of the differential input buffer is monitored by two individually programmable trip-point compara­tors, shown as CompA and CompB. Table 1 shows all 368 trip points spanning the range 0.664V to 5.734V to
which a comparator’s threshold can be set.

Each comparator outputs a HIGH signal to the PLD array if the voltage at its positive terminal is greater than its pro­grammed trip point setting, otherwise it outputs a LOW signal.

A hysteresis of approximately 1% of the setpoint is provided by the comparators to reduce false triggering as a
result of input noise. The hysteresis provided by the voltage monitor is a function of the input divider setting. Table 3
lists the typical hysteresis versus voltage monitor trip-point.

AGOOD Logic Signal

All the VMON comparators auto-calibrate immediately after a power-on reset event. During this time, the digital
glitch filters are also initialized. This process completion is signalled by an internally generated logic signal:
AGOOD. All logic using the VMON comparator logic signals must wait for the AGOOD signal to become active.

Programmable Over-Voltage and Under-Voltage Thresholds

Figure 7 (a) shows the power supply ramp-up and ramp-down voltage waveforms. Because of hysteresis, the com­parator outputs change state at different thresholds depending on the direction of excursion of the monitored power
supply.

14

Lattice Semiconductor ispPAC-POWR1220AT8 Data Sheet

Figure 7. (a) Power Supply Voltage Ramp-up and Ramp-down Waveform and the Resulting Comparator
Output, (b) Corresponding to Upper and Lower Trip Points

UTP

LTP

(a)

Monitored Power Supply Votlage

(b)

Comparator Logic Output

During power supply ramp-up the comparator output changes from logic 0 to 1 when the power supply voltage
crosses the upper trip point (UTP). During ramp down the comparator output changes from logic state 1 to 0 when
the power supply voltage crosses the lower trip point (LTP). To monitor for over voltage fault conditions, the UTP
should be used. To monitor under-voltage fault conditions, the LTP should be used.

Tables 1 and 2 show both the under-voltage and over-voltage trip points, which are automatically selected in soft­ware depending on whether the user is monitoring for an over-voltage condition or an under-voltage condition.

15

Lattice Semiconductor ispPAC-POWR1220AT8 Data Sheet

Table 1. Trip Point Table Used For Over-Voltage Detection

Fine

Range

Setting

1 0.790 0.941 1.120 1.333 1.580 1.885 2.244 2.665 3.156 3.758 4.818 5.734

2 0.786 0.936 1.114 1.326 1.571 1.874 2.232 2.650 3.139 3.738 4.792 5.703

3 0.782 0.930 1.108 1.319 1.563 1.864 2.220 2.636 3.123 3.718 4.766 5.674

4 0.778 0.926 1.102 1.312 1.554 1.854 2.209 2.622 3.106 3.698 4.741 5.643

5 0.773 0.921 1.096 1.305 1.546 1.844 2.197 2.607 3.089 3.678 4.715 5.612

6 0.769 0.916 1.090 1.298 1.537 1.834 2.185 2.593 3.072 3.657 4.689 5.581

7 0.765 0.911 1.084 1.290 1.529 1.825 2.173 2.579 3.056 3.637 4.663 5.550

8 0.761 0.906 1.078 1.283 1.520 1.815 2.161 2.565 3.039 3.618 4.638 5.520

9 0.756 0.901 1.072 1.276 1.512 1.805 2.149 2.550 3.022 3.598 4.612 5.489

10 0.752 0.896 1.066 1.269 1.503 1.795 2.137 2.536 3.005 3.578 4.586 5.459

11 0.748 0.891 1.060 1.262 1.495 1.785 2.125 2.522 2.988 3.558 4.561 5.428

12 0.744 0.886 1.054 1.255 1.486 1.774 2.113 2.507 2.971 3.537 4.535 5.397

13 0.739 0.881 1.048 1.248 1.478 1.764 2.101 2.493 2.954 3.517 4.509 5.366

14 0.735 0.876 1.042 1.240 1.470 1.754 2.089 2.479 2.937 3.497 4.483 5.336

15 0.731 0.871 1.036 1.233 1.461 1.744 2.077 2.465 2.920 3.477 4.457 5.305

16 0.727 0.866 1.030 1.226 1.453 1.734 2.064 2.450 2.903 3.457 4.431 5.274

17 0.723 0.861 1.024 1.219 1.444 1.724 2.052 2.436 2.886 3.437 4.406 5.244

18 0.718 0.856 1.018 1.212 1.436 1.714 2.040 2.422 2.869 3.416 4.380 5.213

19 0.714 0.851 1.012 1.205 1.427 1.704 2.028 2.407 2.852 3.396 4.355 5.183

20 0.710 0.846 1.006 1.198 1.419 1.694 2.016 2.393 2.836 3.376 4.329 5.152

21 0.706 0.841 1.000 1.190 1.410 1.684 2.004 2.379 2.819 3.356 4.303 5.121

22 0.701 0.836 0.994 1.183 1.402 1.673 1.992 2.365 2.802 3.336 4.277 5.090

23 0.697 0.831 0.988 1.176 1.393 1.663 1.980 2.350 2.785 3.316 4.251 5.059

24 0.693 0.826 0.982 1.169 1.385 1.653 1.968 2.337 2.768 3.296 4.225 5.030

25 0.689 0.821 0.976 1.162 1.376 1.643 1.956 2.323 2.752 3.276 4.199 4.999

26 0.684 0.816 0.970 1.155 1.369 1.633 1.944 2.309 2.735 3.256 4.174 4.968

27 0.680 0.810 0.964 1.148 1.361 1.623 1.932 2.294 2.718 3.236 4.149 4.937

28 0.676 0.805 0.958 1.140 1.352 1.613 1.920 2.280 2.701 3.216 4.123 4.906

29 0.672 0.800 0.952 1.133 1.344 1.603 1.908 2.266 2.684 3.196 4.097 4.876

30 0.668 0.795 0.946 1.126 — 1.593 1.896 2.251 — 3.176 4.071 4.845

Low-V

Sense

123456789101112

Coarse Range Setting

75mV

16

Lattice Semiconductor ispPAC-POWR1220AT8 Data Sheet

Table 2. Trip Point Table Used For Under-Voltage Detection

Fine

Range

Setting

1 0.786 0.936 1.114 1.326 1.571 1.874 2.232 2.650 3.139 3.738 4.792 5.703

2 0.782 0.930 1.108 1.319 1.563 1.864 2.220 2.636 3.123 3.718 4.766 5.674

3 0.778 0.926 1.102 1.312 1.554 1.854 2.209 2.622 3.106 3.698 4.741 5.643

4 0.773 0.921 1.096 1.305 1.546 1.844 2.197 2.607 3.089 3.678 4.715 5.612

5 0.769 0.916 1.090 1.298 1.537 1.834 2.185 2.593 3.072 3.657 4.689 5.581

6 0.765 0.911 1.084 1.290 1.529 1.825 2.173 2.579 3.056 3.637 4.663 5.550

7 0.761 0.906 1.078 1.283 1.520 1.815 2.161 2.565 3.039 3.618 4.638 5.520

8 0.756 0.901 1.072 1.276 1.512 1.805 2.149 2.550 3.022 3.598 4.612 5.489

9 0.752 0.896 1.066 1.269 1.503 1.795 2.137 2.536 3.005 3.578 4.586 5.459

10 0.748 0.891 1.060 1.262 1.495 1.785 2.125 2.522 2.988 3.558 4.561 5.428

11 0.744 0.886 1.054 1.255 1.486 1.774 2.113 2.507 2.971 3.537 4.535 5.397

12 0.739 0.881 1.048 1.248 1.478 1.764 2.101 2.493 2.954 3.517 4.509 5.366

13 0.735 0.876 1.042 1.240 1.470 1.754 2.089 2.479 2.937 3.497 4.483 5.336

14 0.731 0.871 1.036 1.233 1.461 1.744 2.077 2.465 2.920 3.477 4.457 5.305

15 0.727 0.866 1.030 1.226 1.453 1.734 2.064 2.450 2.903 3.457 4.431 5.274

16 0.723 0.861 1.024 1.219 1.444 1.724 2.052 2.436 2.886 3.437 4.406 5.244

17 0.718 0.856 1.018 1.212 1.436 1.714 2.040 2.422 2.869 3.416 4.380 5.213

18 0.714 0.851 1.012 1.205 1.427 1.704 2.028 2.407 2.852 3.396 4.355 5.183

19 0.710 0.846 1.006 1.198 1.419 1.694 2.016 2.393 2.836 3.376 4.329 5.152

20 0.706 0.841 1.000 1.190 1.410 1.684 2.004 2.379 2.819 3.356 4.303 5.121

21 0.701 0.836 0.994 1.183 1.402 1.673 1.992 2.365 2.802 3.336 4.277 5.090

22 0.697 0.831 0.988 1.176 1.393 1.663 1.980 2.350 2.785 3.316 4.251 5.059

23 0.693 0.826 0.982 1.169 1.385 1.653 1.968 2.337 2.768 3.296 4.225 5.030

24 0.689 0.821 0.976 1.162 1.376 1.643 1.956 2.323 2.752 3.276 4.199 4.999

25 0.684 0.816 0.970 1.155 1.369 1.633 1.944 2.309 2.735 3.256 4.174 4.968

26 0.680 0.810 0.964 1.148 1.361 1.623 1.932 2.294 2.718 3.236 4.149 4.937

27 0.676 0.805 0.958 1.140 1.352 1.613 1.920 2.280 2.701 3.216 4.123 4.906

28 0.672 0.800 0.952 1.133 1.344 1.603 1.908 2.266 2.684 3.196 4.097 4.876

29 0.668 0.795 0.946 1.126 1.335 1.593 1.896 2.251 2.667 3.176 4.071 4.845

30 0.664 0.790 0.940 1.119 — 1.583 1.884 2.236 — 3.156 4.045 4.815

Low-V

Sense

123456789101112

Coarse Range Setting

75mV

17