Lattice ispPAC-POWR1014 User Manual

g
g
®
ispPAC-POWR1014/A
Reset Generator and Sequencing Controller
August 2007 Data Sheet DS1014

Features

Monitor and Control Multiple Power Supplies
• Simultaneously monitors up to 10 power supplies
• Provides up to 14 output control signals
• Programmable digital and analog circuitry
Embedded PLD for Sequence Control
• 24-macrocell CPLD implements both state machines and combinatorial logic functions
Embedded Programmable Timers
• Four independent timers
• 32µs to 2 second intervals for timing sequences
Analog Input Monitoring
• 10 independent analog monitor inputs
• Two programmable threshold comparators per analog input
• Hardware window comparison
• 10-bit ADC for I POWR1014A only)
High-Voltage FET Drivers
• Power supply ramp up/down control
• Programmable current and voltage output
• Independently configurable for FET control or digital output
2-Wire (I
2
C/SMBus™ Compatible) Interface
• Comparator status monitor
• ADC readout
• Direct control of inputs and outputs
• Power sequence control
• Only available with ispPAC-POWR1014A
3.3V Operation, Wide Supply Range 2.8V to
3.96V
• In-system programmable through JTAG
• Industrial temperature range: -40°C to +85°C
• 48-pin TQFP package, lead-free option
2
C monitoring (ispPAC-

Application Block Diagram

Primary
Supply
Primary
Supply
Primary
Supply
Primary
Supply
Primary
Supply
*ispPAC-POWR1014A only.
3.3V
2.5V
1.8V
POL#1
POL#N
ADC*
10 Analog Inputs
and Voltage Monitors
ispPAC-POWR1014A
4 Timers
Enables
12 Digital
Outputs
24 Macrocells
4 Digital
Inputs
Other Control/Supervisory
Signals
2 MOSFET
Drivers
CPLD
53 Inputs
2
C
I
Interface
2
I
Bus*
Voltage
C
Other Board Circuitry
Monitoring
ital Monitorin
Di
CPU

Description

Lattice’s Power Manager II ispPAC-POWR1014/A is a general-purpose power-supply monitor and sequence controller, incorporating both in-system programmable logic and in-system programmable analog functions implemented in non-volatile E ispPAC-POWR1014/A device provides 10 independent analog input channels to monitor up to 10 power supply test points. Each of these input channels has two inde­pendently programmable comparators to support both high/low and in-bounds/out-of-bounds (window-com­pare) monitor functions. Four general-purpose digital inputs are also provided for miscellaneous control func­tions.
2
CMOS
®
technology. The
The ispPAC-POWR1014/A provides 14 open-drain digi­tal outputs that can be used for controlling DC-DC con­verters, low-drop-out regulators (LDOs) and opto­couplers, as well as for supervisory and general-pur­pose logic interface functions. Two of these outputs
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
(HVOUT1-HVOUT2) may be configured as high-voltage
1
DS1014_01.5
n
n
Lattice Semiconductor ispPAC-POWR1014/A Data Sheet
MOSFET drivers. In high-voltage mode these outputs can provide up to 10V for driving the gates of n-channel MOSFETs so that they can be used as high-side power switches controlling the supplies with a programmable ramp rate for both ramp up and ramp down.
The ispPAC-POWR1014/A incorporates a 24-macrocell CPLD that can be used to implement complex state machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. The status of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as inputs by the CPLD array, and all digital outputs may be controlled by the CPLD. Four independently programmable timers can create delays and time-outs ranging from 32µs to 2 seconds. The CPLD is programmed using Logi­Builder™, an easy-to-learn language integrated into the PAC-Designer monitor the status of any of the analog input channel comparators or the digital inputs.
The on-chip 10-bit A/D converter is used to monitor the V
MON
POWR1014A device.
2
The I
C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the V
inputs, read back the status of each of the V
comparator and PLD outputs, control logic signals IN2 to IN4 and
MON
control the output pins (ispPAC-POWR1014A only).
®
software. Control sequences are written to
voltage through the I
2
C bus of the ispPAC-
MON
Figure 1. ispPAC-POWR1014/A Block Diagram
ADC*
VMON1 VMON2 VMON3 VMON4 VMON5 VMON6 VMON7 VMON8 VMON9
VMON10
IN1 IN2 IN3 IN4
A N D
V O L T A
E G
N O M I
T O R S
I
N P
T U S
1 0
A N A L O G
I
N P
S T U
4 D I
G I
T A L
VCCINP
VCCA
VCCD (2)
V
C C P R O G
JTAG LOGIC
T
V
T
T
C
D
C
K
O
C
S M
J
TDISEL
T D I
A T D I
MEASUREMENT
CONTROL LOGIC*
CPLD
24 MACROCELLS
53 INPUTS
CLOCK
OSCILLATOR
P
M
L
C L
C D
K
L K
R S E T E
b
TIMERS
(4)
O U T
P U
P
T
O
R
O
O
L
G N I T U
I2C
INTERFACE
SCL (POWR1014A o
SDA (POWR1014A o
GNDA
D R
2
I
V R E
S
G I D T I
L A O
T U P U T S
F T E
1 2
O P E N
-
D R
I A
N
GNDD (2)
HVOUT1 HVOUT2
OUT3/(SMBA*) OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14
*ispPAC-POWR1014A only.
2
Lattice Semiconductor ispPAC-POWR1014/A Data Sheet
Pin Descriptions
Number Name Pin Type Voltage Range Description
44 IN1 Digital Input VCCINP
46 IN2 Digital Input VCCINP
47 IN3 Digital Input VCCINP
48 IN4 Digital Input VCCINP
25 VMON1 Analog Input -0.3V to 5.87V
26 VMON2 Analog Input -0.3V to 5.87V
27 VMON3 Analog Input -0.3V to 5.87V
28 VMON4 Analog Input -0.3V to 5.87V
32 VMON5 Analog Input -0.3V to 5.87V
33 VMON6 Analog Input -0.3V to 5.87V
34 VMON7 Analog Input -0.3V to 5.87V
35 VMON8 Analog Input -0.3V to 5.87V
36 VMON9 Analog Input -0.3V to 5.87V
37 VMON10 Analog Input -0.3V to 5.87V
7, 31 GNDD
30 GNDA
41, 23 VCCD
29 VCCA
5
5
6
6
Ground Ground Digital Ground
Ground Ground Analog Ground
Power 2.8V to 3.96V Core VCC, Main Power Supply
Power 2.8V to 3.96V Analog Power Supply
45 VCCINP Power 2.25V to 5.5V VCC for IN[1:4] Inputs
20 VCCJ Power 2.25V to 3.6V VCC for JTAG Logic Interface Pins
24 VCCPROG Power 3.0V to 3.6V
7
Open Drain Output
15 HVOUT1
Current Source/Sink
Open Drain Output
14 HVOUT2
Current Source/Sink
13 SMBA_OUT3 Open Drain Output
12 OUT4 Open Drain Output
11 OUT5 Open Drain Output
10 OUT6 Open Drain Output
9 OUT7 Open Drain Output
8 OUT8 Open Drain Output
6 OUT9 Open Drain Output
5 OUT10 Open Drain Output
4 OUT11 Open Drain Output
3 OUT12 Open Drain Output
2 OUT13 Open Drain Output
1 OUT14 Open Drain Output
8
40 RESETb
Digital I/O 0V to 3.96V Device Reset (Active Low) - Internal pull-up
0V to 10V Open-Drain Output 1
12.5µA to 100µA Source 100µA to 3000µA Sink
7
0V to 10V Open-Drain Output 2
12.5µA to 100µA Source 100µA to 3000µA Sink
7
0V to 5.5V
7
0V to 5.5V Open-Drain Output 4
7
0V to 5.5V Open-Drain Output 5
7
0V to 5.5V Open-Drain Output 6
7
0V to 5.5V Open-Drain Output 7
7
0V to 5.5V Open-Drain Output 8
7
0V to 5.5V Open-Drain Output 9
7
0V to 5.5V Open-Drain Output 10
7
0V to 5.5V Open-Drain Output 11
7
0V to 5.5V Open-Drain Output 12
7
0V to 5.5V Open-Drain Output 13
7
0V to 5.5V Open-Drain Output 14
42 PLDCLK Digital Output 0V to 3.96V
1
1
1
1
4
4
4
4
4
4
4
4
4
4
PLD Logic Input 1 Registered by MCLK
PLD Logic Input 2 Registered by MCLK
PLD Logic Input 3 Registered by MCLK
PLD Logic Input 4 Registered by MCLK
Voltage Monitor 1 Input
Voltage Monitor 2 Input
Voltage Monitor 3 Input
Voltage Monitor 4 Input
Voltage Monitor 5 Input
Voltage Monitor 6 Input
Voltage Monitor 7 Input
Voltage Monitor 8 Input
Voltage Monitor 9 Input
Voltage Monitor 10 Input
VCC for E Powered by V
2
Programming when the Device is Not
and V
CCD
CCA
High-voltage FET Gate Driver 1
High-voltage FET Gate Driver 2
Open-Drain Output 3, (SMBUS Alert Active Low, ispPAC-POWR1014A only).
250kHz PLD Clock Output (Tristate), CMOS Output - Internal pull-up
3
Lattice Semiconductor ispPAC-POWR1014/A Data Sheet
Pin Descriptions (Cont.)
Number Name Pin Type Voltage Range Description
43 MCLK Digital I/O 0V to 3.96V
21 TDO Digital Output 0V to 5.5V JTAG Test Data Out
22 TCK Digital Input 0V to 5.5V JTAG Test Clock Input
16 TMS Digital Input 0V to 5.5V JTAG Test Mode Select - Internal Pull-up
18 TDI Digital Input 0V to 5.5V
17 ATDI Digital Input 0V to 5.5V
19 TDISEL Digital Input 0V to 5.5V Select TDI/ATDI Input - Internal Pull-up
39 SCL
38 SDA
1. [IN1...IN4] are inputs to the PLD. The thresholds for these pins are referenced by the voltage on VCCINP. Unused INx inputs should be tied to GNDD.
2. IN1 pin can also be controlled through JTAG interface.
3. [IN2..IN4] can also be controlled through I
4. The VMON inputs can be biased independently from VCCA. Unused VMON inputs should be tied to GNDD.
5. GNDA and GNDD pins must be connected together on the circuit board.
6. VCCD and VCCA pins must be connected together on the circuit board.
7. Open-drain outputs require an external pull-up resistor to a supply.
8. The RESETb pin should only
9. These pins should be connected to GNDD (ispPAC-POWR1014 device only).
9
9
Digital Input 0V to 5.5V I
Digital I/O 0V to 5.5V
2
C/SMBus interface (ispPAC-POWR1014A only).
be used for cascading two or more ispPAC-POWR1014/A devices.
8MHz Clock I/O (Tristate), CMOS Drive - Internal Pull-up
JTAG Test Data In, TDISEL pin = 1 - Internal Pull-up
JTAG Test Data In (Alternate), TDISEL Pin = 0 ­Internal Pull-up
2
C Serial Clock Input (ispPAC-POWR1014A Only)
2
I
C Serial Data, Bi-directional Pin, Open Drain
(ispPAC-POWR1014A Only)
4
C
C
Lattice Semiconductor ispPAC-POWR1014/A Data Sheet

Absolute Maximum Ratings

Absolute maximum ratings are shown in the table below. Stresses beyond those listed may cause permanent dam­age to the device. Functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions of this specification is not implied.
Symbol Parameter Conditions Min. Max. Units
V
CCD
V
CCA
V
CCINP
V
CCJ
V
CCPROG
V
IN
V
MON
V
TRI
I
SINKMAXTOTAL
T
S
T
A
Core supply -0.5 4.5 V
Analog supply -0.5 4.5 V
Digital input supply (IN[1:4]) -0.5 6 V
JTAG logic supply -0.5 6 V
2
E
programming supply -0.5 4 V
Digital input voltage (all digital I/O pins) -0.5 6 V
V
input voltage -0.5 6 V
MON
Voltage applied to tri-stated pins
HVOUT[1:2] -0.5 11 V
OUT[3:14] -0.5 6 V
Maximum sink current on any output 23 mA
Storage temperature -65 150
Ambient temperature -65 125
o
C
o

Recommended Operating Conditions

Symbol Parameter Conditions Min. Max. Units
V
CCD,
V
CCINP
V
CCJ
V
CCPROG
V
IN
V
MON
V
CCA
Core supply voltage at pin 2.8 3.96 V
Digital input supply for IN[1:4] at pin 2.25 5.5 V
JTAG logic supply voltage at pin 2.25 3.6 V
2
E
programming supply at pin During E
2
programming 3.0 3.6 V
Input voltage at digital input pins -0.3 5.5 V
Input voltage at V
pins -0.3 5.9 V
MON
OUT[3:14] pins -0.3 5.5 V
V
OUT
T
APROG
T
A
Open-drain output voltage
Ambient temperature during programming
HVOUT[1:2] pins in open­drain mode
-0.3 10.4 V
-40 85
Ambient temperature Power applied -40 85
Analog Specifications
Symbol Parameter Conditions Min. Typ. Max. Units
1
I
CC
I
CCINP
I
CCJ
I
CCPROG
1. Includes currents on V
Supply current 20 mA
Supply current 5mA
Supply current 1mA
Supply current During programming cycle 20 mA
CCD
and V
supplies.
CCA
o
C
o
5
Lattice Semiconductor ispPAC-POWR1014/A Data Sheet

Voltage Monitors

Symbol Parameter Conditions Min. Typ. Max. Units
R
IN
C
IN
V
Range Programmable trip-point range 0.075 5.867 V
MON
V
Sense Near-ground sense threshold 70 75 80 mV
Z
V
Accuracy Absolute accuracy of any trip-point
MON
HYST
1. Guaranteed by characterization across V
Input resistance 55 65 75 k
Input capacitance 8 pF
1
Hysteresis of any trip-point (relative to setting)
range, operating temperature, process.
CCA
0.3 0.9 %
1%
Ω

High Voltage FET Drivers

Symbol Parameter Conditions Min. Typ. Max. Units
10V setting 9.6 10 10.4
V
PP
I
OUTSRC
I
OUTSINK
Gate driver output voltage
Gate driver source current (HIGH state)
Gate driver sink current (LOW state)
6V setting 5.8 6 6.2
12.5
Four settings in software
25
50
100
FAST OFF mode 2000 3000
100
Controlled ramp settings
250
500
V8V setting 7.7 8 8.3
µA
µA
6
Lattice Semiconductor ispPAC-POWR1014/A Data Sheet
ADC Characteristics
1
Symbol Parameter Conditions Min. Typ. Max. Units
ADC resolution 10 Bits
T
CONVERT
V
IN
ADC Step Size LSB
Conversion time Time from I2C request 100 µs
Input range full scale
Programmable attenuator = 1 0 2.048 V
Programmable attenuator = 3 0 5.9
2
Programmable attenuator = 1 2 mV
Programmable attenuator = 3 6 mV
Eattenuator Error due to attenuator Programmable attenuator = 3 +/- 0.1 %
1. ispPAC-POWR1014A only.
2. Maximum voltage is limited by V
ADC Error Budget Across Entire Operating Temperature Range
pin (theoretical maximum is 6.144V).
MONX
1
Symbol Parameter Conditions Min. Typ. Max. Units
TADC Error
1. ispPAC-POWR1014A only.
2. Total error, guaranteed by characterization, includes INL, DNL, Gain, Offset, and PSR specs of the ADC.
Total Measurement Error at Any Voltage
2
Measurement Range 600 mV - 2.048V, Attenuator =1
-8 +/-4 8 mV

Power-On Reset

Symbol Parameter Conditions Min. Typ. Max. Units
T
GOOD
V
TL
V
TH
V
T
T
POR
C
L
1. Corresponds to VCCA and VCCD supply voltages.
Power-on reset to valid VMON comparator output
Threshold below which RESETb is LOW
Threshold above which RESETb is HIGH
Threshold above which RESETb is valid
Minimum duration dropout required to trigger RESETb
Capacitive load on RESETb for master/slave operation
1
1
1
2.7 V
0.8 V
15µs
500 µs
2.3 V
200 pF
V
7
Lattice Semiconductor ispPAC-POWR1014/A Data Sheet

AC/Transient Characteristics

Over Recommended Operating Conditions
Symbol Parameter Conditions Min. Typ. Max. Units
Voltage Monitors
t
PD16
t
PD64
Propagation delay input to output glitch filter OFF
Propagation delay input to output glitch filter ON
Oscillators
f
CLK
f
CLKEXT
f
PLDCLK
Internal master clock frequency (MCLK)
Externally applied master clock (MCLK)
PLDCLK output frequency f
Timers
Timeout Range
Resolution
Range of programmable timers (128 steps)
Spacing between available adjacent timer intervals
Accuracy Timer accuracy f
7.6 8 8.4 MHz
7.2 8.8 MHz
= 8MHz 250 kHz
CLK
= 8MHz 0.032 1966 ms
f
CLK
= 8MHz -6.67 -12.5 %
CLK
16 µs
64 µs
13 %
8
Lattice Semiconductor ispPAC-POWR1014/A Data Sheet
Digital Specifications
Over Recommended Operating Conditions
Symbol Parameter Conditions Min. Typ. Max. Units
I
IL,IIH
I
OH-HVOUT
I
PU
V
IL
V
IH
V
OL
V
OH
I
SINKTOTAL
1. IN[1:4] referenced to V
2. Sum of maximum current sink from all digital outputs combined. Reliable operation is not guaranteed if this value is exceeded.
Input leakage, no pull-up/pull-down +/-10 µA
HVOUT[1:2] in open
Output leakage current
drain mode and pulled
35 60 µA
up to 10V
Input pull-up current (TMS, TDI, TDISEL, ATDI, MCLK, PLDCLK,
70 µA
RESETb)
TDI, TMS, ATDI, TDISEL, 3.3V supply
Voltage input, logic low
1
TDI, TMS, ATDI, TDISEL, 2.5V supply
SCL, SDA 30% V
IN[1:4] 30% V
TDI, TMS, ATDI, TDISEL, 3.3V supply
Voltage input, logic high
1
TDI, TMS, ATDI, TDISEL, 2.5V supply
SCL, SDA 70% V
IN[1:4] 70% V
HVOUT[1:2] (open drain mode), I
TDO,MCLK,PLDCLK I
TDO, MCLK, PLDCLK I
2
All digital outputs 67 mA
; TDO, TDI, TMS, ATDI, TDISEL referenced to V
CCINP
= 10mA 0.8
SINK
= 20mA 0.8
SINK
= 4mA 0.4
SINK
= 4mA V
SRC
CCJ
2.0
1.7
CCD
CCINP
; SCL, SDA referenced to V
CCD.
0.8
0.7
CCD
CCINP
V
CCD
V
CCINP
- 0.4 V
CCD
V
V
VOUT[3:14] I
9
Lattice Semiconductor ispPAC-POWR1014/A Data Sheet
I2C Port Characteristics
1
Symbol Definition
F
I2C
T
SU;STA
T
HD;STA
T
SU;DAT
T
SU;STO
T
HD;DAT
T
LOW
T
HIGH
T
F
T
R
T
TIMEOUT
T
POR
T
BUF
1. Applies to ispPAC-POWR1014A only.
2. If F
is less than 50kHz, then the ADC DONE status bit is not guaranteed to be set after a valid conversion request is completed. In this
I2C
case, waiting for the T readout. When F
I2C clock/data rate 100
After start 4.7 0.6 us
After start 4 0.6 us
Data setup 250 100 ns
Stop setup 4 0.6 us
Data hold; SCL= Vih_min = 2.1V 0.3 3.45 0.3 0.9 us
Clock low period 4.7 10 1.3 10 us
Clock high period 4 0.6 us
Fall time; 2.25V to 0.65V 300 300 ns
Rise time; 0.65V to 2.25V 1000 300 ns
Detect clock low timeout 25 35 25 35 ms
Device must be operational after power-on reset 500 500 ms
Bus free time between stop and start condition 4.7 1.3 us
CONVERT
is greater than 50kHz, ADC conversion complete is ensured by waiting for the DONE status bit.
I2C
minimum time after a convert request is made is the only way to guarantee a valid conversion is ready for
100KHz 400KHz
2
400
UnitsMin. Max. Min. Max.
2
KHz
10
Lattice Semiconductor ispPAC-POWR1014/A Data Sheet

Timing for JTAG Operations

Symbol Parameter Conditions Min. Typ. Max. Units
t
ISPEN
t
ISPDIS
t
HVDIS
t
HVDIS
t
CEN
t
CDIS
t
SU1
t
H
t
CKH
t
CKL
f
MAX
t
CO
t
PWV
t
PWP
Figure 2. Erase (User Erase or Erase All) Timing Diagram
Program enable delay time 10 µs
Program disable delay time 30 µs
High voltage discharge time, program 30 µs
High voltage discharge time, erase 200 µs
Falling edge of TCK to TDO active 10 ns
Falling edge of TCK to TDO disable 10 ns
Setup time 5 ns
Hold time 10 ns
TCK clock pulse width, high 20 ns
TCK clock pulse width, low 20 ns
Maximum TCK clock frequency 25 MHz
Falling edge of TCK to valid output 10 ns
Verify pulse width 30 µs
Programming pulse width 20 ms
VIH
TMS
VIL
t
SU1
VIH
TCK
VIL
Update-IR Run-Test/Idle (Erase) Select-DR Scan
State
t
t
SU1
H
t
CKH tGKL
t
H
Figure 3. Programming Timing Diagram
VIH
TMS
VIL
TCK
State
t
SU1
VIH
VIL
Update-IR Run-Test/Idle (Program) Select-DR Scan
t
t
SU1
H
t
t
CKH
CKL
CKH
t
SU1
t
SU2
t
t
SU1
H
t
CKL
t
H
t
CKH
t
H
t
CKH
t
SU1
t
H
t
H
t
CKH
t
SU1
t
PWP
t
t
SU1
Instruction, then clock to the Run-Test/Idle state
Clock to Shift-IR state and shift in the Discharge
t
H
CKH
t
t
SU1
H
t
t
CKH
GKL
Run-Test/Idle (Discharge)
t
SU1
t
H
t
CKH
Specified by the Data Sheet
t
Update-IR
Clock to Shift-IR state and shift in the next
Instruction, which will stop the discharge process
11
Lattice Semiconductor ispPAC-POWR1014/A Data Sheet
Figure 4. Verify Timing Diagram
VIH
TMS
VIL
t
H
t
CKH
TCK
VIH
t
t
SU1
VIL
t
H
SU1
t
t
CKH
CKL
t
H
t
SU1
t
PWV
t
H
t
CKH
t
SU1
t
t
H
SU1
t
CKH
t
CKL
State
Update-IR Run-Test/Idle (Program) Select-DR Scan
Update-IR
Clock to Shift-IR state and shift in the next Instruction
Figure 5. Discharge Timing Diagram
t
(Actual)
t
SU1
Clock to Shift-IR state and shift in the Verify
Instruction, then clock to the Run-Test/Idle state
HVDIS
t
t
H
SU1
t
t
CKH
CKL
Run-Test/Idle (Verify)
t
H
t
CKH
Specified by the Data Sheet
t
PWV
t
SU1
t
PWV
Actual
t
H
t
CKH
TMS
TCK
State
VIH
VIL
t
H
VIH
VIL
t
t
SU1
t
H
SU1
t
CKH tCKL
Update-IR Run-Test/Idle (Erase or Program)
t
SU1
t
PWP
t
H
t
CKH
Select-DR Scan

Theory of Operation

Analog Monitor Inputs

The ispPAC-POWR1014/A provides 10 independently programmable voltage monitor input circuits as shown in Figure 6. Two individually programmable trip-point comparators are connected to an analog monitoring input. Each comparator reference has 372 programmable trip points over the range of 0.672V to 5.867V. Additionally, a 75mV ‘zero-detect’ threshold is selectable which allows the voltage monitors to determine if a monitored signal has dropped to ground level. This feature is especially useful for determining if a power supply’s output has decayed to a substantially inactive condition after it has been switched off.
12
Lattice Semiconductor ispPAC-POWR1014/A Data Sheet
Figure 6. ispPAC-POWR1014/A Voltage Monitors
ispPAC-POWR1014/A
To ADC (POWR1014A only)
Comp A/Window
Select
MUX
Glitch
Filter
Glitch
Filter
VMONxA
Logic
Signal
VMONxB
Logic
Signal
PLD
Array
VMONx
Trip Point A
Trip Point B
Comp A
+
Comp B
+
Analog Input
Window Control
Filtering
VMONx Status
I2C Interface
Unit (POWR1014A
only)
Figure 6 shows the functional block diagram of one of the 10 voltage monitor inputs - ‘x’ (where x = 1...10). Each voltage monitor can be divided into three sections: Analog Input, Window Control, and Filtering.
The voltage input is monitored by two individually programmable trip-point comparators, shown as CompA and CompB. Table 1 shows all trip points and the range to which any comparator’s threshold can be set.
Each comparator outputs a HIGH signal to the PLD array if the voltage at its positive terminal is greater than its pro­grammed trip point setting, otherwise it outputs a LOW signal.
A hysteresis of approximately 1% of the setpoint is provided by the comparators to reduce false triggering as a result of input noise. The hysteresis provided by the voltage monitor is a function of the input divider setting. Table 3 lists the typical hysteresis versus voltage monitor trip-point.

AGOOD Logic Signal

All the VMON comparators auto-calibrate immediately after a power-on reset event. During this time, the digital glitch filters are also initialized. This process completion is signalled by an internally generated logic signal: AGOOD. All logic using the VMON comparator logic signals must wait for the AGOOD signal to become active.

Programmable Over-Voltage and Under-Voltage Thresholds

Figure 7 (a) shows the power supply ramp-up and ramp-down voltage waveforms. Because of hysteresis, the com­parator outputs change state at different thresholds depending on the direction of excursion of the monitored power supply.
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Lattice Semiconductor ispPAC-POWR1014/A Data Sheet
Figure 7. (a) Power Supply Voltage Ramp-up and Ramp-down Waveform and the Resulting Comparator Output, (b) Corresponding to Upper and Lower Trip Points
UTP
LTP
(a)
Monitored Power Supply Votlage
(b)
Comparator Logic Output
During power supply ramp-up the comparator output changes from logic 0 to 1 when the power supply voltage crosses the upper trip point (UTP). During ramp down the comparator output changes from logic state 1 to 0 when the power supply voltage crosses the lower trip point (LTP). To monitor for over voltage fault conditions, the UTP should be used. To monitor under-voltage fault conditions, the LTP should be used.
Tables 1 and 2 show both the under-voltage and over-voltage trip points, which are automatically selected in soft­ware depending on whether the user is monitoring for an over-voltage condition or an under-voltage condition.
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