• 24-macrocell CPLD implements both state
machines and combinatorial logic functions
Embedded Programmable Timers
• Four independent timers
• 32µs to 2 second intervals for timing sequences
Analog Input Monitoring
• 10 independent analog monitor inputs
• Two programmable threshold comparators per
analog input
• Hardware window comparison
• 10-bit ADC for I
POWR1014A only)
High-Voltage FET Drivers
• Power supply ramp up/down control
• Programmable current and voltage output
• Independently configurable for FET control or
digital output
2-Wire (I
2
C/SMBus™ Compatible) Interface
• Comparator status monitor
• ADC readout
• Direct control of inputs and outputs
• Power sequence control
• Only available with ispPAC-POWR1014A
3.3V Operation, Wide Supply Range 2.8V to
3.96V
• In-system programmable through JTAG
• Industrial temperature range: -40°C to +85°C
• 48-pin TQFP package, lead-free option
2
C monitoring (ispPAC-
Application Block Diagram
Primary
Supply
Primary
Supply
Primary
Supply
Primary
Supply
Primary
Supply
*ispPAC-POWR1014A only.
3.3V
2.5V
1.8V
POL#1
POL#N
ADC*
10 Analog Inputs
and Voltage Monitors
ispPAC-POWR1014A
4 Timers
Enables
12 Digital
Outputs
24 Macrocells
4 Digital
Inputs
Other Control/Supervisory
Signals
2 MOSFET
Drivers
CPLD
53 Inputs
2
C
I
Interface
2
I
Bus*
Voltage
C
Other Board Circuitry
Monitoring
ital Monitorin
Di
CPU
Description
Lattice’s Power Manager II ispPAC-POWR1014/A is a
general-purpose power-supply monitor and sequence
controller, incorporating both in-system programmable
logic and in-system programmable analog functions
implemented in non-volatile E
ispPAC-POWR1014/A device provides 10 independent
analog input channels to monitor up to 10 power supply
test points. Each of these input channels has two independently programmable comparators to support both
high/low and in-bounds/out-of-bounds (window-compare) monitor functions. Four general-purpose digital
inputs are also provided for miscellaneous control functions.
2
CMOS
®
technology. The
The ispPAC-POWR1014/A provides 14 open-drain digital outputs that can be used for controlling DC-DC converters, low-drop-out regulators (LDOs) and optocouplers, as well as for supervisory and general-purpose logic interface functions. Two of these outputs
MOSFET drivers. In high-voltage mode these outputs can provide up to 10V for driving the gates of n-channel
MOSFETs so that they can be used as high-side power switches controlling the supplies with a programmable
ramp rate for both ramp up and ramp down.
The ispPAC-POWR1014/A incorporates a 24-macrocell CPLD that can be used to implement complex state
machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. The status
of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as
inputs by the CPLD array, and all digital outputs may be controlled by the CPLD. Four independently programmable
timers can create delays and time-outs ranging from 32µs to 2 seconds. The CPLD is programmed using LogiBuilder™, an easy-to-learn language integrated into the PAC-Designer
monitor the status of any of the analog input channel comparators or the digital inputs.
The on-chip 10-bit A/D converter is used to monitor the V
MON
POWR1014A device.
2
The I
C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the V
inputs, read back the status of each of the V
comparator and PLD outputs, control logic signals IN2 to IN4 and
JTAG Test Data In, TDISEL pin = 1 - Internal
Pull-up
JTAG Test Data In (Alternate), TDISEL Pin = 0 Internal Pull-up
2
C Serial Clock Input (ispPAC-POWR1014A Only)
2
I
C Serial Data, Bi-directional Pin, Open Drain
(ispPAC-POWR1014A Only)
4
C
C
Lattice SemiconductorispPAC-POWR1014/A Data Sheet
Absolute Maximum Ratings
Absolute maximum ratings are shown in the table below. Stresses beyond those listed may cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the
recommended operating conditions of this specification is not implied.
SymbolParameterConditionsMin.Max.Units
V
CCD
V
CCA
V
CCINP
V
CCJ
V
CCPROG
V
IN
V
MON
V
TRI
I
SINKMAXTOTAL
T
S
T
A
Core supply-0.54.5V
Analog supply-0.54.5V
Digital input supply (IN[1:4])-0.56V
JTAG logic supply-0.56V
2
E
programming supply-0.54V
Digital input voltage (all digital I/O pins)-0.56V
V
input voltage-0.56V
MON
Voltage applied to tri-stated pins
HVOUT[1:2]-0.511V
OUT[3:14]-0.56V
Maximum sink current on any output23mA
Storage temperature-65150
Ambient temperature-65125
o
C
o
Recommended Operating Conditions
SymbolParameterConditionsMin.Max.Units
V
CCD,
V
CCINP
V
CCJ
V
CCPROG
V
IN
V
MON
V
CCA
Core supply voltage at pin2.83.96V
Digital input supply for IN[1:4] at pin2.255.5V
JTAG logic supply voltage at pin2.253.6V
2
E
programming supply at pinDuring E
2
programming3.03.6V
Input voltage at digital input pins-0.35.5V
Input voltage at V
pins-0.35.9V
MON
OUT[3:14] pins-0.35.5V
V
OUT
T
APROG
T
A
Open-drain output voltage
Ambient temperature during
programming
HVOUT[1:2] pins in opendrain mode
-0.310.4V
-4085
Ambient temperaturePower applied-4085
Analog Specifications
SymbolParameterConditionsMin.Typ.Max.Units
1
I
CC
I
CCINP
I
CCJ
I
CCPROG
1. Includes currents on V
Supply current20mA
Supply current5mA
Supply current1mA
Supply currentDuring programming cycle20mA
CCD
and V
supplies.
CCA
o
C
o
5
Lattice SemiconductorispPAC-POWR1014/A Data Sheet
Voltage Monitors
SymbolParameterConditionsMin.Typ.Max.Units
R
IN
C
IN
V
RangeProgrammable trip-point range0.0755.867V
MON
V
SenseNear-ground sense threshold707580mV
Z
V
AccuracyAbsolute accuracy of any trip-point
MON
HYST
1. Guaranteed by characterization across V
Input resistance556575k
Input capacitance8pF
1
Hysteresis of any trip-point (relative to
setting)
range, operating temperature, process.
CCA
0.30.9%
1%
Ω
High Voltage FET Drivers
SymbolParameterConditionsMin.Typ.Max.Units
10V setting9.61010.4
V
PP
I
OUTSRC
I
OUTSINK
Gate driver output voltage
Gate driver source current
(HIGH state)
Gate driver sink current
(LOW state)
6V setting5.866.2
12.5
Four settings in software
25
50
100
FAST OFF mode20003000
100
Controlled ramp settings
250
500
V8V setting7.788.3
µA
µA
6
Lattice SemiconductorispPAC-POWR1014/A Data Sheet
ADC Characteristics
1
SymbolParameterConditionsMin.Typ.Max.Units
ADC resolution 10 Bits
T
CONVERT
V
IN
ADC Step Size LSB
Conversion timeTime from I2C request100µs
Input range full scale
Programmable attenuator = 102.048V
Programmable attenuator = 305.9
2
Programmable attenuator = 12mV
Programmable attenuator = 36mV
EattenuatorError due to attenuatorProgrammable attenuator = 3+/- 0.1%
1. ispPAC-POWR1014A only.
2. Maximum voltage is limited by V
ADC Error Budget Across Entire Operating Temperature Range
pin (theoretical maximum is 6.144V).
MONX
1
SymbolParameterConditionsMin.Typ.Max.Units
TADC Error
1. ispPAC-POWR1014A only.
2. Total error, guaranteed by characterization, includes INL, DNL, Gain, Offset, and PSR specs of the ADC.
Total Measurement Error at
Any Voltage
2
Measurement Range 600 mV - 2.048V,
Attenuator =1
-8+/-48mV
Power-On Reset
SymbolParameterConditionsMin.Typ.Max.Units
T
GOOD
V
TL
V
TH
V
T
T
POR
C
L
1. Corresponds to VCCA and VCCD supply voltages.
Power-on reset to valid VMON comparator
output
Threshold below which RESETb is LOW
Threshold above which RESETb is HIGH
Threshold above which RESETb is valid
Minimum duration dropout required to trigger
RESETb
Capacitive load on RESETb for master/slave
operation
1
1
1
2.7V
0.8V
15µs
500µs
2.3V
200pF
V
7
Lattice SemiconductorispPAC-POWR1014/A Data Sheet
AC/Transient Characteristics
Over Recommended Operating Conditions
SymbolParameterConditionsMin.Typ.Max.Units
Voltage Monitors
t
PD16
t
PD64
Propagation delay input to
output glitch filter OFF
Propagation delay input to
output glitch filter ON
Oscillators
f
CLK
f
CLKEXT
f
PLDCLK
Internal master clock
frequency (MCLK)
Externally applied master
clock (MCLK)
PLDCLK output frequencyf
Timers
Timeout Range
Resolution
Range of programmable
timers (128 steps)
Spacing between available
adjacent timer intervals
AccuracyTimer accuracyf
7.688.4MHz
7.28.8MHz
= 8MHz250kHz
CLK
= 8MHz0.0321966ms
f
CLK
= 8MHz-6.67-12.5%
CLK
16µs
64µs
13%
8
Lattice SemiconductorispPAC-POWR1014/A Data Sheet
Digital Specifications
Over Recommended Operating Conditions
SymbolParameterConditionsMin.Typ.Max.Units
I
IL,IIH
I
OH-HVOUT
I
PU
V
IL
V
IH
V
OL
V
OH
I
SINKTOTAL
1. IN[1:4] referenced to V
2. Sum of maximum current sink from all digital outputs combined. Reliable operation is not guaranteed if this value is exceeded.
Input leakage, no pull-up/pull-down+/-10µA
HVOUT[1:2] in open
Output leakage current
drain mode and pulled
3560µA
up to 10V
Input pull-up current (TMS, TDI,
TDISEL, ATDI, MCLK, PLDCLK,
70µA
RESETb)
TDI, TMS, ATDI,
TDISEL, 3.3V supply
Voltage input, logic low
1
TDI, TMS, ATDI,
TDISEL, 2.5V supply
SCL, SDA30% V
IN[1:4]30% V
TDI, TMS, ATDI,
TDISEL, 3.3V supply
Voltage input, logic high
1
TDI, TMS, ATDI,
TDISEL, 2.5V supply
SCL, SDA70% V
IN[1:4]70% V
HVOUT[1:2] (open drain mode), I
TDO,MCLK,PLDCLKI
TDO, MCLK, PLDCLKI
2
All digital outputs67mA
; TDO, TDI, TMS, ATDI, TDISEL referenced to V
CCINP
= 10mA0.8
SINK
= 20mA0.8
SINK
= 4mA0.4
SINK
= 4mAV
SRC
CCJ
2.0
1.7
CCD
CCINP
; SCL, SDA referenced to V
CCD.
0.8
0.7
CCD
CCINP
V
CCD
V
CCINP
- 0.4V
CCD
V
V
VOUT[3:14]I
9
Lattice SemiconductorispPAC-POWR1014/A Data Sheet
I2C Port Characteristics
1
SymbolDefinition
F
I2C
T
SU;STA
T
HD;STA
T
SU;DAT
T
SU;STO
T
HD;DAT
T
LOW
T
HIGH
T
F
T
R
T
TIMEOUT
T
POR
T
BUF
1. Applies to ispPAC-POWR1014A only.
2. If F
is less than 50kHz, then the ADC DONE status bit is not guaranteed to be set after a valid conversion request is completed. In this
I2C
case, waiting for the T
readout. When F
I2C clock/data rate100
After start4.70.6us
After start40.6us
Data setup250100ns
Stop setup40.6us
Data hold; SCL= Vih_min = 2.1V0.33.450.30.9us
Clock low period4.7101.310us
Clock high period40.6us
Fall time; 2.25V to 0.65V300300ns
Rise time; 0.65V to 2.25V1000300ns
Detect clock low timeout25352535ms
Device must be operational after power-on reset500500ms
Bus free time between stop and start condition4.71.3us
CONVERT
is greater than 50kHz, ADC conversion complete is ensured by waiting for the DONE status bit.
I2C
minimum time after a convert request is made is the only way to guarantee a valid conversion is ready for
100KHz400KHz
2
400
UnitsMin.Max.Min.Max.
2
KHz
10
Lattice SemiconductorispPAC-POWR1014/A Data Sheet
Timing for JTAG Operations
SymbolParameterConditionsMin.Typ.Max.Units
t
ISPEN
t
ISPDIS
t
HVDIS
t
HVDIS
t
CEN
t
CDIS
t
SU1
t
H
t
CKH
t
CKL
f
MAX
t
CO
t
PWV
t
PWP
Figure 2. Erase (User Erase or Erase All) Timing Diagram
Program enable delay time10——µs
Program disable delay time30——µs
High voltage discharge time, program30——µs
High voltage discharge time, erase200——µs
Falling edge of TCK to TDO active——10ns
Falling edge of TCK to TDO disable——10ns
Setup time5——ns
Hold time10——ns
TCK clock pulse width, high20——ns
TCK clock pulse width, low20——ns
Maximum TCK clock frequency——25MHz
Falling edge of TCK to valid output——10ns
Verify pulse width30——µs
Programming pulse width20——ms
VIH
TMS
VIL
t
SU1
VIH
TCK
VIL
Update-IR Run-Test/Idle (Erase) Select-DR Scan
State
t
t
SU1
H
t
CKH tGKL
t
H
Figure 3. Programming Timing Diagram
VIH
TMS
VIL
TCK
State
t
SU1
VIH
VIL
Update-IRRun-Test/Idle (Program)Select-DR Scan
t
t
SU1
H
t
t
CKH
CKL
CKH
t
SU1
t
SU2
t
t
SU1
H
t
CKL
t
H
t
CKH
t
H
t
CKH
t
SU1
t
H
t
H
t
CKH
t
SU1
t
PWP
t
t
SU1
Instruction, then clock to the Run-Test/Idle state
Clock to Shift-IR state and shift in the Discharge
t
H
CKH
t
t
SU1
H
t
t
CKH
GKL
Run-Test/Idle (Discharge)
t
SU1
t
H
t
CKH
Specified by the Data Sheet
t
Update-IR
Clock to Shift-IR state and shift in the next
Instruction, which will stop the discharge process
11
Lattice SemiconductorispPAC-POWR1014/A Data Sheet
Figure 4. Verify Timing Diagram
VIH
TMS
VIL
t
H
t
CKH
TCK
VIH
t
t
SU1
VIL
t
H
SU1
t
t
CKH
CKL
t
H
t
SU1
t
PWV
t
H
t
CKH
t
SU1
t
t
H
SU1
t
CKH
t
CKL
State
Update-IRRun-Test/Idle (Program)Select-DR Scan
Update-IR
Clock to Shift-IR state and shift in the next Instruction
Figure 5. Discharge Timing Diagram
t
(Actual)
t
SU1
Clock to Shift-IR state and shift in the Verify
Instruction, then clock to the Run-Test/Idle state
HVDIS
t
t
H
SU1
t
t
CKH
CKL
Run-Test/Idle (Verify)
t
H
t
CKH
Specified by the Data Sheet
t
PWV
t
SU1
t
PWV
Actual
t
H
t
CKH
TMS
TCK
State
VIH
VIL
t
H
VIH
VIL
t
t
SU1
t
H
SU1
t
CKH tCKL
Update-IR Run-Test/Idle (Erase or Program)
t
SU1
t
PWP
t
H
t
CKH
Select-DR Scan
Theory of Operation
Analog Monitor Inputs
The ispPAC-POWR1014/A provides 10 independently programmable voltage monitor input circuits as shown in
Figure 6. Two individually programmable trip-point comparators are connected to an analog monitoring input. Each
comparator reference has 372 programmable trip points over the range of 0.672V to 5.867V. Additionally, a 75mV
‘zero-detect’ threshold is selectable which allows the voltage monitors to determine if a monitored signal has
dropped to ground level. This feature is especially useful for determining if a power supply’s output has decayed to
a substantially inactive condition after it has been switched off.
12
Lattice SemiconductorispPAC-POWR1014/A Data Sheet
Figure 6. ispPAC-POWR1014/A Voltage Monitors
ispPAC-POWR1014/A
To ADC
(POWR1014A only)
Comp A/Window
Select
MUX
Glitch
Filter
Glitch
Filter
VMONxA
Logic
Signal
VMONxB
Logic
Signal
PLD
Array
VMONx
Trip Point A
Trip Point B
Comp A
+
–
Comp B
+
–
Analog Input
Window Control
Filtering
VMONx Status
I2C Interface
Unit (POWR1014A
only)
Figure 6 shows the functional block diagram of one of the 10 voltage monitor inputs - ‘x’ (where x = 1...10). Each
voltage monitor can be divided into three sections: Analog Input, Window Control, and Filtering.
The voltage input is monitored by two individually programmable trip-point comparators, shown as CompA and
CompB. Table 1 shows all trip points and the range to which any comparator’s threshold can be set.
Each comparator outputs a HIGH signal to the PLD array if the voltage at its positive terminal is greater than its programmed trip point setting, otherwise it outputs a LOW signal.
A hysteresis of approximately 1% of the setpoint is provided by the comparators to reduce false triggering as a
result of input noise. The hysteresis provided by the voltage monitor is a function of the input divider setting. Table 3
lists the typical hysteresis versus voltage monitor trip-point.
AGOOD Logic Signal
All the VMON comparators auto-calibrate immediately after a power-on reset event. During this time, the digital
glitch filters are also initialized. This process completion is signalled by an internally generated logic signal:
AGOOD. All logic using the VMON comparator logic signals must wait for the AGOOD signal to become active.
Programmable Over-Voltage and Under-Voltage Thresholds
Figure 7 (a) shows the power supply ramp-up and ramp-down voltage waveforms. Because of hysteresis, the comparator outputs change state at different thresholds depending on the direction of excursion of the monitored power
supply.
13
Lattice SemiconductorispPAC-POWR1014/A Data Sheet
Figure 7. (a) Power Supply Voltage Ramp-up and Ramp-down Waveform and the Resulting Comparator
Output, (b) Corresponding to Upper and Lower Trip Points
UTP
LTP
(a)
Monitored Power Supply Votlage
(b)
Comparator Logic Output
During power supply ramp-up the comparator output changes from logic 0 to 1 when the power supply voltage
crosses the upper trip point (UTP). During ramp down the comparator output changes from logic state 1 to 0 when
the power supply voltage crosses the lower trip point (LTP). To monitor for over voltage fault conditions, the UTP
should be used. To monitor under-voltage fault conditions, the LTP should be used.
Tables 1 and 2 show both the under-voltage and over-voltage trip points, which are automatically selected in software depending on whether the user is monitoring for an over-voltage condition or an under-voltage condition.
14
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