Lattice ispPAC-CLK5620A-EV1 User Manual

ispClock5620A Evaluation Board:

ispPAC-CLK5620A-EV1

March 2007 Application Note AN6072

Introduction

The Lattice Semiconductor ispClock™5620A In-System-Programmable Analog Circuit allows designers to imple­ment clock distribution networks supporting multiple, synchronized output frequencies using a single integrated cir­cuit.

By integrating a Phase-Locked Loop (PLL) along with multiple output dividers, the ispClock5620A can derive up to
five separate output frequencies from a single input reference frequency. To facilitate the implementation of wide­fanout clock trees, the ispClock5620A provides up to 20 single-ended outputs or 10 differential outputs, organized
as ten banks of two. Each output bank may be independently programmed to support different logic standards and
operating options. Additionally, each single-ended output or differential output may be skew-adjusted to compen­sate for the effects of propagation delay along the PCB traces used in the distribution network. All configuration
data is stored internally in E
an industry-standard JTAG IEEE 1149.1 interface.

2

CMOS

®

non-volatile memory. Programming a configuration is accomplished through

Figure 1. ispPAC-CLK5620A-EV1 Evaluation Board

ispPAC-CLK5620A-EV1 Evaluation Board

The ispPAC-CLK5620A-EV1 evaluation board (Figure 1) allows the designer to quickly configure and evaluate the
ispClock5620A on a fully assembled printed-circuit board. The four-layer board supports a 100-pin TQFP package,

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an6072_01.1

ispClock5620A Evaluation Board:

Lattice Semiconductor ispPAC-CLK5620A-EV1

a header for user I/O and a JTAG programming cable connector. SMA connectors are installed to provide high-sig­nal integrity access to selected high-speed I/O signals. JTAG programming signals can be generated by using an
ispDOWNLOAD
user-programmable features of the ispPAC-CLK5620A can be easily configured using Lattice Semiconductor’s
PAC-Designer

®

programming cable connected between the evaluation board and a PC’s parallel (printer) port. All

®

software.

Programming Interface

Lattice Semiconductor’s ispDOWNLOAD cable can be used to program the ispClock5620A which is provided on
the evaluation board. This cable plugs into a PC-compatible’s parallel port connector, and includes active buffer cir­cuitry inside its DB-25 connector housing. The other end of the ispDOWNLOAD cable terminates in an 8-pin 0.100”
pitch header connector which plugs directly into a mating connector provided on the ispPAC-CLK5620A-EV1 eval­uation board.

Power Supply Considerations

The ispClock5620A operates with analog and digital core power supplies of 3.3V, while each output driver has a
dedicated power supply pin which may be driven with supply voltage of 1.5V, 1.8V, 2.5V or 3.3V, depending on the
logic standard which it has been configured to drive.

To simplify evaluation work, the ispPAC-CLK5620A-EV1 board was designed to operate from a single 4.5V-5.5V
power supply, which may be brought in through either a pair of banana plugs (J2 and J3), or a standard 5mm power
plug (J1 - center tip positive). The evaluation board provides two linear regulators to provide the appropriate operat­ing voltages for the ispClock5620A. One of these regulators provides a fixed 3.3V for the analog and core func­tions, while the other regulator is dipswitch-programmable to provide 1.5V, 1.8V, 2.5V and 3.3V to power the
BANK8 and BANK9 output drivers.

Input/Output Connections

Connectors are provided for key functions and test points on this evaluation board, as shown In Figure 2. Power
may be supplied in one of two ways; either through two color coded (RED = +, BLACK = -) banana jacks in the
upper right corner of the board or through a 5mm (center pin +) DC power connector (J1), The JTAG programming
cable is connected to a keyed header (J4) in the upper right corner of the board.

Access to a subset of the ispClock5620A’s I/O pins is available at J5, which is a 2x17 row of pads to which one may
attach test probes or a ribbon-cable connector. At this point most of the device’s non-RF control pins (except those
required for the JTAG programming interface) are accessible.

SMA connectors are provided along the left and right edges of the board to support access to key high-speed I/O
pins. Pairs of connectors are provided for the BANK8 and BANK9 outputs (J10-J13). Additional pairs of connectors
are provided for REFA(+/-) clock reference inputs (J8, J9) and FBKA (+, -) external feedback inputs (J6, J7). On this
evaluation board design the REFB(+/-) clock inputs are dedicated to supporting an on-board crystal oscillator.
Because this board was designed to maintain high levels of signal integrity at the edge rates at which the
ispClock5620A operates, it is strongly suggested that the user do not attempt to access any of the device’s high­speed I/O except through the provided SMA connectors and supporting impedance-controlled printed-circuit
traces.

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ispClock5620A Evaluation Board:

Lattice Semiconductor ispPAC-CLK5620A-EV1

Figure 2. I/O Connections, Controls and Indicators

Controls and Indicators

A 12-position dipswitch (S2) is provided on the evaluation board (Figure 2) for the purpose of setting device inputs
and programming the VCCO power supply for the BANK8 and BANK9 outputs. The following table shows the
options controlled by each switch:

Table 1. User Configuration Functions

Position Function (when ON)

1 PLL_BYPASS

2 PS0

3 PS1

4 GOE

5 SGATE

6 REFSEL

7 OEX

8 OEY

9 OSC DIS

10

BANK8 and BANK9 VCCO Programming11

12

Each of the switch positions used to control logic inputs (positions 1-8) pulls its respective control signal HIGH
when it is turned on. Each of these switch outputs is connected to the device through a 1K Ω resistor. This feature
allows external CMOS logic control signals applied to the J5 header connector to over-ride the on-board switch set­tlings.