Lattice ispLSI 2096VE User Manual

Lead-

Free

Package

Options

Available!

ispLSI® 2096VE

3.3V In-System Programmable

SuperFAST™ High Density PLD

Features

• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC
— 4000 PLD Gates
— 96 I/O Pins, Six Dedicated Inputs
— 96 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible

with ispLSI 2096V Devices
— Pinout Compatible with ispLSI 2192VE

• 3.3V LOW VOLTAGE 2096 ARCHITECTURE
— Interfaces with Standard 5V TTL Devices

2

• HIGH PERFORMANCE E
—

fmax = 250MHz Maximum Operating Frequency

— tpd = 4.0ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP™) Using

Boundary Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global

Interconnectivity

• LEAD-FREE PACKAGE OPTIONS

CMOS® TECHNOLOGY

Functional Block Diagram

Output Routing Pool (ORP)

6

C7

C

A0

A1

GLB

A2

Output Routing Pool (ORP)

A3

A4

A5

Output Routing Pool (ORP)

Logic
Array

C4

C5

DQ

DQ

DQ

DQ

A7

A6

Output Routing Pool (ORP)

C3

Global Routing Pool

(GRP)

B0

Output Routing Pool (ORP)

C1

C2

B2

B1

C0

B7

B6

B5

Output Routing Pool (ORP)

B4

B3

0919/2096VE

Description

The ispLSI 2096VE is a High Density Programmable
Logic Device containing 96 Registers, six Dedicated
Input pins, three Dedicated Clock Input pins, two dedi­cated Global OE input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 2096VE
features in-system programmability through the Bound­ary Scan Test Access Port (TAP) and is 100% IEEE

1149.1 Boundary Scan Testable. The ispLSI 2096VE
offers non-volatile reprogrammability of the logic, as well
as the interconnect to provide truly reconfigurable sys­tems.

The basic unit of logic on the ispLSI 2096VE device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. C7 (see Figure 1). There are a total of 24 GLBs in the
ispLSI 2096VE device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.

The devices also have 96 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can

Copyright © 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2004
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

2096ve_08 1

Functional Block Diagram

Figure 1. ispLSI 2096VE Functional Block Diagram

I/O 95

I/O 94

I/O 93

GOE 0

GOE 1

I/O 92

I/O 91

I/O 90

I/O 89

I/O 88

I/O 87

I/O 86

I/O 85

I/O 84

I/O 83

I/O 82

Specifications ispLSI 2096VE

I/O 81

I/O 80

I/O 79

I/O 78

I/O 77

I/O 76

I/O 75

I/O 74

I/O 73

I/O 72

I/O 71

I/O 70

I/O 69

I/O 68

I/O 67

I/O 66

I/O 65

I/O 64

IN 5

IN 4

Input Bus

Output Routing Pool (ORP)

A5

I/O 20

I/O 21

Input Bus

I/O 22

I/O 23

C6

A6

I/O 24

I/O 25

C7

Output Routing Pool (ORP)

I/O 18

I/O 19

I/O 26

I/O 27

C5

I/O 28

A7

I/O 29

I/O 30

C4

Routing

I/O 31

I/O 0
I/O 1
I/O 2
I/O 3

I/O 4
I/O 5
I/O 6
I/O 7

I/O 8

I/O 9
I/O 10
I/O 11

I/O 12
I/O 13
I/O 14
I/O 15

TDI/IN 0

TMS/IN 1

RESET

BSCAN

egablock

M

eneric Logic

G
Blocks (GLBs)

A0

A1

Input Bus

A2

Output Routing Pool (ORP)

A3

A4

I/O 16

I/O 17

be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Device pins can be safely driven to 5V signal levels to
support mixed-voltage systems.

Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2096VE device contains three Megablocks.

The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.

Input Bus

Output Routing Pool (ORP)

C3

C2

C1

C0

B7

Global

B6

Pool

(GRP)

TCK/IN 3

TDO/IN 2

B0

I/O 32

B1

Output Routing Pool (ORP)

I/O 33

I/O 34

I/O 35

I/O 36

I/O 37

I/O 38

Input Bus

I/O 39

I/O 40

B2

I/O 41

I/O 42

I/O 43

I/O 44

B3

I/O 45

I/O 46

B5

B4

CLK 0

I/O 47

Input Bus

Output Routing Pool (ORP)

CLK 1

CLK 2

0917/2096VE

Y0Y1Y2

Programmable Open-Drain Outputs

In addition to the standard output configuration, the
outputs of the ispLSI 2096VE are individually program­mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro­grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispLEVER software tools.

I/O 63
I/O 62
I/O 61
I/O 60

I/O 59
I/O 58
I/O 57
I/O 56

I/O 55
I/O 54
I/O 53
I/O 52

I/O 51
I/O 50
I/O 49
I/O 48

Clocks in the ispLSI 2096VE device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock can
be generated in any GLB for its own clock.

2

Specifications ispLSI 2096VE

Absolute Maximum Ratings

1

Supply Voltage Vcc.................................. -0.5 to +5.4V

Input Voltage Applied............................... -0.5 to +5.6V

Off-State Output Voltage Applied ............ -0.5 to +5.6V

Storage Temperature................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (TJ) with Power Applied ... 150°C

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Condition

V
V

V

CC

IL
IH

SYMBOL

Supply Voltage

Input Low Voltage
Input High Voltage

PARAMETER

Commercial
Industrial

TA = 0°C to + 70°C

= -40°C to + 85°C

T

A

MIN. MAX. UNITS

3.0

3.0

V – 0.5

SS

2.0

3.6

3.6

0.8

5.25

Table 2-0005/2096VE

V
V
V
V

Capacitance (TA=25°C, f=1.0 MHz)

SYMBOL

C

1

C

2

C

3

I/O Capacitance
Clock and Global Output Enable Capacitance

PARAMETER

Erase Reprogram Specifications

PARAMETER MINIMUM MAXIMUM UNITS

Erase/Reprogram Cycles

UNITSTYPICAL TEST CONDITIONS

8Dedicated Input Capacitance
6

10

10000 – Cycles

pf
pf
pf V = 3.3V, V = 0.0V

V = 3.3V, V = 0.0V

CC

V = 3.3V, V = 0.0V

CC I/O

CC Y

IN

Table 2-0006/2096VE

Table 2-0008/2096VE

3

Switching Test Conditions

Specifications ispLSI 2096VE

Input Pulse Levels
Input Rise and Fall Time

Input Timing Reference Levels
Output Timing Reference Levels
Output Load

3-state levels are measured 0.5V from

GND to 3.0V

≤ 1.5ns 10% to 90%

1.5V

1.5V

See Figure 2

Table 2-0003/2096VE

Figure 2. Test Load

Device
Output

+ 3.3V

R

1

Test

Point

steady-state active level.

R

2

C

*

L

Output Load Conditions (see Figure 2)

TEST CONDITION R1 R2 CL

A 316Ω 348Ω 35pF

Active High

B

Active Low
Active High to Z

at V -0.5V

C

Active Low to Z
at V +0.5V

OH

OL

∞ 348Ω 35pF

316Ω 348Ω 35pF

∞ 348Ω 5pF

316Ω 348Ω 5pF

Table 2-0004/2096VE

*C

includes Test Fixture and Probe Capacitance.

L

0213A/2096VE

DC Electrical Characteristics

Over Recommended Operating Conditions

SYMBOL

VOL
VOH
IIL

IIH
IIL-isp

IIL-PU
IOS

ICC

Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current

Input or I/O High Leakage Current

BSCAN Input Low Leakage Current
I/O Active Pull-Up Current

1

Output Short Circuit Current

2, 4

Operating Power Supply Current

1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test

PARAMETER

CONDITION MIN. TYP. MAX. UNITS

I = 8 mA

OL

I = -4 mA

OH

0V ≤ V ≤ V (Max.)

IN IL

(V – 0.2)V ≤ V ≤ V

CC

V ≤ V ≤ 5.25V

IN

CC

0V ≤ V ≤ V
0V ≤ V ≤ V
V = 3.3V, V = 0.5V
V = 0.0V, V = 3.0V

f = 1 MHz

IL

IN

IN IL

CC OUT

IL

CLOCK

IH

OUT

CC

IN

–

2.4
–
–
–
–
–
–

–

problems by tester ground degradation. Characterized but not 100% tested.

2. Measured using six 16-bit counters.

3. Typical values are at V = 3.3V and T = 25°C.

4. Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption

CC

CC

A

section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I .

CC

3

–
–
–
–
–
–
–
–

125

0.4
–

-10

10
10

-150

-150

-100
–

Table 2-0007A/2096VE

µA
µA
µA
µA
µA

mA
mA

V
V

4

Specifications ispLSI 2096VE

External Timing Parameters

Over Recommended Operating Conditions

3

TEST

COND.

t

pd1

t

pd2

f

max

f

max (Ext.)

f

max (Tog.)

t

su1

t

co1

t

h1

t

su2

t

co2

t

h2

t

r1

t

rw1

t

ptoeen

t

ptoedis

t

goeen

t

goedis

t

wh

t

wl

1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.

2. Standard 16-bit counter using GRP feedback.

3. Reference Switching Test Conditions section.

A1Data Propagation Delay, 4PT Bypass, ORP Bypass ns
A2Data Propagation Delay ns
A3Clock Frequency with Internal Feedback MHz
–4Clock Frequency with External Feedback MHz
–5Clock Frequency, Max. Toggle MHz
–6GLB Reg. Setup Time before Clock, 4 PT Bypass ns
A7GLB Reg. Clock to Output Delay, ORP Bypass ns
–8GLB Reg. Hold Time after Clock, 4 PT Bypass ns
–9GLB Reg. Setup Time before Clock ns
A10GLB Reg. Clock to Output Delay ns
–11GLB Reg. Hold Time after Clock ns
A12Ext. Reset Pin to Output Delay, ORP Bypass ns
–13Ext. Reset Pulse Duration ns
B14Input to Output Enable ns
C15Input to Output Disable ns
B16Global OE Output Enable ns
C17Global OE Output Disable ns
–18External Synchronous Clock Pulse Duration, High ns
–19External Synchronous Clock Pulse Duration, Low ns

DESCRIPTION#PARAMETER

1

2

1

( )

tsu2 + tco1

MIN. MAX.

–4.0

–
250 –
158
277

2.5
–

0.0

3.3
–

0.0
–

3.5
–
–
–
–

1.8 –

1.8 –

-250

6.0

–
–
–

3.0
–
–

3.7
–

6.0
–

6.0

6.0

4.0

4.0

-200

MIN. MAX.

– 4.5
–

200 –
133
200

3.0
–

0.0

4.0
–

0.0
–

4.0
–
–
–

USE ispLSI 2096VE-250

–

2.5 –

2.5 –

Table 2-0030A/2096VE

UNITS

7.0

–
–
–

3.5
–
–

4.5
–

6.0
–

8.0

8.0

FOR NEW DESIGNS

5.0

5.0

v.1.0

5

Specifications ispLSI 2096VE

External Timing Parameters

Over Recommended Operating Conditions

3

TEST

COND.

tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl

1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.

2. Standard 16-bit counter using GRP feedback.

3. Reference Switching Test Conditions section.

A1Data Propagation Delay, 4PT Bypass, ORP Bypass – 7.5 – 10.0 ns
A2Data Propagation Delay – – ns
A3Clock Frequency with Internal Feedback 135 – 100 – MHz
–4Clock Frequency with External Feedback – – MHz
–5Clock Frequency, Max. Toggle – – MHz
–6GLB Reg. Setup Time before Clock, 4 PT Bypass – – ns
A7GLB Reg. Clock to Output Delay, ORP Bypass – – ns
–8GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – ns
–9GLB Reg. Setup Time before Clock 6.0 – ns
A10GLB Reg. Clock to Output Delay – – ns
–11GLB Reg. Hold Time after Clock 0.0 – ns
A12Ext. Reset Pin to Output Delay, ORP Bypass – – ns
–13Ext. Reset Pulse Duration 5.0 – ns
B14Input to Output Enable – – ns
C15Input to Output Disable – – ns
B16Global OE Output Enable – – ns
C17Global OE Output Disable – – ns
–18External Synchronous Clock Pulse Duration, High 3.5 – – ns
–19External Synchronous Clock Pulse Duration, Low 3.5 – – ns

DESCRIPTION#PARAMETER

1

2

1

( )

tsu2 + tco1

-135

MIN.

100
143

5.0

10.0

4.0
–
–

5.0
–

9.0
–

12.0

12.0

7.0

7.0

-100

MIN.MAX. MAX.

13.0

77

100

6.5

5.0

0.0

8.0

6.0

0.0

12.5

6.5

15.0

15.0

9.0

9.0

5.0

5.0

Table 2-0030B/2096VE

UNITS

v.1.0

6

Specifications ispLSI 2096VE

Internal Timing Parameters

1

Over Recommended Operating Conditions

PARAMETER

Inputs

t

io

t

din

GRP

t

grp

GLB

t

4ptbpc

t

4ptbpr

t

1ptxor

t

20ptxor

t

xoradj

t

gbp

t

gsu

t

gh

t

gco

t

gro

t

ptre

t

ptoe

t

ptck

ORP

t

orp

t

orpbp

Outputs

t

ob

t

sl

t

oen

t

odis

t

goe

Clocks

t

gy0

t

gy1/2

Global Reset

t

gr

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

2

20 Input Buffer Delay ns
21 Dedicated Input Delay ns

22 GRP Delay

23 4 Product Term Bypass Path Delay (Combinatorial) ns
24 4 Product Term Bypass Path Delay (Registered) ns
25 1 Product Term/XOR Path Delay ns
26 20 Product Term/XOR Path Delay ns
27 XOR Adjacent Path Delay ns
28 GLB Register Bypass Delay ns
29 GLB Register Setup Time before Clock ns
30 GLB Register Hold Time after Clock ns
31 GLB Register Clock to Output Delay ns
32 GLB Register Reset to Output Delay ns
33 GLB Product Term Reset to Register Delay ns
34 GLB Product Term Output Enable to I/O Cell Delay ns
35 GLB Product Term Clock Delay ns

36 ORP Delay ns
37 ORP Bypass Delay

38 Output Buffer Delay ns
39 Output Slew Limited Delay Adder ns
40 I/O Cell OE to Output Enabled ns
41 I/O Cell OE to Output Disabled ns
42 Global Output Enable ns

43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line ns

45 Global Reset to GLB

DESCRIPTION#

3

-250

MIN. MAX.

0.5

–

0.7

–

0.2

–

1.5

–

2.0

–

2.8

–

2.8

–

2.8

–

0.0

–

0.8

1.7

0.8

–
–

0.2

–

0.3

–

3.7

–

2.9

–

3.6

1.1

–

0.4

–

1.4

–

2.0

–

2.4

–

2.4

–

1.6

–

-200

MIN. MAX.

0.5

–

1.1

–

0.6

–

1.4

–

1.9

–

2.9

–

2.9

–

2.9

–

0.0

–

–

1.2
–

1.8

0.3

–

0.4

–

4.3

–

3.9

–

4.0

1.0

1.5

–

0.5

–

1.5

–

2.0

–

3.0

–

3.0

–

2.0

–

UNITS

ns

ns

USE ispLSI 2096VE-250 FOR NEW DESIGNS

1.2

1.2

1.0

1.0

1.4

1.4

1.2

1.2

–

3.9

–ns

3.6

Table 2-0036A/2096VE

v.1.0

7

Specifications ispLSI 2096VE

Internal Timing Parameters

1

Over Recommended Operating Conditions

PARAMETER

Inputs

t

io

t

din

GRP

t

grp

GLB

t

4ptbpc

t

4ptbpr

t

1ptxor

t

20ptxor

t

xoradj

t

gbp

t

gsu

t

gh

t

gco

t

gro

t

ptre

t

ptoe

t

ptck

ORP

t

orp

t

orpbp

Outputs

t

ob

t

sl

t

oen

t

odis

t

goe

Clocks

t

gy0

t

gy1/2

Global Reset

t

gr

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

2

20 Input Buffer Delay ns
21 Dedicated Input Delay ns

22 GRP Delay

23 4 Product Term Bypass Path Delay (Combinatorial) ns
24 4 Product Term Bypass Path Delay (Registered) ns
25 1 Product Term/XOR Path Delay ns
26 20 Product Term/XOR Path Delay ns
27 XOR Adjacent Path Delay ns
28 GLB Register Bypass Delay ns
29 GLB Register Setup Time before Clock ns
30 GLB Register Hold Time after Clock ns
31 GLB Register Clock to Output Delay ns
32 GLB Register Reset to Output Delay ns
33 GLB Product Term Reset to Register Delay ns
34 GLB Product Term Output Enable to I/O Cell Delay ns
35 GLB Product Term Clock Delay ns

36 ORP Delay ns
37 ORP Bypass Delay

38 Output Buffer Delay ns
39 Output Slew Limited Delay Adder ns
40 I/O Cell OE to Output Enabled ns
41 I/O Cell OE to Output Disabled ns
42 Global Output Enable ns

43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line ns

45 Global Reset to GLB

DESCRIPTION#

3

MIN.

–
–

–

–
–
–
–
–
–

1.2

3.8
–
–

–
–

1.6

–
–

–
–
–
–
–

1.6

1.8

–

-135

0.5

1.7

1.2

3.7

3.7

4.7

4.7

4.7

0.5
–

–

0.3

1.1

6.1

6.9

5.0

1.5

0.5

1.6

2.0

3.4

3.4

3.6

1.6

1.8

5.8

-100

MIN.MAX. MAX.

–
–

–

–
–
–
–
–
–

1.7

4.8
–
–

–
–

2.6

–
–

–
–
–
–
–

2.4

2.6

–ns

Table 2-0036B/2096VE

0.7

2.5

1.8

5.2

4.7

6.2

6.2

6.2

1.0
–

–

0.3

3.1

7.1

9.1

5.6

1.7

0.7

1.6

2.0

3.4

3.4

5.6

2.4

2.6

7.1

UNITS

ns

ns

v.1.0

8

ispLSI 2096VE Timing Model

Specifications ispLSI 2096VE

I/O CellORPGLBGRPI/O Cell

Feedback

Ded. In

I/O Pin

(Input)

Reset

Y0,1,2

GOE 0

#21

I/O Delay

#20

#45

#43, 44

GRP

#22

#42

Reg 4 PT Bypass

Comb 4 PT Bypass #23

#24

20 PT

XOR Delays

#25, 26, 27

Control

RE

PTs

OE
CK

#33, 34,

35

Derivations of tsu, th and tco from the Product Term Clock

2.5ns

=

Logic + Reg su - Clock (min)

t

io + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))

=

(
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)

=

(0.5 + 0.2 + 2.8) + (0.8) - (0.5 + 0.2 + 0.8)

=
=

t

io + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)

(

=

(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)

=

(0.5 + 0.2 + 3.6) + (1.7) - (0.5 + 0.2 + 2.8)

=

t

su

2.8ns

t

h Clock (max) + Reg h - Logic

GLB Reg Bypass ORP Bypass

#28

GLB Reg

Delay

DQ
RST

#29, 30,

31, 32

#37

ORP

Delay

#36

#38,

#40, 41

0491/2032

39

I/O Pin

(Output)

t

co

7.0ns

Clock (max) + Reg co + Output

=

t

io + tgrp + tptck(max)) + (tgco) + (torp + tob)

(

=

(#20 + #22 + #35) + (#31) + (#36 + #38)

=

(0.5 + 0.2 + 3.6) + (0.2) + (1.1 + 1.4)

=

Note: Calculations are based upon timing specifications for the ispLSI 2096VE-250L.

Table 2-0042/2096VE

9

Power Consumption

Specifications ispLSI 2096VE

Power consumption in the ispLSI 2096VE device de­pends on two primary factors: the speed at which the
device is operating and the number of Product Terms

Figure 3. Typical Device Power Consumption vs fmax

260

240

220

200

180

CC (mA)

I

160

140

120

050100 150 200 250

f

max (MHz)

Notes: Configuration of six 16-bit counters
Typical current at 3.3V, 25° C

used. Figure 3 shows the relationship between power
and operating speed.

ispLSI 2096VE

ICC can be estimated for the ispLSI 2096VE using the following equation:
I

(mA) = 8.0 + (# of PTs * 0.63) + (# of Nets * Fmax * 0.005)

CC

Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)

The I

estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two

CC

GLB loads on average exists. These values are for estimates only. Since the value of I
operating conditions and the program in the device, the actual I

should be verified.

CC

is sensitive to

CC

10

Pin Description

Specifications ispLSI 2096VE

NAME

I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95

BSCAN

TDI/IN 0

TMS/IN 1

TDO/IN 2

TCK/IN 3

21,
27,
35,
41,
51,
57,
64,
71,
85,
91,

99,
105,
115,
121,
128,

7,

80, 17

19

20

48

112

77

TQFP PIN NUMBERS DESCRIPTION

22,
28,
36,
42,
52,
58,
65,
72,
86,

92,
100,
106,
116,
122,

11384,

23,

24,
30,
38,
44,
54,
60,
68,
74,
88,
94,

10,

25,
32,
39,
45,
55,
61,
69,
75,
89,

96,
103,
109,
119,
125,

4,

5,

11,

29,
37,
43,
53,
59,
67,
73,
87,
93,

101,

102,

107,

108,

117,

118,

123,
1,
8,

124,
3,
9,

Input/Output Pins - These are the general purpose I/O pins used by the

26

logic array.

33
40
46
56
62
70
76
90

97
104
110
120
126

6

12

Global Output Enables input pins.GOE 0, GOE 1
Dedicated input pins to the device.IN 4, IN 5

Input — Dedicated in-system programming Boundary Scan enable input
pin. This pin is brought low to enable the programming mode. The TMS,
TDI, TDO and TCK controls become active.

Input — This pin performs two functions. When BSCAN is logic low, it
functions as a serial data input pin to load programming data into the
device. When BSCAN is high, it functions as a dedicated input pin.

Input — This pin performs two functions. When BSCAN is logic low, it
functions as a mode control pin for the Boundary Scan state machine.
When BSCAN is high, it functions as a dedicated input pin.

Output/Input — This pin performs two functions. When BSCAN is logic
low, it functions as an output pin to read serial shift register data. When
BSCAN is high, it functions as a dedicated input pin.

Input — This pin performs two functions. When BSCAN is logic low, it
functions as a clock pin for the Boundary Scan state machine. When

BSCAN is high, it functions as a dedicated input pin.

RESET

Y0, Y1, Y2

GND

VCC

1

NC

1. NC pins are not to be connected to any active signal, VCC or GND.

15
14

83,

18,

111,

34,

127

2,

16,

95,

114

13, 49, 82

78

50, 63,

31, 47, 66, 81,

79, 98,

Active Low (0) Reset pin which resets all of the registers in the device.
Dedicated Clock input. This clock input is connected to one of the clock

inputs of all the GLBs on the device.
Ground (GND)

V

CC

No Connect.

Table 2-0002-2096VE

11

Specifications ispLSI 2096VE

Pin Configuration

ispLSI 2096VE 128-Pin TQFP Pinout Diagram (0.4mm Lead Pitch/14.0 x 14.0mm Body Size)

I/O 85

VCC
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95

1

NC

Y0

RESET

VCC

GOE 1

GND

BSCAN

TDI/IN 0

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9

VCC
I/O 10

1
2
3
4
5
6

7
8
9
10
11
12

13
14
15
16
17
18
19
20
21
22
23
24

25
26
27
28
29
30
31
32

I/O 84

GND

128

127

I/O 83

I/O 82

126

125

I/O 81

I/O 80

124

123

I/O 79

I/O 78

121

122

I/O 74

I/O 73

116

VCC

I/O 72

115

114

IN 5

TDO/IN 2

113

112

I/O 77

I/O 76

120

119

I/O 75

118

117

ispLSI 2096VE

Top View

GND

I/O 71

111

110

I/O 70

I/O 69

109

108

I/O 68

I/O 67

107

106

I/O 66

I/O 65

105

104

I/O 64

I/O 63

103

102

I/O 62

I/O 61

101

100

I/O 60

GND

I/O 59

99989764

96
95

94
93
92
91
90

89
88
87
86
85
84

83
82
81
80
79
78
77
76
75
74
73
72

71
70
69
68
67
66
65

I/O 58

VCC
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 4
Y1

1

NC
VCC
GOE 0
GND
Y2
TCK/IN 3
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
VCC

I/O 37

33343536373839404142434445464748495051525354555657585960616263

NC

1

VCC

GND

I/O 12

I/O 13

I/O 14

I/O 15

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 11

1. NC pins are not to be connected to any active signals, VCC or GND.

I/O 23

GND

I/O 24

TMS/IN 1

I/O 25

12

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

I/O 32

I/O 33

I/O 34

I/O 35

GND

I/O 36

0124-2096VE

Part Number Description

Specifications ispLSI 2096VE

ispLSI 2096VE XX X XXXXX

–

Device Family

Device Number
Speed

250 = 250 MHz
200 = 200 MHz
135 = 135 MHz
100 = 100 MHz

*Use ispLSI 2096VE-250 for new designs

f

max

f

max*

f

max

f

max

ispLSI 2096VE Ordering Information

Conventional Packaging

FAMILY fmax (MHz)

250 128-Pin TQFP4.0 ispLSI 2096VE-250LT128

ispLSI

*Use ispLSI 2096VE-250 for new designs

200
135
100 128-Pin TQFP10

tpd (ns)

4.5

7.5

X

Grade

Blank = Commercial
I = Industrial

Package

T128 = 128-Pin TQFP
TN128 = Lead-Free 128-Pin TQFP

Power

L = Low

0212/2096VE

COMMERCIAL

ORDERING NUMBER PACKAGE

ispLSI 2096VE-200LT128*

ispLSI 2096VE-100LT128

128-Pin TQFP
128-Pin TQFPispLSI 2096VE-135LT128

Table 2-0041A/2096VE

FAMILY fmax (MHz)

ispLSI

135

Lead-Free Packaging

FAMILY fmax (MHz)

250 Lead-Free 128-Pin TQFP4.0 ispLSI 2096VE-250LTN128

ispLSI

FAMILY fmax (MHz)

ispLSI

135
100 Lead-Free 128-Pin TQFP10

135

tpd (ns)

7.5

7.5

tpd (ns)

7.5

INDUSTRIAL

ORDERING NUMBER PACKAGE

ispLSI 2096VE-135LT128I

COMMERCIAL

ORDERING NUMBER PACKAGEtpd (ns)

Lead-Free 128-Pin TQFPispLSI 2096VE-135LTN128

ispLSI 2096VE-100LTN128

INDUSTRIAL

ORDERING NUMBER PACKAGE

ispLSI 2096VE-135LTN128I

Lead-Free 128-Pin TQFP

128-Pin TQFP

Table 2-0041B/2096VE

13