Lattice ispLSI 2032E User Manual

ispLSI® 2032E

In-System Programmable

SuperFAST™ High Density PLD

Features

• SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 1000 PLD Gates
— 32 I/O Pins, Two Dedicated Inputs
— 32 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functionally and JEDEC Upward Compatible

with ispLSI 2032 Devices

2

• HIGH PERFORMANCE E

— fmax = 225 MHz Maximum Operating Frequency
— tpd = 3.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— 5V Programmable Logic Core
— ispJTAG™ In-System Programmable via IEEE 1149.1

(JTAG) Test Access Port
— User-Selectable 3.3V or 5V I/O (48-Pin Package Only)

Supports Mixed Voltage Systems
— PCI Compatible Outputs (48-Pin Package Only)
— Open-Drain Output Option
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Unused Product Term Shutdown Saves Power

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to

Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global

Interconnectivity

CMOS® TECHNOLOGY

Functional Block Diagram

GLB

Global Routing Pool

(GRP)

DQ

DQ

Logic
Array

DQ

DQ

A7

A6

A5

A4

Input Bus

Output Routing Pool (ORP)

0139Bisp/2000

A0

A1

Input Bus

A2

Output Routing Pool (ORP)

A3

Description

The ispLSI 2032E is a High Density Programmable Logic
Device. The device contains 32 Registers, 32 Universal
I/O pins, two Dedicated Input Pins, three Dedicated
Clock Input Pins, one dedicated Global OE input pin and
a Global Routing Pool (GRP). The GRP provides com­plete interconnectivity between all of these elements.
The ispLSI 2032E features 5V in-system programmabil­ity and in-system diagnostic capabilities. The ispLSI
2032E offers non-volatile reprogrammability of the logic,
as well as the interconnect to provide truly reconfigurable
systems.

The basic unit of logic on the ispLSI 2032E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. A7 (see Figure 1). There are a total of eight GLBs in the
ispLSI 2032E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.

The device also has 32 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually

Copyright © 2003 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

2032e_05 1

November 2003

Functional Block Diagram

E

Figure 1. ispLSI 2032E Functional Block Diagram

GOE 0

Specifications ispLSI 2032E

I/O 0
I/O 1
I/O 2
I/O 3

I/O 4
I/O 5
I/O 6
I/O 7

I/O 8

I/O 9
I/O 10
I/O 11

I/O 12
I/O 13
I/O 14
I/O 15

TDI/IN 0

TDO/IN 1

TMS

BSCAN

Notes:
*Y1 and RESET are multiplexed on the same pin

A0

A1

Input Bus

A2

Output Routing Pool (ORP)

A3

Global Routing Pool

programmed to be a combinatorial input, output or bi­directional I/O pin with 3-state control. The signal levels
are TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA. Each output can be pro­grammed independently for fast or slow output slew rate
to minimize overall output switching noise. By connecting
the VCCIO pins to a common 5V or 3.3V power supply,
I/O output levels can be matched to 5V or 3.3V compat­ible voltages. When connected to a 5V supply, the I/O
pins provide PCI-compatible output drive (48-pin device
only).

Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the ORP. Each ispLSI
2032E device contains one Megablock.

The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.

I/O 31

Input Bus

0139/2032

I/O 30
I/O 29
I/O 28

I/O 27
I/O 26
I/O 25
I/O 24

I/O 23
I/O 22
I/O 21
I/O 20

I/O 19
I/O 18
I/O 17
I/O 16

(GRP)

Y1*

TCK/Y2

A7

A6

A5

Output Routing Pool (ORP)

A4

CLK 1

CLK 2

CLK 0

Y0

Clocks in the ispLSI 2032E device are selected using the
dedicated clock pins. Three dedicated clock pins (Y0, Y1,
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the
outputs of the ispLSI 2032E are individually program­mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro­grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the Lattice software tools.

2

Specifications ispLSI 2032E

Absolute Maximum Ratings

1

Supply Voltage Vcc.................................. -0.5 to +7.0V

Input Voltage Applied........................-2.5 to VCC +1.0V

Off-State Output Voltage Applied .....-2.5 to VCC +1.0V

Storage Temperature................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (TJ) with Power Applied ... 150°C

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Condition

SYMBOL

V

CC
CCIO

IL
IH

1

V
V

V

1. 3.3V I/O operation not available for 44-pin packages.

Supply Voltage: Logic Core, Input Buffers
Supply Voltage: Output Drivers

Input Low Voltage
Input High Voltage

PARAMETER

5V

3.3V

TA = 0°C to +70°C

MIN. MAX. UNITS

4.75

4.75 5.25 V

3.0 3.6 V
0

2.0

5.25

0.8

V

cc

+1

V

V
V

Table 2-0005/2032E

Capacitance (TA=25°C, f=1.0 MHz)

SYMBOL

C

1

C

2

C

3

Dedicated Input Capacitance
I/O Capacitance
Clock Capacitance

PARAMETER

Erase/Reprogram Specification

PARAMETER MINIMUM MAXIMUM UNITS

Erase/Reprogram Cycles

TYP

10

10,000 – Cycles

UNITS TEST CONDITIONS

6
7

pf
pf
pf V = 5.0V, V = 2.0V

V = 5.0V, V = 2.0V

CC

V = 5.0V, V = 2.0V

CC I/O

CC Y

IN

Table 2-0006/2032E

Table 2-0008/2032E

3

Switching Test Conditions

Specifications ispLSI 2032E

Input Pulse Levels
Input Rise and Fall Time 10% to 90%

Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.5V from

steady-state active level.

GND to 3.0V

1.5 ns

1.5V

1.5V

See Figure 2

Table 2-0003/2032E

Figure 2. Test Load

Device
Output

+ 5V

R

1

R

2

*

C

L

Output Load Conditions (see Figure 2)

*

TEST CONDITION R1 R2 CL

CL includes Test Fixture and Probe Capacitance.

A 470Ω 390Ω 35pF

Active High

B

Active Low
Active High to Z

at V -0.5V

C

Active Low to Z
at V +0.5V

OH

OL

∞ 390Ω 35pF

470Ω 390Ω 35pF

∞ 390Ω 5pF

470Ω 390Ω 5pF

Table 2 - 0004A

DC Electrical Characteristics

Over Recommended Operating Conditions

SYMBOL

VOL
VOH
IIL

IIH

IIL-PU

1

IOS

2,4,6

ICC

Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current

Input or I/O High Leakage Current

I/O Active Pull-Up Current, non-PCI
I/O Active Pull-Up Current, PCI

Output Short Circuit Current, non-PCI
Output Short Circuit Current, PCI

Operating Power Supply Current

PARAMETER

I

= 8 mA

OL

= -4 mA

I

OH

0V ≤ V

IN

- 0.2)V ≤ VIN ≤ V

(V

CCIO

≤ V

V

CCIO

0V ≤ V

5

5

IN

0V ≤ VIN ≤ 2.0V -10 – -250 µA

= 5V, V

V

CCIO

V

= 5.0V or 3.3V, V

CCIO

V

= 0.0V, VIH = 3.0V

IL

f

TOGGLE

1. One output at a time for a maximum duration of one second (V

2. Meaured using two 16-bit counters.

3. Typical values are at V

= 5V and TA = 25°C.

CC

4. Unused inputs held at 0.0V.

5. Available in 48-pin package only.

6. Maximum I

varies widely with specific device configuration and operating frequency. Refer to the

CC

Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor
Data Book or CD-ROM to estimate maximum I

CC

.

CONDITION MIN. TYP.

≤ VIL (Max.)

CCIO

≤ 5.25V

IN

≤ 2.0V

= 0.5V

OUT

= 0.5V – – -240 mA

OUT

-225/-200

= 1 MHz

= 0.5V). Characterized, but not 100% tested.

OUT

Others mA–

1

–

2.4
–
–
–

-10

–

–85 mA–
–65

3

–
–
–
–
–
–

–

MAX. UNITS

0.4
–

-10

10
10

-150

-200

Table 2-0007/2032E

Test

Point

0213A

V
V

µA
µA
µA
µA

mA

4

External Timing Parameters

Over Recommended Operating Conditions

Specifications ispLSI 2032E

PARAMETER

tpd1
tpd2
fmax

fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl

1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-bit counter using GRP feedback.

4. Reference Switching Test Conditions section.

TEST

COND.

A1Data Prop. Delay, 4PT Bypass, ORP Bypass – 3.5 – 5.0 ns
A2Data Prop. Delay – – ns
A3Clk Frequency with Int. Feedback

–4Clk Frequency with Ext. Feedback – – MHz
–5Clk Frequency, Max. Toggle – – MHz
–6GLB Reg. Setup Time before Clk, 4 PT Bypass – – ns
A7GLB Reg. Clk to Output Delay, ORP Bypass – – ns
–8GLB Reg. Hold Time after Clk, 4 PT Bypass 0.0 – ns
–9GLB Reg. Setup Time before Clk 3.5 – ns
–10GLB Reg. Clk to Output Delay – – ns
–11GLB Reg. Hold Time after Clk 0.0 – ns
A12Ext. Reset Pin to Output Delay, ORP Bypass – – ns
–13Ext. Reset Pulse Duration 3.5 – ns
B14Input to Output Enable – – ns
C15Input to Output Disable – – ns
B16Global OE Output Enable – – ns
C17Global OE Output Disable – – ns
–18Ext. Synch. Clk Pulse Duration, High 2.0 – – ns
–19Ext. Synch. Clk Pulse Duration, Low 2.0 – – ns

2

4

DESCRIPTION#

1

3

( )

1
tsu2 + tco1

-225

MIN. MAX.

– 3.5
–

5.5

225 –

2.5
–

2.5

0.0

3.5
–

3.5

0.0
–

5.0

3.5
–

7.0

–

7.0

–

3.5

–

3.5

2.0 –

2.0 –

–
–
–

–
–

–

–

167
250

-200

MIN.

200 – 180 – MHz
167
250

2.5

USE 2032E-225 FOR

MIN.MAX. MAX.

5.5

125
200

3.0

2.5
–

0.0

–

4.0

3.5
–

0.0

5.0
–

4.0

7.0

NEW DESIGNS

7.0

3.5

3.5

2.5

2.5

-180
UNITS

7.5

4.0

4.5

6.5

10.0

10.0

5.0

5.0

Table 2-0030A/2032E

5

External Timing Parameters

Over Recommended Operating Conditions

Specifications ispLSI 2032E

PARAMETER

tpd1
tpd2
fmax

fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl

1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-bit counter using GRP feedback.

4. Reference Switching Test Conditions section.

TEST

COND.

A1Data Propagation Delay, 4PT Bypass, ORP Bypass – 7.5 – 10.0 ns
A2Data Propagation Delay – – ns
A3Clock Frequency with Internal Feedback

–4Clock Frequency with External Feedback – – MHz
–5Clock Frequency, Max. Toggle – – MHz
–6GLB Register Setup Time before Clock, 4 PT Bypass – – ns
A7GLB Register Clock to Output Delay, ORP Bypass – – ns
–8GLB Register Hold Time after Clock, 4 PT Bypass 0.0 – ns
–9GLB Register Setup Time before Clock 5.5 – ns
–10GLB Register Clock to Output Delay – – ns
–11GLB Register Hold Time after Clock 0.0 – ns
A12External Reset Pin to Output Delay, ORP Bypass – – ns
–13External Reset Pulse Duration 5.0 – ns
B14Input to Output Enable – – ns
C15Input to Output Disable – – ns
B16Global OE Output Enable – – ns
C17Global OE Output Disable – – ns
–18External Synchronous Clock Pulse Duration, High 3.0 – – ns
–19External Synchronous Clock Pulse Duration, Low 3.0 – – ns

2

4

DESCRIPTION#

1

3

1

( )

tsu2 + tco1

-135

10.0

4.5
–

–

5.5
–

9.0
–

12.0

12.0

6.0

6.0

MIN.MAX. MAX.

77.0
125

5.5

0.0

7.5

0.0

6.5

4.0

4.0

MIN.

137 – 111 – MHz
100
167

4.0

-110
UNITS

13.0

5.5

6.5

12.5

14.5

14.5

7.0

7.0

Table 2-0030B/2032E

6

Specifications ispLSI 2032E

Internal Timing Parameters

PARAMETER

Inputs

tio
tdin

GRP

tgrp

GLB

t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck

ORP

torp
torpbp

Outputs

tob
tsl

toen
todis
tgoe

Clocks

tgy0
tgy1/2

Global Reset

tgr

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

2

20 Input Buffer Delay – – 0.6 ns
21 Dedicated Input Delay – – 1.3 ns

22 GRP Delay – – 0.7 ns

23 4 Product Term Bypass Path Delay (Combinatorial) – – 1.8 ns
24 4 Product Term Bypass Path Delay (Registered) – – 2.8 ns
25 1 Product Term/XOR Path Delay – – 3.8 ns
26 20 Product Term/XOR Path Delay – – 3.8 ns
27 XOR Adjacent Path Delay – – 3.8 ns
28 GLB Register Bypass Delay – – 0.0 ns
29 GLB Register Setup Time before Clock – 0.3 – ns
30 GLB Register Hold Time after Clock – 2.7 – ns
31 GLB Register Clock to Output Delay – – 0.7 ns
32 GLB Register Reset to Output Delay – – 1.1 ns
33 GLB Product Term Reset to Register Delay – – 2.9 ns
34 GLB Product Term Output Enable to I/O Cell Delay – – 5.9 ns
35 GLB Product Term Clock Delay 1.5 3.7 ns

36 ORP Delay – – 1.1 ns
37 ORP Bypass Delay – – 0.6 ns

38 Output Buffer Delay – – 1.3 ns
39 Output Slew Limited Delay Adder – – 1.5 ns

40 I/O Cell OE to Output Enabled – – 2.8 ns
41 I/O Cell OE to Output Disabled – – 2.8 ns
42 Global Output Enable – – 2.2 ns

43

Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 1.2 1.4 1.4 ns

44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 1.4 1.6 1.6 ns

45

Global Reset to GLB

1

Over Recommended Operating Conditions

DESCRIPTION#

3

-225

MIN. MAX.

0.6

–

1.3

–

–

0.7

–

1.2

–

1.2

2.2

–

2.2

–

2.2

–

0.0

–

–

0.8
–

1.7

–

0.7

–

1.3

–

2.5

–

4.2

0.3 2.8

––1.0

0.0

–

1.0

–

1.5

–

1.5

–

1.5

–

2.0

0.8

0.8

1.0

1.0

–

2.7

-200

MIN.

0.4

1.3

0.7

1.8

1.8

2.8

2.8

2.8

0.0

0.8

1.7

0.7

2.9

2.5

4.4

0.7 3.2

1.0

0.0

0.6

1.5

1.5

1.5

USE 2032E-225 FOR NEW DESIGNS

2.0

1.2

1.4

––3.5 ns

2.7

-180

MIN.MAX. MAX.

Table 2-0036A/2032E

UNITS

7

Specifications ispLSI 2032E

Internal Timing Parameters

PARAMETER

Inputs

t

io

t

din

GRP

t

grp

GLB

t

4ptbpc

t

4ptbpr

t

1ptxor

t

20ptxor

t

xoradj

t

gbp

t

gsu

t

gh

t

gco

t

gro

t

ptre

t

ptoe

t

ptck

ORP

t

orp

t

orpbp

Outputs

t

ob

t

sl

t

oen

t

odis

t

goe

Clocks

t

gy0

t

gy1/2

Global Reset

t

gr

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

2

20 Input Buffer Delay – – 1.7 ns
21 Dedicated Input Delay – – 3.4 ns

22 GRP Delay – – 1.7 ns

23 4 Product Term Bypass Path Delay (Combinatorial) – – 4.9 ns
24 4 Product Term Bypass Path Delay (Registered) – – 4.8 ns
25 1 Product Term/XOR Path Delay – – 6.2 ns
26 20 Product Term/XOR Path Delay – – 6.8 ns
27 XOR Adjacent Path Delay – – 7.5 ns
28 GLB Register Bypass Delay – – 0.1 ns
29 GLB Register Setup Time before Clock – 0.5 – ns
30 GLB Register Hold Time after Clock – 4.0 – ns
31 GLB Register Clock to Output Delay – – 0.6 ns
32 GLB Register Reset to Output Delay – – 1.8 ns
33 GLB Product Term Reset to Register Delay – – 5.9 ns
34 GLB Product Term Output Enable to I/O Cell Delay – – 7.1 ns
35 GLB Product Term Clock Delay 4.0 7.0 ns

36 ORP Delay – – 1.5 ns
37 ORP Bypass Delay – – 0.5 ns

38 Output Buffer Delay – – 1.2 ns
39 Output Slew Limited Delay Adder – – 10.0 ns

40 I/O Cell OE to Output Enabled – – 4.0 ns
41 I/O Cell OE to Output Disabled – – 4.0 ns
42 Global Output Enable – – 3.0 ns

43

Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 2.3 3.2 3.2 ns

44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 2.3 3.2 3.2 ns

45

Global Reset to GLB

1

DESCRIPTION#

3

-135

MIN.

1.1

2.4

1.3

3.6

3.6

5.0

5.1

5.6

0.0

0.3

3.0

0.7

1.1

4.4

6.4

2.9 5.2

1.3

0.3

1.2

10.0

3.2

3.2

2.8

2.3

2.3

––9.0 ns

6.4

-110

MIN.MAX. MAX.

Table 2-0036B/2032E

UNITS

8

ispLSI 2032E Timing Model

Specifications ispLSI 2032E

I/O CellORPGLBGRPI/O Cell

Feedback

Ded. In

I/O Pin
(Input)

Reset

Y0,1,2

GOE 0

#21

I/O Delay

#20

GRP

#22

#45

#43, 44

#42

Comb 4 PT Bypass #23

Reg 4 PT Bypass

#24

20 PT

XOR Delays

#25, 26, 27

Control

RE

PTs

OE
CK

#33, 34,

35

Derivations of tsu, th and tco from the Product Term Clock

tsu Logic + Reg su - Clock (min)

th Clock (max) + Reg h - Logic

tco Clock (max) + Reg co + Output

=

tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))

=

(
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)

=

(0.6 + 0.7 + 2.2) + (0.8) - (0.6 + 0.7 + 0.3)

=

2.7
=

tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)

(

=

(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)

=

(0.6 + 0.7 + 2.8) + (1.7) - (0.6 + 0.7 + 2.2)

=

2.3
=

tio + tgrp + tptck(max)) + (tgco) + (torp + tob)

(

=

(#20 + #22 + #35) + (#31) + (#36 + #38)

=

(0.6 + 0.7 + 2.8) + (0.7) + (1.0 + 1.0)

=

6.8

GLB Reg Bypass ORP Bypass

#28

GLB Reg

Delay

DQ
RST

#29, 30,

31, 32

#37

ORP

Delay

#36

#40, 41

0491/2032E

#38,
#39

I/O Pin

(Output)

Note: Calculations are based upon timing specifications for the ispLSI 2032E-225L

Table 2-0042/2032E

9

Power Consumption

Specifications ispLSI 2032E

Power consumption in the ispLSI 2032E device depends
on two primary factors: the speed at which the device is
operating and the number of Product Terms used.

Figure 3. Typical Device Power Consumption vs fmax

150
140
130
120
110

100

90

CC (mA)

I

80
70

60
50

Figure 3 shows the relationship between power and
operating speed.

ispLSI 2032E-225 and -200

ispLSI 2032E-180
and Slower

40

120406080100 120 140 160 180 200 220 240

f

max (MHz)

Notes: Configuration of two 16-bit counters

Typical current at 5V, 25°C

ICC can be estimated for the ispLSI 2032E using the following equation:
For 2032E-225 and -200: ICC = 4.5 + (# of PTs * 1.3) + (# of nets * Max freq * 0.0035)

For 2032E-180 and Slower: I

= 4.5 + (# of PTs * 1.02) + (# of nets * Max freq * 0.0035)

CC

Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)

The I
loads on average exists. These values are for estimates only. Since the value of I
conditions and the program in the device, the actual I

estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB

CC

is sensitive to operating

CC

should be verified.

CC

0127A/2032E

10

Pin Description

Specifications ispLSI 2032E

44-PIN PLCC

NAME

I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31

Y0

RESET/Y1

BSCAN

1

TDI/IN 0

TMS/NC

TDO/IN 1

TCK/Y2

VCC
VCCIO

1. Pins have dual function capability.

2. NC pins are not to be connected to any active signals, V

2

1

1

PIN NUMBERS

15,

16,
20,
26,
30,
38,
42,
4,
8,

17,
21,
27,
31,
39,
43,
5,
9,

19,
25,
29,
37,
41,
3,
7,

11

35

13

14

36

24

33

1, 23GND
12, 34

PIN NUMBERS

18,

9,

22,

13,

28,

19,

32,

23,

40,

31

44,

35,

6,

41,

10

1,
40
5

29

7

8

30

18

27

17, 39
6, 28

44-PIN TQFP

10,

11,

14,

15,

20,

21,

24,

25,

32,

33,

36,

37,

42,

43,

2,

3,

48-PIN TQFP

PIN NUMBERS

9,

12,

14,

16,

20,

22,

25,

26,

33,

34,

38,

38,

44,

44,

1,

4

43
5

31

7

8

32

19

29

12, 18, 36, 42
6, 30

24, 48

or GND.

CC

10,
15,
21,
26,
34,
39,
45,
2,

11,
16,
22,
27,
35,
40,
46,
3,

DESCRIPTION

13,

Input/Output Pins — These are the general purpose

17,

I/O pins used by the logic array.
23,
28,
37,
41,
47,
4

Global Output Enable input pin.2GOE 0

Dedicated Clock input. This clock input is connected to

one of the clock inputs of all the GLBs on the device.

This pin performs two functions:

- Dedicated clock input. This clock input is brought

into the Clock Distribution Network, and can optionally

be routed to any GLB and/or I/O cell on the device.

- Active Low (0) Reset pin which resets all of the GLB

and I/O registers in the device.

Input — Dedicated in-system programming enable

input pin. This pin is brought low to enable the

programming mode. The TMS, TDI, TDO and TCK

controls become active.

Input — This pin performs two functions. When
BSCAN is logic low, it functions as an input pin to load
programming data into the device. TDI/IN0 also is used
as one of the two control pins for the ISP state
machine. When BSCAN is high, it functions as a
dedicated input pin.

Input — When in ISP mode, controls operation of ISP

state machine.

Output/Input — This pin performs two functions. When

BSCAN is logic low, it functions as an output pin to

read serial shift register data. When BSCAN is high, it

functions as a dedicated input pin.

Input — This pin performs two functions. When

BSCAN is logic low, it functions as a clock pin for the

Serial Shift Register. When BSCAN is high, it

functions as a dedicated clock input. This clock input

is brought into the Clock Distribution Network and

can be routed to any GLB and/or I/O cell on the

device.

Ground (GND)

V

CC

Supply voltage for output drivers, 5V or 3.3V. All

VCCIO pins must be connected to the same voltage

level.

Table 2-0002/2032E

11

Pin Configuration

ispLSI 2032E 44-Pin PLCC Pinout Diagram

618519420321222123442443254226412740

I/O 27

I/O 26

I/O 25

I/O 24

GOE 0

GND

Specifications ispLSI 2032E

I/O 23

I/O 22

I/O 21

I/O 20

I/O 19

I/O 28
I/O 29
I/O 30
I/O 31

BSCAN

1

TDI/IN 0

1. Pins have dual function capability.

2. NC pins are not to be connected to any active signals, V

Y0

VCC

I/O 0
I/O 1
I/O 2

7
8
9
10
11
12
13
14
15
16
17

ispLSI 2032E 44-Pin TQFP Pinout Diagram

441243134214411540163917381837193620352134

ispLSI 2032E

Top View

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

GND

I/O 27

I/O 26

I/O 25

I/O 24

GOE 0

GND

I/O 8

TDO/IN 1

1

I/O 23

I/O 22

I/O 9

I/O 10

I/O 21

I/O 20

28

I/O 11

I/O 19

39
38
37
36
35
34
33
32
31
30
29

or GND.

CC

I/O 18
I/O 17
I/O 16
TMS/NC
RESET/Y1
VCC

1

TCK/Y2
I/O 15
I/O 14
I/O 13
I/O 12

44PLCC/2032E

2

1

I/O 28
I/O 29
I/O 30
I/O 31

BSCAN

1

TDI/IN 0

1
2
3
4
5

Y0

VCC

6
7
8

I/O 0

9

I/O 1

10

I/O 2

11

1. Pins have dual function capability.

2. NC pins are not to be connected to any active signals, VCC or GND.

ispLSI 2032E

Top View

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

GND

I/O 8

TDO/IN 1

1

I/O 9

22

I/O 10

I/O 11

33
32
31
30
29
28
27
26
25
24
23

12

I/O 18
I/O 17
I/O 16
TMS/NC
RESET/Y1
VCC

1

TCK/Y2
I/O 15
I/O 14
I/O 13
I/O 12

44TQFP/2032E

2

1

Pin Configuration

ispLSI 2032E 48-Pin TQFP Pinout Diagram

VCCIO

471346144515441643174218411940203921382237

48

I/O 28
I/O 29
I/O 30
I/O 31

BSCAN

1

TDI/IN 0

1
2
3
4
5

Y0

6

VCC

7
8
9

I/O 0

10

I/O 1

11

I/O 2
GND 12

I/O 27

I/O 26

I/O 25

I/O 24

GOE 0

GND

I/O 23

ispLSI 2032E

Top View

Specifications ispLSI 2032E

I/O 22

I/O 21

I/O 20

I/O 19

GND36

35

I/O 18

34

I/O 17

33

I/O 16

2

TMS/NC
RESET/Y1
VCC

1

TCK/Y2
I/O 15
I/O 14
I/O 13
I/O 12

1

23

32
31
30
29
28
27
26
25

24

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

1. Pins have dual function capability.

2. NC pins are not to be connected to any active signals, V

GND

TDO/IN 1

1

I/O 8

I/O 9

I/O 10

I/O 11

VCCIO

or GND.

CC

48TQFP/2032E

13

Part Number Description

Specifications ispLSI 2032E

ispLSI 2032E XXX X XXX

Device Family

Device Number
Speed

225 = 225 MHz fmax
200 = 200 MHz fmax
180 = 180 MHz fmax
135 = 135 MHz fmax
110 = 110 MHz fmax

ispLSI 2032E Ordering Information

FAMILY fmax (MHz)

225
225
225

200 3.5
180 44-Pin PLCC5.0 ispLSI 2032E-180LJ44

180

ispLSI

*2032E-225 recommended for new designs.

180
135
135
135
110 44-Pin PLCC10.0
110
110

tpd (ns)

3.5

3.5

3.5

5.0

7.5

7.5

7.5

10.0

–

COMMERCIAL

ORDERING NUMBER PACKAGE

ispLSI 2032E-225LJ44

ispLSI 2032E-225LT44

ispLSI 2032E-200LT48*

ispLSI 2032E-180LT44

ispLSI 2032E-135LJ44

ispLSI 2032E-135LT44

ispLSI 2032E-110LJ44
ispLSI 2032E-110LT44

X

Grade

Blank = Commercial

Package

J44 = PLCC
T44 = TQFP
T48 = TQFP

Power

L = Low

0212/2032E

44-Pin PLCC
44-Pin TQFP
48-Pin TQFPispLSI 2032E-225LT48

48-Pin TQFP

44-Pin TQFP5.0
48-Pin TQFPispLSI 2032E-180LT48
44-Pin PLCC
44-Pin TQFP
48-Pin TQFPispLSI 2032E-135LT48

44-Pin TQFP10.0
48-Pin TQFPispLSI 2032E-110LT48

Table 2-0041/2032E

14