Lattice ispLSI 2032E User Manual

ispLSI® 2032E

In-System Programmable

SuperFAST™ High Density PLD

Features

• SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 1000 PLD Gates
— 32 I/O Pins, Two Dedicated Inputs
— 32 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functionally and JEDEC Upward Compatible

with ispLSI 2032 Devices

2

• HIGH PERFORMANCE E

— fmax = 225 MHz Maximum Operating Frequency
— tpd = 3.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— 5V Programmable Logic Core
— ispJTAG™ In-System Programmable via IEEE 1149.1

(JTAG) Test Access Port
— User-Selectable 3.3V or 5V I/O (48-Pin Package Only)

Supports Mixed Voltage Systems
— PCI Compatible Outputs (48-Pin Package Only)
— Open-Drain Output Option
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Unused Product Term Shutdown Saves Power

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to

Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global

Interconnectivity

CMOS® TECHNOLOGY

Functional Block Diagram

GLB

Global Routing Pool

(GRP)

DQ

DQ

Logic
Array

DQ

DQ

A7

A6

A5

A4

Input Bus

Output Routing Pool (ORP)

0139Bisp/2000

A0

A1

Input Bus

A2

Output Routing Pool (ORP)

A3

Description

The ispLSI 2032E is a High Density Programmable Logic
Device. The device contains 32 Registers, 32 Universal
I/O pins, two Dedicated Input Pins, three Dedicated
Clock Input Pins, one dedicated Global OE input pin and
a Global Routing Pool (GRP). The GRP provides com­plete interconnectivity between all of these elements.
The ispLSI 2032E features 5V in-system programmabil­ity and in-system diagnostic capabilities. The ispLSI
2032E offers non-volatile reprogrammability of the logic,
as well as the interconnect to provide truly reconfigurable
systems.

The basic unit of logic on the ispLSI 2032E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. A7 (see Figure 1). There are a total of eight GLBs in the
ispLSI 2032E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.

The device also has 32 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually

Copyright © 2003 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

2032e_05 1

November 2003

Functional Block Diagram

E

Figure 1. ispLSI 2032E Functional Block Diagram

GOE 0

Specifications ispLSI 2032E

I/O 0
I/O 1
I/O 2
I/O 3

I/O 4
I/O 5
I/O 6
I/O 7

I/O 8

I/O 9
I/O 10
I/O 11

I/O 12
I/O 13
I/O 14
I/O 15

TDI/IN 0

TDO/IN 1

TMS

BSCAN

Notes:
*Y1 and RESET are multiplexed on the same pin

A0

A1

Input Bus

A2

Output Routing Pool (ORP)

A3

Global Routing Pool

programmed to be a combinatorial input, output or bi­directional I/O pin with 3-state control. The signal levels
are TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA. Each output can be pro­grammed independently for fast or slow output slew rate
to minimize overall output switching noise. By connecting
the VCCIO pins to a common 5V or 3.3V power supply,
I/O output levels can be matched to 5V or 3.3V compat­ible voltages. When connected to a 5V supply, the I/O
pins provide PCI-compatible output drive (48-pin device
only).

Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the ORP. Each ispLSI
2032E device contains one Megablock.

The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.

I/O 31

Input Bus

0139/2032

I/O 30
I/O 29
I/O 28

I/O 27
I/O 26
I/O 25
I/O 24

I/O 23
I/O 22
I/O 21
I/O 20

I/O 19
I/O 18
I/O 17
I/O 16

(GRP)

Y1*

TCK/Y2

A7

A6

A5

Output Routing Pool (ORP)

A4

CLK 1

CLK 2

CLK 0

Y0

Clocks in the ispLSI 2032E device are selected using the
dedicated clock pins. Three dedicated clock pins (Y0, Y1,
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the
outputs of the ispLSI 2032E are individually program­mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro­grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the Lattice software tools.

2

Specifications ispLSI 2032E

Absolute Maximum Ratings

1

Supply Voltage Vcc.................................. -0.5 to +7.0V

Input Voltage Applied........................-2.5 to VCC +1.0V

Off-State Output Voltage Applied .....-2.5 to VCC +1.0V

Storage Temperature................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (TJ) with Power Applied ... 150°C

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Condition

SYMBOL

V

CC
CCIO

IL
IH

1

V
V

V

1. 3.3V I/O operation not available for 44-pin packages.

Supply Voltage: Logic Core, Input Buffers
Supply Voltage: Output Drivers

Input Low Voltage
Input High Voltage

PARAMETER

5V

3.3V

TA = 0°C to +70°C

MIN. MAX. UNITS

4.75

4.75 5.25 V

3.0 3.6 V
0

2.0

5.25

0.8

V

cc

+1

V

V
V

Table 2-0005/2032E

Capacitance (TA=25°C, f=1.0 MHz)

SYMBOL

C

1

C

2

C

3

Dedicated Input Capacitance
I/O Capacitance
Clock Capacitance

PARAMETER

Erase/Reprogram Specification

PARAMETER MINIMUM MAXIMUM UNITS

Erase/Reprogram Cycles

TYP

10

10,000 – Cycles

UNITS TEST CONDITIONS

6
7

pf
pf
pf V = 5.0V, V = 2.0V

V = 5.0V, V = 2.0V

CC

V = 5.0V, V = 2.0V

CC I/O

CC Y

IN

Table 2-0006/2032E

Table 2-0008/2032E

3

Switching Test Conditions

Specifications ispLSI 2032E

Input Pulse Levels
Input Rise and Fall Time 10% to 90%

Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.5V from

steady-state active level.

GND to 3.0V

1.5 ns

1.5V

1.5V

See Figure 2

Table 2-0003/2032E

Figure 2. Test Load

Device
Output

+ 5V

R

1

R

2

*

C

L

Output Load Conditions (see Figure 2)

*

TEST CONDITION R1 R2 CL

CL includes Test Fixture and Probe Capacitance.

A 470Ω 390Ω 35pF

Active High

B

Active Low
Active High to Z

at V -0.5V

C

Active Low to Z
at V +0.5V

OH

OL

∞ 390Ω 35pF

470Ω 390Ω 35pF

∞ 390Ω 5pF

470Ω 390Ω 5pF

Table 2 - 0004A

DC Electrical Characteristics

Over Recommended Operating Conditions

SYMBOL

VOL
VOH
IIL

IIH

IIL-PU

1

IOS

2,4,6

ICC

Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current

Input or I/O High Leakage Current

I/O Active Pull-Up Current, non-PCI
I/O Active Pull-Up Current, PCI

Output Short Circuit Current, non-PCI
Output Short Circuit Current, PCI

Operating Power Supply Current

PARAMETER

I

= 8 mA

OL

= -4 mA

I

OH

0V ≤ V

IN

- 0.2)V ≤ VIN ≤ V

(V

CCIO

≤ V

V

CCIO

0V ≤ V

5

5

IN

0V ≤ VIN ≤ 2.0V -10 – -250 µA

= 5V, V

V

CCIO

V

= 5.0V or 3.3V, V

CCIO

V

= 0.0V, VIH = 3.0V

IL

f

TOGGLE

1. One output at a time for a maximum duration of one second (V

2. Meaured using two 16-bit counters.

3. Typical values are at V

= 5V and TA = 25°C.

CC

4. Unused inputs held at 0.0V.

5. Available in 48-pin package only.

6. Maximum I

varies widely with specific device configuration and operating frequency. Refer to the

CC

Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor
Data Book or CD-ROM to estimate maximum I

CC

.

CONDITION MIN. TYP.

≤ VIL (Max.)

CCIO

≤ 5.25V

IN

≤ 2.0V

= 0.5V

OUT

= 0.5V – – -240 mA

OUT

-225/-200

= 1 MHz

= 0.5V). Characterized, but not 100% tested.

OUT

Others mA–

1

–

2.4
–
–
–

-10

–

–85 mA–
–65

3

–
–
–
–
–
–

–

MAX. UNITS

0.4
–

-10

10
10

-150

-200

Table 2-0007/2032E

Test

Point

0213A

V
V

µA
µA
µA
µA

mA

4

External Timing Parameters

Over Recommended Operating Conditions

Specifications ispLSI 2032E

PARAMETER

tpd1
tpd2
fmax

fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl

1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-bit counter using GRP feedback.

4. Reference Switching Test Conditions section.

TEST

COND.

A1Data Prop. Delay, 4PT Bypass, ORP Bypass – 3.5 – 5.0 ns
A2Data Prop. Delay – – ns
A3Clk Frequency with Int. Feedback

–4Clk Frequency with Ext. Feedback – – MHz
–5Clk Frequency, Max. Toggle – – MHz
–6GLB Reg. Setup Time before Clk, 4 PT Bypass – – ns
A7GLB Reg. Clk to Output Delay, ORP Bypass – – ns
–8GLB Reg. Hold Time after Clk, 4 PT Bypass 0.0 – ns
–9GLB Reg. Setup Time before Clk 3.5 – ns
–10GLB Reg. Clk to Output Delay – – ns
–11GLB Reg. Hold Time after Clk 0.0 – ns
A12Ext. Reset Pin to Output Delay, ORP Bypass – – ns
–13Ext. Reset Pulse Duration 3.5 – ns
B14Input to Output Enable – – ns
C15Input to Output Disable – – ns
B16Global OE Output Enable – – ns
C17Global OE Output Disable – – ns
–18Ext. Synch. Clk Pulse Duration, High 2.0 – – ns
–19Ext. Synch. Clk Pulse Duration, Low 2.0 – – ns

2

4

DESCRIPTION#

1

3

( )

1
tsu2 + tco1

-225

MIN. MAX.

– 3.5
–

5.5

225 –

2.5
–

2.5

0.0

3.5
–

3.5

0.0
–

5.0

3.5
–

7.0

–

7.0

–

3.5

–

3.5

2.0 –

2.0 –

–
–
–

–
–

–

–

167
250

-200

MIN.

200 – 180 – MHz
167
250

2.5

USE 2032E-225 FOR

MIN.MAX. MAX.

5.5

125
200

3.0

2.5
–

0.0

–

4.0

3.5
–

0.0

5.0
–

4.0

7.0

NEW DESIGNS

7.0

3.5

3.5

2.5

2.5

-180
UNITS

7.5

4.0

4.5

6.5

10.0

10.0

5.0

5.0

Table 2-0030A/2032E

5