Lattice ispLSI 1048E User Manual

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• HIGH DENSITY PROGRAMMABLE LOGIC
— 8,000 PLD Gates
— 96 I/O Pins, Twelve Dedicated Inputs
— 288 Registers

— High-Speed Global Interconnects
— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Functionally and Pin-out Compatible to ispLSI 1048C

2

• HIGH PERFORMANCE E
—

fmax = 125 MHz Maximum Operating Frequency
tpd = 7.5 ns Propagation Delay

—
— TTL Compatible Inputs and Outputs
— Electrically Eraseable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture

• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to

Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispLSI DEVELOPMENT TOOLS
ispVHDL™ Systems

— VHDL/Verilog-HDL/Schematic Design Options
— Functional/Timing/VHDL Simulation Options

ispDS+™ VHDL Synthesis-Optimized Logic Fitter
— Supports Leading Third-Party Design Environments

for Schematic Capture, Synthesis and Timing
Simulation

— Static Timing Analyzer
ispDS™ Software
— Lattice HDL or Boolean Logic Entry

— Functional Simulator and Waveform Viewer
ISP Daisy Chain Download Software

CMOS® TECHNOLOGY

ispLSI® 1048E

High-Density Programmable Logic

Functional Block DiagramFeatures

Output Routing Pool

F7 F6 F5 F4 F3 F2 F1 F0

A0
A1
A2
A3

Global Routing Pool (GRP) GLB

A4
A5

Output Routing Pool

A6
A7

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

Description

The ispLSI 1048E is a High-Density Programmable Logic
Device containing 288 Registers, 96 Universal I/O pins,
12 Dedicated Input pins, four Dedicated Clock Input pins,
two dedicated Global OE input pins, and a Global Routing
Pool (GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1048E fea­tures 5V in-system programmability and in-system
diagnostic capabilities. The ispLSI 1048E offers non­volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems. A
functional superset of the ispLSI 1048 architecture, the
ispLSI 1048E device adds two new global output enable
pins and two additional dedicated inputs.

The basic unit of logic on the ispLSI 1048E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…F7 (see Figure 1). There are a total of 48 GLBs in the
ispLSI 1048E device. Each GLB has 18 inputs, a pro­grammable AND/OR/Exclusive OR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.

Output Routing Pool

E7 E6 E5 E4 E3 E2 E1 E0

DQ

DQ

Logic
Array

DQ

DQ

C0 C1 C2 C3 C4 C5 C6 C7

Output Routing Pool

D7
D6
D5
D4
D3
D2

Output Routing Pool

D1
D0

CLK

0139G1A-isp

Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. July 1998
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

1048E_08

1

Functional Block Diagram

Figure 1. ispLSI 1048E Functional Block Diagram

Specifications ispLSI 1048E

RESET

GOE 0

GOE 1

I/O 0
I/O 1
I/O 2
I/O 3

I/O 4
I/O 5
I/O 6
I/O 7

I/O 8

I/O 9
I/O 10
I/O 11

I/O 12
I/O 13
I/O 14
I/O 15

SDI/IN 0

MODE/IN 1

ispEN/NC

Generic

Logic Blocks

Input Bus

Output Routing Pool (ORP)

Megablock

(GLBs)

A0

A1

A2

A3

A4

A5

A6

A7

IN 2

I/O94I/O95I/O93I/O92I/O91I/O90I/O89I/O88I/O87I/O86I/O85I/O84I/O83I/O82I/O81I/O

Input Bus

Output Routing Pool (ORP)

F7 F6 F5 F4 F3 F2 F1 F0

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool (ORP)

Input Bus

SDO/

I/O17I/O16I/O18I/O19I/O20I/O21I/O22I/O23I/O24I/O25I/O26I/O27I/O28I/O29I/O30I/O

IN 3

80

Routing

31

IN

IN

11

10

I/O78I/O79I/O77I/O76I/O75I/O74I/O73I/O72I/O71I/O70I/O69I/O68I/O67I/O66I/O65I/O

Output Routing Pool (ORP)

E7 E6 E5 E4 E3 E2 E1 E0

Global

Pool

(GRP)

C0 C1 C2 C3 C4 C5 C6 C7

Output Routing Pool (ORP)

Input Bus

I/O33I/O32I/O34I/O35I/O36I/O37I/O38I/O39I/O40I/O41I/O42I/O43I/O44I/O45I/O46I/O

SCLK/

IN 5IN4

Input Bus

IN

IN

9

64

8

IN 7
IN 6

lnput Bus

I/O 63
I/O 62
I/O 61
I/O 60

I/O 59
I/O 58
I/O 57
I/O 56

I/O 55
I/O 54
I/O 53
I/O 52

I/O 51
I/O 50
I/O 49
I/O 48

D7

D6

D5

D4

D3

D2

Output Routing Pool (ORP)

D1

D0

CLK 0
CLK 1

Clock

Network

Y0Y1Y2Y

CLK 2
IOCLK 0
IOCLK 1

0139F(2)-48B-isp

3

Distribution

47

The device also has 96 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in­put, latched input, output or bi-directional
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source 4
mA or sink 8 mA. Each output can be programmed
independently for fast or slow output slew rate to mini­mize overall output switching noise.

Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected to
a set of 16 universal I/O cells by the ORP. Each ispLSI
1048E device contains six Megablocks.

The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.

Clocks in the ispLSI 1048E device are selected using the
Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (D0). The logic
of this GLB allows the user to create an internal clock
from a combination of internal signals within the device.

2

Specifications ispLSI 1048E

Absolute Maximum Ratings

1

Supply Voltage Vcc. ................................. -0.5 to +7.0V

Input Voltage Applied........................-2.5 to VCC +1.0V

Off-State Output Voltage Applied .....-2.5 to VCC +1.0V

Storage Temperature................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (TJ) with Power Applied ... 150°C

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Conditions

V
V

V

CC

IL
IH

SYMBOL

Supply Voltage

Input Low Voltage
Input High Voltage

PARAMETER

Commercial
Industrial

TA = 0°C to + 70°C

= -40°C to + 85°C

T

A

MIN. MAX. UNITS

4.75

4.5
0

2.0

5.25

5.5

0.8

V

cc

+1

V
V
V
V

Table 2-0005/1048E

Capacitance (TA=25oC, f=1.0 MHz)

SYMBOL

C

1

C

2

Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
Y0 Clock Capacitance

PARAMETER

Data Retention Specifications

PARAMETER

Data Retention
Erase/Reprogram Cycles

UNITSTYPICAL TEST CONDITIONS

8

15

MINIMUM MAXIMUM UNITS

20

10000

pf
pf

–
–

V = 5.0V, V = 2.0V

CC

V = 5.0V, V = 2.0V

CC PIN

PIN

Table 2-0006/1048E

Years

Cycles

Table 2-0008/1048E

3

Switching Test Conditions

Specifications ispLSI 1048E

Input Pulse Levels
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load

3-state levels are measured 0.5V from
steady-state active level.

GND to 3.0V

≤ 3 ns 10% to 90%

1.5V

1.5V

See Figure 2

Table 2-0003/1048E

Output Load Conditions (see Figure 2)

TEST CONDITION R1 R2 CL

A 470Ω 390Ω 35pF

Active High

B

Active Low
Active High to Z

at V -0.5V

C

Active Low to Z
at V +0.5V

OH

OL

∞ 390Ω 35pF

470Ω 390Ω 35pF

∞ 390Ω 5pF

470Ω 390Ω 5pF

Table 2-0004a

Figure 2. Test Load

+ 5V

R

1

Device
Output

R

2

*

CL includes Test Fixture and Probe Capacitance.

*

C

L

Test

Point

0213a

DC Electrical Characteristics

Over Recommended Operating Conditions

–
–
–
–
–
–

–
175
175

3

0.4
–

-10

10

-150

-150

-200
–
–

Table 2-0007/1048E

µA
µA
µA
µA

mA
mA
mA

SYMBOL

V

OL

V

OH

I

IL

I

IH

I

IL-isp

I

IL-PU

1

I

OS

2, 4

I

CC

Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
ispEN Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current

Operating Power Supply Current

PARAMETER

I = 8 mA

OL

I = -4 mA

OH

0V ≤ V ≤ V (Max.)

IN IL

3.5V ≤ V ≤ V
0V ≤ V ≤ V
0V ≤ V ≤ V
V = 5V, V = 0.5V

V = 0.0V, V = 3.0V
f = 1 MHz

CLOCK

IN CC

IN

IN IL

CC OUT

IL

1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test problems

CONDITION MIN. TYP. MAX. UNITS

–

2.4
–
–

IL

–
–
–

IH

Commercial
Industrial

OUT

–
–

by tester ground degradation. Characterized but not 100% tested.

2. Measured using twelve 16-bit counters.

3. Typical values are at V = 5V and T = 25°C.

4. Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption

CC

CC A

section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I .

CC

V
V

4

External Timing Parameters

Over Recommended Operating Conditions

Specifications ispLSI 1048E

PARAMETER

tpd1
tpd2
fmax (Int.)
fmax (Ext.)
fmax (Tog.)
tsu1

tco1
th1
tsu2

tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis

4

TEST

COND.

A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 10.0 ns
A 2 Data Propagation Delay, Worst Case Path – ns
A 3 Clock Frequency with Internal Feedback 90.9 – MHz
– 4 Clock Frequency with External Feedback – MHz
– 5 Clock Frequency, Max. Toggle – MHz
– 6 GLB Reg. Setup Time before Clock,4 PT Bypass – ns

A 7 GLB Reg. Clock to Output Delay, ORP Bypass – ns
– 8 GLB Reg. Hold Time after Clock, 4 PT Bypass – ns
– 9 GLB Reg. Setup Time before Clock – ns

– 10 GLB Reg. Clock to Output Delay – ns
– 11 GLB Reg. Hold Time after Clock – ns
A 12 Ext. Reset Pin to Output Delay – ns
– 13 Ext. Reset Pulse Duration – ns
B 14 Input to Output Enable – ns
C 15 Input to Output Disable – ns
B 16 Global OE Output Enable – ns9.0
C 17 Global OE Output Disable – ns

2

DESCRIPTION#

1

1

( )

twh + twl

3

1

( )

tsu2 + tco1

twh – 18 External Synchronous Clock Pulse Duration, High 4.0 ns
twl
tsu3

th3

1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-bit counter using GRP feedback.

4. Reference Switching Test Conditions section.

– 19 External Synchronous Clock Pulse Duration, Low 4.0 ns
– 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) – ns

– 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) – ns

-125

MIN. MAX.

– 7.5

–

10.0

125.0 –

91.0

167.0

–
–
–

5.5
–

4.5

0.0

–

6.5

–

–

5.5

0.0

–

–

10.0

5.0

–

–

12.0

–

12.0
– 7.0
– 7.0 9.0

3.0

–

3.0

–

3.0 –

0.0 –

-100

MIN. MAX.

– 10.0

–

12.5

100.0 –

6.5
–

0.0

7.5
–

0.0
–

6.5
–
–
– 9.0
– 9.0

4.0

4.0

3.5

0.0

–
–
–

6.5
–
–

7.5
–

13.5
–

15.0

15.0

–
–

–
–

71.0

125.0

MIN. MAX.

71.0

125.0

6.5

0.0

7.5

0.0

6.5

USE 1048E-100 FOR

4.0

0.0

-90

12.5

6.5

7.5

13.5

15.0

NEW DESIGNS

15.0

–
–

Table 2-0030A/1048E

UNITS

5