ispLSI ® 1024/883
In-System Programmable High Density PLD
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— High-Speed Global Interconnect
— 4000 PLD Gates
— 48 I/O Pins, Six Dedicated Inputs
— 144 Registers
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Fast Random Logic
— Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E
—
fmax = 60 MHz Maximum Operating Frequency
— tpd = 20 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E
— 100% Tested
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
unctional
Block Diagram
2
2
CMOS® TECHNOLOGY
CMOS Technology
Functional Block Diagram
A0
A1
A2
A3
A4
A5
A6
Output Routing Pool
Global Routing Pool (GRP)
A7
B0 B1 B2 B3 B4 B5 B6 B7
Logic
Array
Output Routing Pool
DQ
DQ
DQ
DQ
GLB
C7
C6
C5
C4
C3
C2
C1
Output Routing Pool
C0
CLK
0139-A-isp
Description
The ispLSI 1024/883 is a High-Density Programmable
Logic Device processed in full compliance to MIL-STD-
883. This military grade device contains 144 Registers,
48 Universal I/O pins, six Dedicated Input pins, four
Dedicated Clock Input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1024/883
features 5-Volt in-system programmability and in-system
diagnostic capabilities. It is the first device which offers
non-volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 1024/883 device is
the Generic Logic Block (GLB). The GLBs are labeled A0,
A1 .. C7 (see figure 1). There are a total of 24 GLBs in the
ispLSI 1024/883 device. Each GLB has 18 inputs, a
programmable AND/OR/XOR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. September 2000
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
1024MIL_01
1
Functional Block Diagram
Figure 1.ispLSI 1024/883 Functional Block Diagram
RESET
Generic
Logic Blocks
(GLBs)
Specifications ispLSI 1024/883
IN 5
IN 4
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
SDI/IN 0
SDO/IN 1
ispEN
Input Bus
Megablock
SCLK/IN 2
MODE/IN 3
A0
A1
A2
A3
A4
A5
Output Routing Pool (ORP)
A6
A7
Global
Routing
Pool
(GRP)
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool (ORP)
Input Bus
I/O17I/O16I/O18I/O19I/O20I/O21I/O22I/O23I/O24I/O25I/O26I/O27I/O28I/O29I/O30I/O
lnput Bus
0139D_1024.eps
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
C7
C6
C5
C4
C3
C2
C1
C0
Clock
Distribution
Network
31
Y0Y1Y2Y
Output Routing Pool (ORP)
3
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
The device also has 48 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered input, latched input, output or bi-directional
I/O pin with 3-state control. Additionally, all outputs are
polarity selectable, active high or active low. The signal
levels are TTL compatible voltages and the output drivers
can source 4 mA or sink 8 mA.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected
to a set of 16 universal I/O cells by the ORP. The I/O cells
within the Megablock also share a common Output
Enable (OE) signal. The ispLSI 1024/883 device contains three of these Megablocks.
The GRP has as its inputs the outputs from all of the GLBs
and all of the inputs from the bi-directional I/O cells. All of
these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1024/883 device are selected using
the Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (B4 on the ispLSI
1024/883 device). The logic of this GLB allows the user
to create an internal clock from a combination of internal
signals within the device.
2
Specifications ispLSI 1024/883
SYMBOL PARAMETER MAXIMUM
1
UNITS TEST CONDITIONS
C
1
10 pf V
CC
=5.0V, VIN=2.0V
C
2
I/O and Clock Capacitance 10 pf VCC=5.0V, V
I/O
, VY=2.0V
1. Characterized but not 100% tested.
Table 2- 0006mil
Dedicated Input Capacitance
Absolute Maximum Ratings
1
Supply Voltage Vcc...................................-0.5 to +7.0V
Input Voltage Applied........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
PARAMETERSYMBOL MIN. MAX. UNITS
V
V
V
CC
IL
IH
Supply Voltage
Input Low Voltage
Input High Voltage
Military/883 T
= -55°C to +125°C
C
4.5
0
2.0
5.5
0.8
Vcc + 1
V
V
V
0005A mil.eps
Capacitance (TA=25oC, f=1.0 MHz)
Data Retention Specifications
PARAMETER
Data Retention
Erase/Reprogram Cycles
MINIMUM MAXIMUM UNITS
20
10000
—
—
Years
Cycles
Table 2- 0008B
3
Switching Test Conditions
-
Specifications ispLSI 1024/883
Input Pulse Levels GND to 3.0V
Input Rise and Fall Time ≤ 3ns 10% to 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See figure 2
3-state levels are measured 0.5V from steady-state
active level.
Table 2- 0003
Output Load Conditions (see figure 2)
Test Condition R1 R2 CL
A 470Ω 390Ω 35pF
B Active High 390Ω 35pF
Active Low 470Ω 390Ω 35pF
Active High to Z 390Ω 5pF
Cat V
- 0.5V
OH
Active Low to Z 470Ω 390Ω 5pF
+ 0.5V
at V
OL
∞
∞
Table 2- 0004A
Figure 2. Test Load
Device
Output
*C
includes Test Fixture and Probe Capacitance.
L
+ 5V
R
1
Test
Point
R
2
*
C
L
DC Electrical Characteristics
Over Recommended Operating Conditions
–
–
–
–
–
–
–
135
3
UNITSTYP.
0.4
–
-10
10
-150
-150
-200
215
0007A-24 mil
SYMBOL
V
OL
V
OH
I
IL
I
IH
I
IL-isp
I
IL-PU
1
I
OS
2,4
I
CC
Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
isp Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
PARAMETER
IOL =8 mA
=-4 mA
I
OH
0V ≤ V
3.5V ≤ V
0V ≤ VIN ≤ VIL (MAX.)
0V ≤ V
VCC = 5V, V
= 0.5V, V
V
IL
f
TOGGLE
1. One output at a time for a maximum duration of one second. V
degradation. Characterized but not 100% tested.
CONDITION
≤ VIL (MAX.)
IN
≤ V
IN
CC
≤ V
IN
IL
= 0.5V
OUT
= 3.0V
IH
= 1 MHz
MIN. MAX.
–
2.4
–
–
–
–
–
–
= 0.5V was selected to avoid test problems by tester ground
out
2. Measured using six 16-bit counters.
3. Typical values are at V
4. Maximum I
varies widely with specific device configuration and operating frequency . Refer to the Power Consumption sec
CC
= 5V and TA = 25oC.
CC
tion of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum
.
I
CC
V
V
µA
µA
µA
µA
mA
mA
4
External Timing Parameters
Specifications ispLSI 1024/883
Over Recommended Operating Conditions
5
PARAMETER #
t
pd1
t
pd2
f
max (Int.)
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
en
t
dis
t
wh
t
wl
t
su5
t
h5
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-Bit loadable counter using GRP feedback.
4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions Section.
TEST
COND.
2
DESCRIPTION
Data Propagation Delay, 4PT bypass, ORP bypass
1
A
Data Propagation Delay, Worst Case Path
2
A
Clock Frequency with Internal Feedback
3
A
Clock Frequency with External Feedback
4
–
Clock Frequency, Max Toggle
5
–
GLB Reg. Setup Time before Clock, 4PT bypass
6
–
GLB Reg. Clock to Output Delay, ORP bypass
7
A
GLB Reg.
8
–
GLB Reg. Setup Time before Clock
9
–
GLB Reg. Clock to Output Delay
10
–
GLB Reg. Hold Time after Clock
11
–
Ext. Reset Pin to Output Delay
12
A
Ext. Reset Pulse Duration
13
–
Input to Output Enable
14
B
Input to Output Disable
15
C
Ext. Sync. Clock Pulse Duration, High
16
–
Ext. Sync. Clock Pulse Duration, Low
17
–
I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)
18
–
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
19
–
1
3
( )
4
Hold Time after Clock, 4 PT bypass
tsu2 + tco1
1
-60
MIN. MAX.
–
20
–
25
60
–
38
–
83
–
9
–
–
13
0
–
13
–
–
16
0
–
–
22.5
13
–
–
24
–
24
6
–
6
–
2.5
–
8.5
–
Table 2-0030-24 mil
UNITS
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
Specifications ispLSI 1024/883
Internal Timing Parameters
2
DESCRIPTIONPARAMETER UNITS
#
Inputs
iobp
t
tiolat
tiosu
tioh
tioco
tior
tdin
I/O Register Bypass
20
I/O Latch Delay
21
I/O Register Setup Time before Clock
22
I/O Register Hold Time after Clock
23
I/O Register Clock to Out Delay
24
I/O Register Reset to Out Delay
25
Dedicated Input Delay
26
GRP
grp1
t
tgrp4
tgrp8
tgrp12
tgrp16
tgrp24
GRP Delay, 1 GLB Load
27
GRP Delay, 4 GLB Loads
28
GRP Delay, 8 GLB Loads
29
GRP Delay, 12 GLB Loads
30
GRP Delay, 16 GLB Loads
31
GRP Delay, 24 GLB Loads
32
1
-60
MIN. MAX.
2.7
–
–
7.3
1.3
–
–
–
–
–
–
–
–
–
4.0
–
–
4.0
3.3
5.3
2.0
2.7
4.0
5.0
6.0
8.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GLB
t
4ptbp
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgr
tptre
tptoe
tptck
4 Product Term Bypass Path Delay
33
1 Product Term/XOR Path Delay
34
20 Product Term/XOR Path Delay
35
XOR Adjacent Path Delay
36
GLB Register Bypass Delay
37
GLB Register Setup Time before Clock
38
GLB Register Hold Time after Clock
39
GLB Register Clock to Output Delay
40
GLB Register Reset to Output Delay
41
GLB Product Term Reset to Register Delay
42
GLB Product Term Output Enable to I/O Cell Delay
43
GLB Product Term Clock Delay
44
3
ORP
t
orp
torpbp
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Lattice Hard Macros.
ORP Delay
45
ORP Bypass Delay
46
–
–
–
–
–
1.3
6.0
–
–
–
–
4.6
–
–
8.6
9.3
10.6
12.7
1.3
–
–
2.7
3.3
13.3
12.0
9.9
3.3
0.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
Specifications ispLSI 1024/883
Internal Timing Parameters
2
DESCRIPTIONPARAMETER UNITS
#
1
Outputs
t
t
t
ob
oen
odis
Output Buffer Delay
47
I/O Cell OE to Output Enabled
48
I/O Cell OE to Output Disabled
49
Clocks
gy0
t
t
gy1/2
t
gcp
t
ioy2/3
t
iocp
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
50
Clock Delay, Y1 or Y2 to Global GLB Clock Line
51
Clock Delay, Clock GLB to Global GLB Clock Line
52
Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
53
Clock Delay, Clock GLB to I/O Cell Global Clock Line
54
Global Reset
t
gr
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
Global Reset to GLB and I/O Registers
55
-60
MIN. MAX.
4.0
–
6.7
–
6.7
–
6.0
6.0
7.3
4.6
6.6
1.3
7.3
4.6
6.6
1.3
12.0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
ispLSI Timing Model
Specifications ispLSI 1024/883
I/O CellORPGLBGRPI/O Cell
Feedback
Ded. In
I/O Pin
(Input)
#55
Reset
Y1,2,3
Y0
#26
I/O Reg Bypass
#20
Input
Register
D
RST
Q
#21 - 25
GRP 4
#28
GRP
Loading
Delay
#27, 29,
30, 31, 32
Clock
Distribution
#51, 52,
53, 54
#50
4 PT Bypass
#33
20 PT
XOR Delays
#34, 35, 36
#55
Control
RE
PTs
OE
CK
#42, 43,
44
Derivations of tsu, th and tco from the Product Term Clock
t
su = Logic + Reg su - Clock (min)
=
(t
iobp + tgrp4 + t20ptxor) + (tgsu
= (#20 + #28 + #35) + (#38
) - (
7.3 ns = (2.7 + 2.7 + 10.6) + (1.3) - (2.7 + 2.7 + 4.6)
t
h = Clock (max) + Reg h - Logic
=
(t
iobp + tgrp4 + tptck(max)) + (tgh
= (#20 + #28 + #44) + (#39
) - (
5.3 ns = (2.7 + 2.7 + 9.9) + (6.0) - (2.7 + 2.7 + 10.6)
t
co = Clock (max) + Reg co + Output
= (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob
= (#20 + #28 + #44) + (#40) + (#45 + #47
25.3 ns = (2.7+ 2.7 +9.9) + (2.7) + (3.3 + 4.0)
) - (t
iobp + tgrp4 + tptck(min)
#20 + #28 + #44
) - (t
iobp + tgrp4 + t20ptxor
#20 + #28 + #35
)
)
)
)
GLB Reg Bypass ORP Bypass
#37
GLB Reg
Delay
DQ
RST
#38, 39,
40, 41
1
)
)
#46
ORP
Delay
#45
#47
I/O Pin
(Output)
#48, 49
Derivations of tsu, th and tco from the Clock GLB
t
su = Logic + Reg su - Clock (min)
=
(t
iobp + tgrp4 + t20ptxor) + (tgsu
= (#20 + #28 + #35) + (#38
) - (
) - (t
#50 + #40 + #52
1
gy0(min) + tgco + tgcp(min)
)
7.3 ns = (2.7 + 2.7 + 10.6) + (1.3) - (6.0 + 2.7 + 1.3)
t
h = Clock (max) + Reg h - Logic
(t
gy0(max) + tgco + tgcp(max)) + (tgh
=
= (#50 + #40 + #52) + (#39
) - (
#20 + #28 + #35
) - (t
iobp + tgrp4 + t20ptxor
)
5.3 ns = (6.0 + 2.7 + 6.6) + (6.0) - (2.7 + 2.7 + 10.6)
t
co = Clock (max) + Reg co + Output
(t
gy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob
=
= (#50 + #40 + #52) + (#40) + (#45 + #47
)
)
25.3 ns = (6.0 + 2.7 + 6.6) + (2.7) + (3.3 + 4.0)
1. Calculations are based upon timing specifications for the ispLSI 1024-60.
8
)
)
Maximum GRP Delay vs GLB Loads
Specifications ispLSI 1024/883
6
5
4
3
2
GRP Delay (ns)
1
0
4 8 12 16
GLB Loads
Power Consumption
Power consumption in the ispLSI 1024/883 device depends on two primary factors: the speed at which the
device is operating, and the number of Product Terms
Figure 3. Typical Device Power Consumption vs fmax
200
ispLSI 1024-60
0126A-80-24-mil.eps
used. Figure 3 shows the relationship between power
and operating speed.
ispLSI 1024
150
100
CC (mA)
I
50
0 10203040506070
f
max (MHz)
Notes: Configuration of Six 16-bit Counters
Typical Current at 5V, 25˚C
ICC can be estimated for the ispLSI 1024 using the following equation:
ICC = 42 + (# of PTs * 0.45) + (# of nets * Max. freq * 0.008) where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The I
average exists. These values are for estimates only. Since the value of I
program in the device, the actual I
estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on
CC
should be verified.
CC
80
is sensitive to operating conditions and the
CC
0127A-24-80-isp
9
Pin Description
NAME
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
JLCC
PIN NUMBERS
22,
26,
30,
37,
41,
45,
56,
60,
64,
3,
7,
11,
23,
27,
31,
38,
42,
46,
57,
61,
65,
4,
8,
12,
24,
28,
32,
39,
43,
47,
58,
62,
66,
5,
9,
13,
25,
29,
33,
40,
44,
48,
59,
63,
67,
6,
10,
14
Specifications ispLSI 1024/883
DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
IN 4 - IN 5
2
NC
2,
15
19ispEN
1
1
21SDI/IN 0
1
55MODE/IN 3
34SDO/IN 1
1
49SCLK/IN 2
—
20RESET
16Y0
54Y1
51Y2
50Y3
Input - These pins are dedicated input pins to the device.
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO
and SCLK options become active.
Input - This pin performs two functions. When ispEN is logic low, it
functions as an input pin to load programming data into the device.
SDI/IN 0 is also used as one of the two control pins for the isp state
machine. It is a dedicated input pin when ispEN is logic high.
Input - This pin performs two functions. When ispEN is logic low, it
functions as pin to control the operation of the isp state machine. It is a
dedicated input pin when ispEN is logic high.
Output/Input - This pin performs two functions. When ispEN is logic low,
it functions as an output pin to read serial shift register data. It is a
dedicated input pin when ispEN is logic high.
Input - This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. It is a dedicated
input pin when ispEN is logic high.
No Connect
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
GND
VCC
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, Vcc or GND.
1,
17,
18,
36,
35, 52
53, 68
Ground (GND)
V
CC
10
Table 2 - 0002C-24 mil
Pin Configuration
ispLSI 1024/883 68-Pin JLCC Pinout Diagram
I/O 42
I/O 41
I/O 40
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
ispEN
RESET
1
SDI/IN 0
GND
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
10 60
11 59
12 58
13 57
14 56
15 55
IN 5
Y0
16 54
VCC
17 53
18 52
19 51
20 50
21 49
22 48
23 47
24 46
25 45
26 44
27
Specifications ispLSI 1024/883
I/O 39
I/O 38
I/O 37
I/O 36
IN 4
GND
VCC
I/O 35
ispLSI 1024/883
Top View
I/O 34
I/O 33
I/O 32
I/O 31
62426341644065396638673768361352343334325316307298289
I/O 30
61
43
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
IN 3/MODE
Y1
VCC
GND
Y2
Y3
IN 2/SCLK
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
1
1
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
1. Pins have dual function capability.
I/O 10
I/O 11
1
GND
SDO/IN 1
VCC
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
0123-24-isp/JLCC
11
Part Number Description
Specifications ispLSI 1024/883
–
Device Family
ispLSI
Device Number
Speed
60 = 60 MHz fmax
ispLSI
1024 XX X X X
Ordering Information
MILITARY/883
t
f
Family
ispLSI
Note: Lattice Semiconductor recognizes the trend in military device procurement towards
using SMD compliant devices, as such, ordering by this number is recommended.
max (MHz)
60 20 ispLSI 1024-60LH/883 68-Pin JLCC
pd (ns)
Ordering Number Package
5962-9476101MXC
Grade
/883 = 883 Military Process
Package
H = JLCC
Power
L = Low
00212-80B-isp1024 mil
SMD #
Table 2-0041A-24-mil
12
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