Lattice ispLSI, pLSI 1032E User Manual

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• HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates

— 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

• HIGH PERFORMANCE E —

fmax = 125 MHz Maximum Operating Frequency

— tpd = 7.5 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES — In-System Programmable (ISP™) 5-Volt Only — Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs — Enhanced Pin Locking Capability — Four Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to

Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global

Interconnectivity

• ispLSI DEVELOPMENT TOOLS ispVHDL™ Systems

— VHDL/Verilog-HDL/Schematic Design Options — Functional/Timing/VHDL Simulation Options

ispDS™ Software — Lattice HDL or Boolean Logic Entry

— Functional Simulator and Waveform Viewer ispDS+™ HDL Synthesis-Optimized Logic Fitter — Supports Leading Third-Party Design Environments

for Schematic Capture, Synthesis and Timing

Simulation — Static Timing Analyzer ISP Daisy Chain Download Software

2

CMOS® TECHNOLOGY

ispLSI® and pLSI® 1032E

High-Density Programmable Logic

Functional Block DiagramFeatures

Output Routing Pool

D7 D6 D5 D4 D3 D2 D1 D0

GLB

C7 C6 C5 C4 C3 C2

Output Routing Pool

C1 C0

CLK

0139A(A1)-isp

A0 A1 A2 A3 A4 A5

Output Routing Pool

A6

Global Routing Pool (GRP)

A7

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

Logic Array

DQ

Description

The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1032E features 5-Volt in-system programmability and in-system diagnostic capabilities. The ispLSI 1032E device offers non-volatile reprogrammability of the logic, as well as the interconnects to provide truly reconfigurable systems. It is architecturally and parametrically compatible to the pLSI 1032E device, but multiplexes four input pins to control in-system programming. A functional superset of the ispLSI and pLSI 1032 architecture, the ispLSI and pLSI 1032E devices add two new global output enable pins.

The basic unit of logic on the ispLSI and pLSI 1032E devices is the Generic Logic Block (GLB). The GLBs are labeled A0, A1…D7 (see Figure 1). There are a total of 32 GLBs in the ispLSI and pLSI 1032E devices. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device.

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. July 1997 Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com

1032E_05

1

Specifications ispLSI and pLSI 1032E

Functional Block Diagram

Figure 1. ispLSI and pLSI 1032E Functional Block Diagram

I/O 63

I/O 62

I/O 61

I/O 60

I/O 59

I/O 58

I/O 57

I/O 56

I/O 55

RESET

Input Bus

Generic

Logic Blocks

(GLBs)

I/O 0 I/O 1 I/O 2 I/O 3

I/O 4 I/O 5 I/O 6 I/O 7

I/O 8

I/O 9 I/O 10 I/O 11

I/O 12 I/O 13 I/O 14 I/O 15

*SDI/IN 0

*MODE/IN 1

Megablock

*ispEN/NC

*ISP Control Functions for ispLSI 1032E Only

A7

A6

A5

A4

A3

lnput Bus

A2

Output Routing Pool (ORP)

A1

A0

*SDO/IN 2

B0 B1 B2 B3 B4 B5 B6 B7

I/O 16

I/O 17

*SCLK/IN 3

Output Routing Pool (ORP)

D7 D6 D5 D4 D3 D2 D1 D0

Global

Routing

Pool

(GRP)

Output Routing Pool (ORP)

Input Bus

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

I/O 24

I/O 25

I/O 26

I/O 54

I/O 27

I/O 53

I/O 52

I/O 28

I/O 29

I/O 51

I/O 30

I/O 50

I/O 31

I/O 49

I/O 48

IN 7

IN 6

C7

C6

C5

C4

C3

C2

Output Routing Pool (ORP)

C1

C0

CLK 0 CLK 1

Clock

Network

Y0Y1Y2

Y3

CLK 2 IOCLK 0 IOCLK 1

Distribution

lnput Bus

GOE 1/IN 5 GOE 0/IN 4

I/O 47 I/O 46 I/O 45 I/O 44

I/O 43 I/O 42 I/O 41 I/O 40

I/O 39 I/O 38 I/O 37 I/O 36

I/O 35 I/O 34 I/O 33 I/O 32

The devices also have 64 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise.

Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. Each ispLSI and pLSI 1032E device contains four Megablocks.

The GRP has, as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew.

Clocks in the ispLSI and pLSI 1032E devices are selected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (C0 on the ispLSI and pLSI 1032E devices). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device.

2

Specifications ispLSI and pLSI 1032E

Absolute Maximum Ratings

1

Supply Voltage Vcc...................................-0.5 to +7.0V

Input Voltage Applied........................ -2.5 to VCC +1.0V

Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V

Storage Temperature................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (TJ) with Power Applied ... 150°C

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).

DC Recommended Operating Conditions

V V

V

CC

IL IH

SYMBOL

Supply Voltage

Input Low Voltage Input High Voltage

PARAMETER

Commercial Industrial

TA = 0°C to + 70°C

= -40°C to + 85°C

T

A

MIN. MAX. UNITS

4.75

4.5 0

2.0

5.25

5.5

0.8

V

+1

cc

Table 2-0005/1032E

V V V V

Capacitance (TA=25oC, f=1.0 MHz)

SYMBOL

C

1

C

2

(Commercial/Industrial) Y0 Clock Capacitance

PARAMETER

Data Retention Specifications

PARAMETER

Data Retention ispLSI Erase/Reprogram Cycles pLSI Erase/Reprogram Cycles

UNITSTYPICAL TEST CONDITIONS

8Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance

15

MINIMUM MAXIMUM UNITS

20

10000

100

pf

– – –

V = 5.0V, V = 2.0V

CC

V = 5.0V, V = 2.0V

CC PIN

Table 2-0006/1032E

Years Cycles Cycles

Table 2-0008/1032E

3

Switching Test Conditions

Specifications ispLSI and pLSI 1032E

Input Pulse Levels Input Rise and Fall Time

10% to 90% Input Timing Reference Levels

Ouput Timing Reference Levels Output Load

3-state levels are measured 0.5V from steady-state active level.

GND to 3.0V

-125

Others

1.5V

See Figure 2

≤ 2 ns ≤ 3 ns

Table 2-0003/1032E

Figure 2. Test Load

Device Output

+ 5V

R

1

Test

Point

R

2

C

*

L

Output Load Conditions (see Figure 2)

TEST CONDITION R1 R2 CL

*

A 470Ω 390Ω 35pF

Active High

B

Active Low Active High to Z

at V -0.5V

C

Active Low to Z at V +0.5V

OH

OL

∞ 390Ω 35pF

470Ω 390Ω 35pF

∞ 390Ω 5pF

470Ω 390Ω 5pF

Table 2-0004/1032E

CL includes Test Fixture and Probe Capacitance.

DC Electrical Characteristics

Over Recommended Operating Conditions

– – – – – –

– 190 190

3

0.4 –

-10

10

-150

-200 – –

Table 2-0007/1032E

µA µA µA µA

mA mA mA

SYMBOL

V

OL

V

OH

I

IL

I

IH

I

IL-isp

I

IL-PU

1

I

OS

2, 4

I

CC

Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current ispEN Input Low Leakage Current I/O Active Pull-Up Current Output Short Circuit Current

Operating Power Supply Current

PARAMETER

I = 8 mA

OL

I = -4 mA

OH

0V ≤ V ≤ V (Max.)

3.5V ≤ V ≤ V 0V ≤ V ≤ V 0V ≤ V ≤ V V = 5V, V = 0.5V

CC OUT

V = 0.5V, V = 3.0V

IL

f = 1 MHz

CLOCK

1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test problems

CONDITION MIN. TYP. MAX. UNITS

–

2.4

IN IL

IN CC

IL

IN

IN IL

– – – – –

IH

OUT

Commercial Industrial

– –

by tester ground degradation. Characterized but not 100% tested.

2. Measured using eight 16-bit counters.

3. Typical values are at V = 5V and T = 25°C.

4. Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption

CC

CC A

section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I .

CC

0213a

V V

4

External Timing Parameters

Over Recommended Operating Conditions

Specifications ispLSI and pLSI 1032E

4

PARAMETER

t

pd1

t

pd2

f

max (Int.)

f

max (Ext.)

f

max (Tog.)

t

su1

t

co1

t

h1

t

su2

t

co2

t

h2

t

r1

t

rw1

t

ptoeen

t

ptoedis

t

goeen

t

goedis

t

wh – 18 External Synchronous Clock Pulse Duration, High 4.0 ns

t

wl

t

su3

t

h3

1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-bit counter using GRP feedback.

4. Reference Switching Test Conditions section.

TEST

COND.

A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 10.0 ns A 2 Data Propagation Delay, Worst Case Path – ns A 3 Clock Frequency with Internal Feedback 100 – MHz – 4 Clock Frequency with External Feedback – MHz – 5 Clock Frequency, Max. Toggle – MHz – 6 GLB Reg. Setup Time before Clock,4 PT Bypass – ns

A 7 GLB Reg. Clock to Output Delay, ORP Bypass – ns – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass – ns – 9 GLB Reg. Setup Time before Clock – ns

– 10 GLB Reg. Clock to Output Delay – ns – 11 GLB Reg. Hold Time after Clock – ns A 12 Ext. Reset Pin to Output Delay – ns – 13 Ext. Reset Pulse Duration – ns B 14 Input to Output Enable – ns C 15 Input to Output Disable – ns B 16 Global OE Output Enable – ns9.0 C 17 Global OE Output Disable – ns9.0

– 19 External Synchronous Clock Pulse Duration, Low 4.0 ns – 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) – ns

– 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) – ns

2

DESCRIPTION#

( )

1 twh + tw1

1

3

1

( )

tsu2 + tco1

-125

MIN. MAX.

– 7.5

–

10.0

125 –

5.0 –

0.0

6.0 –

0.0

10.0

–

5.0

12.0

–

12.0

– – 7.0 – 7.0

3.0

0.0

– – –

5.0 – –

6.0 –

–

– –

91.0 167

-100

MIN. MAX.

12.5

71.0 125

7.0

6.0

0.0

8.0

7.0

0.0

13.5

6.5

15.0

– –

3.5

0.0

Table 2-0030A/1032E

UNITS

5

External Timing Parameters

Over Recommended Operating Conditions

Specifications ispLSI and pLSI 1032E

4

PARAMETER

t

pd1

t

pd2

f

max (Int.)

f

max (Ext.)

f

max (Tog.)

t

su1

t

co1

t

h1

t

su2

t

co2

t

h2

t

r1

t

rw1

t

ptoeen

t

ptoedis

t

goeen

t

goedis

t

wh – 18 External Synchronous Clock Pulse Duration, High 5.0 ns

t

wl

t

su3

t

h3

1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-bit counter using GRP feedback.

4. Reference Switching Test Conditions section.

TEST

COND.

A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 15.0 ns A 2 Data Propagation Delay, Worst Case Path – ns A 3 Clock Frequency with Internal Feedback 70.0 – MHz – 4 Clock Frequency with External Feedback – MHz – 5 Clock Frequency, Max. Toggle – MHz – 6 GLB Reg. Setup Time before Clock,4 PT Bypass – ns

A 7 GLB Reg. Clock to Output Delay, ORP Bypass – ns – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass – ns – 9 GLB Reg. Setup Time before Clock – ns

– 10 GLB Reg. Clock to Output Delay – ns – 11 GLB Reg. Hold Time after Clock – ns A 12 Ext. Reset Pin to Output Delay – ns – 13 Ext. Reset Pulse Duration – ns B 14 Input to Output Enable – ns C 15 Input to Output Disable – ns B 16 Global OE Output Enable – ns12.0 C 17 Global OE Output Disable – ns

– 19 External Synchronous Clock Pulse Duration, Low 5.0 ns – 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) – ns

– 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) – ns

2

DESCRIPTION#

1

( )

twh + tw1

3

1

( )

tsu2 + tco1

-90

MIN. MAX.

– 10.0

–

12.5

90.0 –

69.0 125

– – –

7.5 –

6.0

0.0

–

8.5

–

7.0

0.0

–

13.5

6.5

–

15.0

–

15.0

USE 1032E-100 FOR

– 9.0 – 9.0 12.0

4.0

–

4.0

–

3.5 –

0.0 –

-80

MIN. MAX.

– 12.0

–

15.0

80.0 –

8.5

6.5

–

0.0

7.5

–

0.0

14.0

–

8.0

16.5

–

16.5

– – 10.0 – 10.0

4.5

3.5

0.0

– – –

– –

–

– –

61.0 111

10.0

NEW DESIGNS

-70

MIN. MAX.

17.5

56.0 100

9.0

7.0

0.0

11.0

8.0

0.0

15.0

10.0

18.0

– –

4.0

0.0

Table 2-0030B/1032E

UNITS

6

Specifications ispLSI and pLSI 1032E

Internal Timing Parameters

PARAM.

2

1

DESCRIPTION#

Inputs

t

iobp

t

iolat

t

iosu

t

ioh

t

ioco

t

ior

t

din

22 I/O Register Bypass ns 23 I/O Latch Delay ns 24 I/O Register Setup Time before Clock ns 25 I/O Register Hold Time after Clock ns 26 I/O Register Clock to Out Delay ns 27 I/O Register Reset to Out Delay ns 28 Dedicated Input Delay ns

GRP

t

grp1

t

grp4

t

grp8

t

grp16

t

grp32

29 GRP Delay, 1 GLB Load ns 30 GRP Delay, 4 GLB Loads ns 31 GRP Delay, 8 GLB Loads ns 32 GRP Delay, 16 GLB Loads ns 33 ns

GRP Delay, 32 GLB Loads

GLB

t

4ptbpc

t

4ptbpr

t

1ptxor

t

20ptxor

t

xoradj

t

gbp

t

gsu

t

gh

t

gco

t

gro

t

ptre

t

ptoe

t

ptck

34 4 Prod.Term Bypass Path Delay (Combinatorial) ns 35 4 Prod. Term Bypass Path Delay (Registered) ns 36 1 Prod.Term/XOR Path Delay ns 37 20 Prod. Term/XOR Path Delay ns 38 XOR Adjacent Path Delay ns 39 GLB Register Bypass Delay 40 GLB Register Setup Time before Clock ns

41 GLB Register Hold Time after Clock ns 42 GLB Register Clock to Output Delay ns 43 GLB Register Reset to Output Delay ns

44 GLB Prod.Term Reset to Register Delay ns 45 GLB Prod. Term Output Enable to I/O Cell Delay ns

46 GLB Prod. Term Clock Delay ns

3

ORP

t

orp

t

orpbp

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

47 ORP Delay ns 48 ORP Bypass Delay ns

MIN.

– –

3.0

0.0 – – –

– – –

–

– – – – –

–

0.1

4.5 – –

– –

2.9

– –

-125

0.3

1.9 – –

4.6

2.3

1.8

2.0

2.3

2.8

3.8

3.9

4.0

3.6

5.0

0.4 –

–

2.3

4.9

3.9

5.4

4.0

1.0

0.0

-100

MIN.MAX. MAX.

–

0.3

–

2.3

3.5

–

0.0

–

5.0

–

5.0

–

2.7

–

1.9

–

2.4

–

2.4

–

3.0

–

4.2

–

5.3

–

5.3

–

4.6

–

5.8

–

6.3

–

1.0

0.5

–

5.8

–

2.5

–

6.2

–

4.5

–

7.2

3.5

4.7

–

1.0

–

0.0

Table 2-0036A/1032E

UNITS

ns

7

Specifications ispLSI and pLSI 1032E

Internal Timing Parameters

PARAM.

2

1

DESCRIPTION#

Inputs

t

iobp

t

iolat

t

iosu

t

ioh

t

ioco

t

ior

t

din

22 I/O Register Bypass – ns 23 I/O Latch Delay – ns 24 I/O Register Setup Time before Clock 3.5 ns 25 I/O Register Hold Time after Clock 0.0 ns 26 I/O Register Clock to Out Delay – ns 27 I/O Register Reset to Out Delay – ns 28 Dedicated Input Delay – ns

GRP

t

grp1

t

grp4

t

grp8

t

grp16

t

grp32

29 GRP Delay, 1 GLB Load – ns 30 GRP Delay, 4 GLB Loads – ns 31 GRP Delay, 8 GLB Loads – ns 32 GRP Delay, 16 GLB Loads – ns 33 –ns

GRP Delay, 32 GLB Loads

GLB

t

4ptbpc

t

4ptbpr

t

1ptxor

t

20ptxor

t

xoradj

t

gbp

t

gsu

t

gh

t

gco

t

gro

t

ptre

t

ptoe

t

ptck

34 4 Prod.Term Bypass Path Delay (Combinatorial) – ns 35 4 Prod. Term Bypass Path Delay (Registered) – ns 36 1 Prod.Term/XOR Path Delay – ns 37 20 Prod. Term/XOR Path Delay – ns 38 XOR Adjacent Path Delay – ns 39 GLB Register Bypass Delay 40 GLB Register Setup Time before Clock ns

41 GLB Register Hold Time after Clock ns 42 GLB Register Clock to Output Delay – ns 43 GLB Register Reset to Output Delay – ns

44 GLB Prod.Term Reset to Register Delay – ns 45 GLB Prod. Term Output Enable to I/O Cell Delay – ns

46 GLB Prod. Term Clock Delay ns

3

ORP

t

orp

t

orpbp

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

47 ORP Delay – ns 48 ORP Bypass Delay – 0.0 ns

-90

MIN. MAX.

–

0.3

–

2.3

3.5

–

0.0

–

5.0

–

5.0

–

2.6

–

2.1

–

2.3

–

2.6

–

3.2

–

4.4

–

5.7

–

6.1

–

5.6

–

6.8

–

7.1

–

0.4

USE 1032E-100 FOR

0.2

–

6.8

–

2.9

–

6.3

–

5.1

–

7.1

4.1

5.3

–

1.0

0.0

–

-80

MIN.

0.3

2.7 – –

5.4

2.8

2.2

2.5

2.8

3.5

4.8

7.1

6.7

6.6

7.8

NEW DESIGNS

8.2

–ns

1.3

0.5

–

7.9

–

2.9

6.4

5.5

8.0

4.5

5.8

1.0

0.0

-70

MIN.MAX. MAX.

–

0.3

–

3.3

4.0

0.0

0.5

8.8

4.8

– –

–

6.1

–

6.0

–

2.8

–

2.5

–

2.5

–

3.2

–

4.0

–

5.6

–

8.8

–

7.2

–

8.3

–

8.7

–

9.2

–

1.6 –

–

2.9

–

6.8

–

5.8

–

9.0

6.2

–

1.0

–

Table 2-0036B/1032E

UNITS

8

Specifications ispLSI and pLSI 1032E

Internal Timing Parameters

1

DESCRIPTION#PARAM.

Outputs

t t t t t

ob sl oen odis goe

49 Output Buffer Delay ns 50 Output Buffer Delay, Slew Limited Adder ns 51 I/O Cell OE to Output Enabled ns 52 I/O Cell OE to Output Disabled ns 53 Global OE ns

Clocks

t

gy0

t

gy1/2

t

gcp

t

ioy2/3

t

iocp

54 Clk Delay, Y0 to Global GLB Clk Line (Ref. clk) ns 55 Clk Delay, Y1 or Y2 to Global GLB Clk Line ns 56 Clk Delay, Clock GLB to Global GLB Clk Line ns 57 Clk Delay, Y2 or Y3 to I/O Cell Global Clk Line ns 58 Clk Delay, Clk GLB to I/O Cell Global Clk Line ns

Global Reset

t

gr

1. Internal Timing Parameters are not tested and are for reference only.

59 Global Reset to GLB and I/O Registers ns

MIN.

– – – – –

1.4

0.8

0.0

0.8

–

-125

1.3

9.9

4.3

2.7

1.4

1.8

0.0

1.8

2.8

-100

MIN.MAX. MAX.

2.0

–

10.0

–

5.1

–

5.1

–

3.9

–

1.5

1.8

0.8

0.0

1.8

0.8

4.3

–

Table 2-0037A/1032E

UNITS

9

Specifications ispLSI and pLSI 1032E

Internal Timing Parameters

1

DESCRIPTION#PARAM.

Outputs

t t t t t

ob sl oen odis goe

49 Output Buffer Delay – ns 50 Output Buffer Delay, Slew Limited Adder – ns 51 I/O Cell OE to Output Enabled – ns 52 I/O Cell OE to Output Disabled – ns 53 Global OE – ns

Clocks

t

gy0

t

gy1/2

t

gcp

t

ioy2/3

t

iocp

54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 1.5 ns 55 Clock Delay, Y1 or Y2 to Global GLB Clock Line 2.6 ns 56 Clock Delay, Clock GLB to Global GLB Clock Line 0.8 ns 57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line 0.0 ns 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line 0.8 ns

Global Reset

t

gr

1. Internal Timing Parameters are not tested and are for reference only.

59 Global Reset to GLB and I/O Registers – ns

-90

MIN. MAX.

1.7

–

10.0

–

5.3

–

5.3

–

3.7

–

1.4

2.9

2.4

1.8

0.8

0.0

1.8

0.8

USE 1032E-100 FOR

4.5

–

-80

MIN.

2.1

10.0

5.7

4.3

1.5

3.1

1.8

0.0

NEW DESIGNS

1.8

4.5

-70

MIN.MAX. MAX.

–

2.6

–

10.0

–

6.2

–

6.2

–

5.8

1.5

0.8

1.8

0.0

0.8

1.8

–

4.6

Table 2-0037B/1032E

UNITS

10

Specifications ispLSI and pLSI 1032E

ispLSI and pLSI 1032E Timing Model

I/O CellORPGLBGRPI/O Cell

Feedback

Ded. In

I/O Pin (Input)

Reset

Y1,2,3

Y0

GOE 0,1

#59

#28

I/O Reg Bypass

#22

Input

Register

D RST

Q

#23 - 27

GRP4

#30

GRP Loading

Delay

#29, 31 - 33

Clock

Distribution

#55 - 58

#54

#53

#34 Comb 4 PT Bypass

Reg 4 PT Bypass

#35

20 PT

XOR Delays

#36 - 38

#59

Control

RE

PTs

OE CK

#44 - 46

Derivations of tsu, th and tco from the Product Term Clock

tsu

2.2 ns

th Clock (max) + Reg h - Logic

3.5 ns

=

Logic + Reg su - Clock (min)

tiobp + tgrp4 + t20ptxor) + (tgsu) – (tiobp + tgrp4 + tptck(min))

=

( (#22 + #30 + #37) + (#40) – (#22 + #30 + #46)

=

(0.3 + 2.0 + 5.0) + (0.1) – (0.3 + 2.0 + 2.9)

=

tiobp + tgrp4 + tptck(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)

=

( (#22 + #30 + #46) + (#41) - (#22 + #30 + #37)

=

(0.3 + 2.0 + 4.0) + (4.5) – (0.3 + 2.0 + 5.0)

=

GLB Reg Bypass ORP Bypass

#39

GLB Reg

Delay

DQ RST

#40 - 43

1

#48

ORP

Delay

#47

#49, 50

#51, 52

0491

I/O Pin

(Output)

tco

10.9 ns

Derivations of tsu, th and tco from the Clock GLB

tsu

2.9 ns

th

2.7 ns

tco

5.5 ns

Clock (max) + Reg co + Output

=

tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)

(

=

(#22 + #30 + #46) + (#42) + (#47 + #49)

=

(0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3)

=

1

=

Logic + Reg su - Clock (min)

tiobp + tgrp4 + t20ptxor) + (tgsu) – (tgy0(min) + tgco + tgcp(min))

=

( (#22 + #30 + #37) + (#40) – (#54 + #42 + #56)

=

(0.3 + 2.0 + 5.0) + (0.1) – (1.4 + 2.3 + 0.8)

=

Clock (max) + Reg h - Logic

=

tgy0(max) + tgco + tgcp(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)

(

=

(#54 + #42 + #56) + (#41) – (#22 + #30 + #37)

=

(1.4 + 2.3 + 1.8) + (4.5) – (0.3 + 2.0 + 5.0)

=

Clock (max) + Reg co + Output

=

tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)

(

=

(#54 + #42 + #56) + (#42) + (#47 + #49)

=

(1.4 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3)

=

1. Calculations are based upon timing specifications for the ispLSI and pLSI 1032E-125.

Table 2-0042a/1032E

11

Specifications ispLSI and pLSI 1032E

Maximum GRP Delay vs GLB Loads

6.0

5.0

4.0

GRP Delay (ns)

3.0

2.0

1.0 1 8 16 32

4

Power Consumption

ispLSI and pLSI 1032E-70 ispLSI and pLSI 1032E-80

ispLSI and pLSI 1032E-90/100 ispLSI and pLSI 1032E-125

GLB Load

GRP/GLB/1032E

Power consumption in the ispLSI and pLSI 1032E device depends on two primary factors: the speed at which the

used. Figure 3 shows the relationship between power and operating speed.

device is operating, and the number of product terms

Figure 3. Typical Device Power Consumption vs fmax

350 300

250

200

CC (mA)

I

150 100

20

0

I can be estimated for the ispLSI and pLSI 1032E using the following equation:

CC

I (mA) = 15 + (# of PTs * 0.59) + (# of nets * Max freq * 0.0078)

CC

Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz)

40

Notes: Configuration of eight 16-bit counters

60 80

f

max (MHz)

Typical current at 5V, 25°C

ispLSI and pLSI 1032E

100

125 150

The I estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of four GLB

CC

loads on average exists. These values are for estimates only. Since the value of I is sensitive to operating conditions and the program in the device, the actual I should be verified.

CC

0127/1032E

12

Pin Description

Specifications ispLSI and pLSI 1032E

NAME

I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 I/O 32 - I/O 35 I/O 36 - I/O 39 I/O 40 - I/O 43 I/O 44 - I/O 47 I/O 48 - I/O 51 I/O 52 - I/O 55 I/O 56 - I/O 59 I/O 60 - I/O 63

GOE 1/IN 5

IN 6, IN 7

PLCC PIN

NUMBERS

27,

26,

31,

30,

35,

34,

39,

38,

46,

45,

50,

49,

54,

53,

58,

57,

69,

68,

73,

72,

77,

76,

81,

80,

4,

3,

8,

7,

12,

11,

16,

15, 67

84

2,

19

23ispEN**/NC

25SDI*/IN 0

42MODE*/IN 1

44SDO*/IN 2

61SCLK*/IN 3

24RESET

20Y0

66Y1

28, 32, 36, 40, 47, 51, 55, 59, 70, 74, 78, 82, 5, 9, 13, 17,

29, 33, 37, 41, 48, 52, 56, 60, 71, 75, 79, 83, 6, 10, 14, 18

TQFP PIN

NUMBERS

18,

17,

22,

21,

30,

29,

34,

33,

41,

40,

45,

44,

53,

48,

57,

56,

68,

67,

72,

71,

80,

79,

84,

83,

91,

90,

95,

94,

3,

98,

7,

6, 66

87

89,

10

14

16

37

39

60

15

11

65

19, 23, 31, 35, 42, 46, 54, 58, 69, 73, 81, 85, 92, 96, 4, 8,

DESCRIPTION

Input/Output Pins - These are the general purpose I/O pins used by the logic

20,

array.

28, 32, 36, 43, 47, 55, 59, 70, 78, 82, 86, 93, 97, 5, 9

This is a dual function pin. It can be used either as Global Output Enable for

GOE 0/IN 4

all I/O cells or it can be used as a dedicated input pin.

This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be used as a dedicated input pin.

Dedicated input pins to the device. Input - Dedicated in-system programming enable input pin. This pin is

brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active.

Input - This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 is also used as one of the two control pins for the isp state machine. It is a dedicated input pin when ispEN is logic high.

Input - This pin performs two functions. When ispEN is logic low, it functions as pin to control the operation of the isp state machine. It is a dedicated input pin when ispEN is logic high.

Output/Input - This pin performs two functions. When ispEN is logic low, it functions as an output pin to read serial shift register data. It is a dedicated input pin when ispEN is logic high.

Input - This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. It is a dedicated input pin when ispEN is logic high.

Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device.

Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device.

Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device.

63Y2

62Y3

GND VCC 21, 65

NC

* ispLSI 1032E only ** ispEN for ispLSI 1032E; NC for pLSI 1032E, must be left floating or tied to V , must not be grounded or tied to any other signal.

1, 22, 43, 64

62

61

13, 38, 63, 88

64

12,

2, 24, 25, No connect.

1,

27, 49, 50,

26,

52, 74, 75,

51,

77, 99, 100

76,

Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device.

Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device.

Ground (GND) Vcc

CC

13

Table 2-0002A/1032E

Specifications ispLSI and pLSI 1032E

Pin Configurations

ispLSI and pLSI 1032E 84-Pin PLCC Pinout Diagram

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

I/O 49

I/O 48

111098765432184838281807978777675

IN 6

GND

**GOE 1/IN 5

I/O 47

I/O 46

I/O 45

I/O 44

I/O 43

I/O 42

I/O 41

I/O 40

I/O 39

I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63

IN 7

Y0

VCC

GND

*ispEN/NC

RESET

*SDI/IN 0

I/O 0 I/O 1 I/O 2

I/O 3 I/O 4 I/O 5 I/O 6

12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

ispLSI 1032E

pLSI 1032E

Top View

74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54

I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 **GOE 0/IN 4 Y1 VCC GND Y2 Y3 *SCLK/IN 3 I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

*MODE/IN 1

GND

*SDO/IN 2

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

I/O 24

* Pins have dual function capability for ispLSI 1032E only (except pin 23, which is ispEN only).

** Pins have dual function capability which is software selectable.

0123-32-isp

14

Specifications ispLSI and pLSI 1032E

Pin Configurations

ispLSI 1032E 100-Pin TQFP Pinout Diagram

NC

NC I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63

IN 7

Y0

VCC

GND

ispEN

RESET

*SDI/IN 0

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6

NC

NCNCI/O 56

100

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

26272829303132333435363738394041424344454647484950

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

I/O 49

I/O 48

IN 6

GND

**GOE 1/IN 5

I/O 47

I/O 46

I/O 45

I/O 44

I/O 43

I/O 42

I/O 41

9998979695949392919089888786858483828180797877

ispLSI 1032E

Top View

I/O 40

I/O 39NCNC

76

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

NC NC I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 **GOE 0/IN 4 Y1 VCC GND Y2 Y3 *SCLK/IN 3 I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 NC NC

NC

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

GND

I/O 15

*MODE/IN1

I/O 16

I/O 17

I/O 18

*SDO/IN 2

I/O 19

I/O 20

* Pins have dual function capability. ** Pins have dual function capability which is software selectable.

15

I/O 21

I/O 22

I/O 23

I/O 24

NC

0766A-32E-isp

Part Number Description

Specifications ispLSI and pLSI 1032E

(is)pLSI

1032E XXX X X X

–

Device Family

Device Number

Speed

f f

f

max

f

max

f

max

max max

125 = 125 MHz 100 = 100 MHz 90 = 90 MHz 80 = 80 MHz 70 = 70 MHz

ispLSI and pLSI 1032E Ordering Information

COMMERCIAL

FAMILY fmax (MHz)

125 125 100-Pin TQFP7.5 ispLSI 1032E-125LT

100

ispLSI

pLSI

*ispLSI 1032E-100 recommended for new designs.

100

90 90 80 12

80 70 70

125 100

90 84-Pin PLCC10 pLSI 1032E-90LJ* 80

70

7.5

10

12 15 15

10

15

ORDERING NUMBER PACKAGEtpd (ns)

ispLSI 1032E-100LJ

ispLSI 1032E-90LJ*

ispLSI 1032E-80LT*

ispLSI 1032E-70LJ

pLSI 1032E-125LJ

pLSI 1032E-80LJ*

Grade

Blank = Commercial I = Industrial

Package

J = PLCC T = TQFP

Power

L = Low

0212/1032E

84-Pin PLCCispLSI 1032E-125LJ

84-Pin PLCC10

100-Pin TQFPispLSI 1032E-100LT

84-Pin PLCC10

100-Pin TQFPispLSI 1032E-90LT*

84-Pin PLCCispLSI 1032E-80LJ*

100-Pin TQFP

84-Pin PLCC

100-Pin TQFPispLSI 1032E-70LT

84-Pin PLCC7.5 84-Pin PLCCpLSI 1032E-100LJ

84-Pin PLCC12

84-Pin PLCCpLSI 1032E-70LJ

Table 2-0041A/1032E

FAMILY fmax (MHz)

ispLSI

70 70

Note: Use ispLSI for all new designs.

tpd (ns)

15 15

INDUSTRIAL

ORDERING NUMBER PACKAGE

ispLSI 1032E-70LJI ispLSI 1032E-70LTI

84-Pin PLCC

100-Pin TQFP

16

Table 2-0041B/1032E

Semiconductor Corp., L (stylized) and Lattice (design) are registered trademarks of Lattice Semiconductor Corporation. Generic Array Logic, ISP, ispATE, ispCODE, ispDOWNLOAD, ispDS, ispDS+, ispGDS, ispGDX, ispHDL, ispJTAG, ispStarter, ispSTREAM, ispTEST, ispTURBO, ispVECTOR, ispVerilog, ispVHDL, Latch-Lock, LHDL, pDS+, RFT, Total ISP and Twin GLB are trademarks of Lattice Semiconductor Corporation. ISP is a service mark of Lattice Semiconductor Corporation. All brand names or product names mentioned are trademarks or registered trademarks of their respective holders.

Lattice Semiconductor Corporation (LSC) products are made under one or more of the following U.S. and international patents: 4,761,768 US, 4,766,569 US, 4,833,646 US, 4,852,044 US, 4,855,954 US, 4,879,688 US, 4,887,239 US, 4,896,296 US, 5,130,574 US, 5,138,198 US, 5,162,679 US, 5,191,243 US, 5,204,556 US, 5,231,315 US, 5,231,316 US, 5,237,218 US, 5,245,226 US, 5,251,169 US, 5,272,666 US, 5,281,906 US, 5,295,095 US, 5,329,179 US, 5,331,590 US, 5,336,951 US, 5,353,246 US, 5,357,156 US, 5,359,573 US, 5,394,033 US, 5,394,037 US, 5,404,055 US, 5,418,390 US, 5,493,205 US, 0194091 EP, 0196771B1 EP, 0267271 EP, 0196771 UK, 0194091 GB, 0196771 WG, P3686070.0-08 WG. LSC does not represent that products described herein are free from patent infringement or from any third-party right.

The specifications and information herein are subject to change without notice. Lattice Semiconductor Corporation (LSC) reserves the right to discontinue any product or service without notice and assumes no obligation to correct any errors contained herein or to advise any user of this document of any correction if such be made. LSC recommends its customers obtain the latest version of the relevant information to establish, before ordering, that the information being relied upon is current.

LSC warrants performance of its products to current and applicable specifications in accordance with LSC’s standard warranty. Testing and other quality control procedures are performed to the extent LSC deems necessary. Specific testing of all parameters of each product is not necessarily performed, unless mandated by government requirements.

LSC assumes no liability for applications assistance, customer’s product design, software performance, or infringements of patents or services arising from the use of the products and services described herein.

LSC products are not authorized for use in life-support applications, devices or systems. Inclusion of LSC products in such applications is prohibited.

LATTICE SEMICONDUCTOR CORPORATION 5555 Northeast Moore Court Hillsboro, Oregon 97124 U.S.A. Tel.: (503) 681-0118 FAX: (503) 681-3037 http://www.latticesemi.com July 1997

Lattice ispLSI, pLSI 1032E User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual