Lattice ispGDX 160V, ispGDX 160VA User Manual

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ispGDX

160V/VA

In-System Programmable

3.3V Generic Digital Crosspoint

Functional Block DiagramFeatures

• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY

— Advanced Architecture Addresses Programmable

PCB Interconnect, Bus Interface Integration and

Jumper/Switch Replacement — “Any Input to Any Output” Routing — Fixed HIGH or LOW Output Option for Jumper/DIP

Switch Emulation — Space-Saving PQFP and BGA Packaging — Dedicated IEEE 1149.1-Compliant Boundary Scan

Test

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 3.3V Core Power Supply

— 3.5ns Input-to-Output/3.5ns Clock-to-Output Delay* — 250MHz Maximum Clock Frequency* — TTL/3.3V/2.5V Compatible Input Thresholds and

Output Levels (Individually Programmable)* — Low-Power: 16.5mA Quiescent Icc* — 24mA IOL Drive with Programmable Slew Rate

Control Option — PCI Compatible Drive Capability* — Schmitt Trigger Inputs for Noise Immunity — Electrically Erasable and Reprogrammable — Non-Volatile E2CMOS Technology

• ispGDXV™ OFFERS THE FOLLOWING ADVANTAGES — 3.3V In-System Programmable Using Boundary Scan

Test Access Port (TAP)

— Change Interconnects in Seconds

• FLEXIBLE ARCHITECTURE — Combinatorial/Latched/Registered Inputs or Outputs

— Individual I/O Tri-state Control with Polarity Control — Dedicated Clock/Clock Enable Input Pins (four) or

Programmable Clocks/Clock Enables from I/O Pins

(40) — Single Level 4:1 Dynamic Path Selection (Tpd = 3.5ns) — Programmable Wide-MUX Cascade Feature

Supports up to 16:1 MUX — Programmable Pull-ups, Bus Hold Latch and Open

Drain on I/O Pins — Outputs Tri-state During Power-up (“Live Insertion”

Friendly)

• DESIGN SUPPORT THROUGH LATTICE’S ispGDX DEVELOPMENT SOFTWARE

— MS Windows or NT / PC-Based or Sun O/S — Easy Text-Based Design Entry — Automatic Signal Routing — Program up to 100 ISP Devices Concurrently — Simulator Netlist Generation for Easy Board-Level

Simulation

* “VA” Version Only

Copyright © 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. July 2000 Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

gdx160va_04

Boundary

Scan

Control

Description

The ispGDXV/VA architecture provides a family of fast, flexible programmable devices to address a variety of system-level digital signal routing and interface requirements including:

• Multi-Port Multiprocessor Interfaces

• Wide Data and Address Bus Multiplexing (e.g. 16:1 High-Speed Bus MUX)

• Programmable Control Signal Routing (e.g. Interrupts, DMAREQs, etc.)

• Board-Level PCB Signal Routing for Prototyping or Programmable Bus Interfaces

The devices feature fast operation, with input-to-output signal delays (Tpd) of 3.5ns and clock-to-output delays of

3.5ns. The architecture of the devices consists of a series of

programmable I/O cells interconnected by a Global Routing Pool (GRP). All I/O pin inputs enter the GRP directly or are registered or latched so they can be routed to the required I/O outputs. I/O pin inputs are defined as four sets (A,B,C,D) which have access to the four MUX inputs

I/O

Cells

I/O Pins A

I/O Pins D

Global Routing

Pool

(GRP)

I/O Pins B

I/O

Cells

ISP

Control

I/O Pins C

Description (Continued)

Specifications ispGDX160V/VA

found in each I/O cell. Each output has individual, programmable I/O tri-state control (OE), output latch clock (CLK), clock enable (CLKEN), and two multiplexer control (MUX0 and MUX1) inputs. Polarity for these signals is programmable for each I/O cell. The MUX0 and MUX1 inputs control a fast 4:1 MUX, allowing dynamic selection of up to four signal sources for a given output. A wider 16:1 MUX can be implemented with the MUX expander feature of each I/O and a propagation delay increase of

2.0ns. OE, CLK, CLKEN, and MUX0 and MUX1 inputs can be driven directly from selected sets of I/O pins. Optional dedicated clock input pins give minimum clockto-output delays. CLK and CLKEN share the same set of I/O pins. CLKEN disables the register clock when CLKEN = 0.

Through in-system programming, connections between I/O pins and architectural features (latched or registered inputs or outputs, output enable control, etc.) can be defined. In keeping with its data path application focus, the ispGDXV devices contain no programmable logic arrays. All input pins include Schmitt trigger buffers for noise immunity. These connections are programmed into the device using non-volatile E

CMOS technology. Non-volatile technology means the device configuration is saved even when the power is removed from the device.

In addition, there are no pin-to-pin routing constraints for

any

1:1 or 1:n signal routing. That is,

I/O pin configured as an input can drive one or more I/O pins configured as outputs.

The device pins also have the ability to set outputs to fixed HIGH or LOW logic levels (Jumper or DIP Switch mode). Device outputs are specified for 24mA sink and 12mA source current (at JEDEC LVTTL levels) and can be tied together in parallel for greater drive. On the ispGDXVA, each I/O pin is individually programmable for

3.3V or 2.5V output levels as described later. Programmable output slew rate control can be defined independently for each I/O pin to reduce overall ground bounce and switching noise.

All I/O pins are equipped with IEEE1149.1-compliant Boundary Scan Test circuitry for enhanced testability. In addition, in-system programming is supported through the Test Access Port via a special set of private commands.

The ispGDXV I/Os are designed to withstand “live insertion” system environments. The I/O buffers are disabled during power-up and power-down cycles. When designing for “live insertion,” absolute maximum rating conditions for the Vcc and I/O pins must still be met.

Table 1. ispGDXV Family Members

I/O Pins 160 I/O-OE Inputs* 40 I/O-CLK / CLKEN Inputs* 40 I/O-MUXsel1 Inputs* 40 I/O-MUXsel2 Inputs* 40 Dedicated Clock Pins** 4

EPEN 1 TOE BSCAN Interface 4

RESET

Pin Count/Package 208-Pin PQFP

* The CLK/CLK_EN, OE, MUX0 and MUX1 terminals on each I/O cell can each be assigned to

25% of the I/Os.

** Global clock pins Y0, Y1, Y2 and Y3 are multiplexed with CLKEN0, CLKEN1, CLKEN2 and

CLKEN3 respectively in all devices.

ispGDXV/VA Device

ispGDX80VA ispGDX240VA

80 20 20 20 20

2 1

1 4 1

100-Pin TQFP

ispGDX160V/VA

208-Ball fpBGA

272-Ball BGA

240

60 60 60 60

4 1

1 4 1

388-Ball fpBGA

Architecture

Specifications ispGDX160V/VA

The ispGDXV/VA architecture is different from traditional PLD architectures, in keeping with its unique application focus. The block diagram is shown below. The program-

The various I/O pin sets are also shown in the block diagram below. The A, B, C, and D I/O pins are grouped

together with one group per side. mable interconnect consists of a single Global Routing Pool (GRP). Unlike ispLSI devices, there are no programmable logic arrays on the device. Control signals for OEs, Clocks/Clock Enables and MUX Controls must come from designated sets of I/O pins. The polarity of these signals can be independently programmed in each I/O cell.

Each I/O cell drives a unique pin. The OE control for each I/O pin is independent and may be driven via the GRP by one of the designated I/O pins (I/O-OE set). The I/O-OE set consists of 25% of the total I/O pins. Boundary Scan test is supported by dedicated registers at each I/O pin. In-system programming is accomplished through the standard Boundary Scan protocol.

I/O Architecture

Each I/O cell contains a 4:1 dynamic MUX controlled by

two select lines as well as a 4x4 crossbar switch con-

trolled by software for increased routing flexiability (Figure

1). The four data inputs to the MUX (called M0, M1, M2,

and M3) come from I/O signals in the GRP and/or

adjacent I/O cells. Each MUX data input can access one

quarter of the total I/Os. For example, in a 160 I/O

ispGDXV, each data input can connect to one of 40 I/O

pins. MUX0 and MUX1 can be driven by designated I/O

pins called MUXsel1 and MUXsel2. Each MUXsel input

covers 25% of the total I/O pins (e.g. 40 out of 160). MUX0

and MUX1 can be driven from either MUXsel1 or MUXsel2.

Figure 1. ispGDXV/VA I/O Cell and GRP Detail (160 I/O Device)

Logic “1”

Logic “0”

I/OCell 0

160 I/O Inputs

I/O Cell 159

I/O Cell 1

•

I/O Cell 78

I/O Cell 79

80 I/O Cells

160 Input GRP

Inputs Vertical

Outputs Horizontal

E2CMOS

Programmable

Interconnect

I/O Group A I/O Group B I/O Group C I/O Group D

• • • • • •

Y0-Y3 Global

Clocks /

Clock_Enables

From MUX Outputs

of 2 Adjacent I/O Cells

N+2

N+1

N-1

N-2

Global

Reset

4x4

Crossbar

Switch

From MUX Outputs

of 2 Adjacent I/O Cells

80 I/O Cells

ispGDXV/VA architecture enhancements over ispGDX (5V)

4-to-1 MUX

M0 M1 M2 M3

MUX1MUX0

I/O Cell 158

To 2 Adjacent

I/O Cells above

To 2 Adjacent

I/O Cells below

I/O Cell 81

I/O Cell 80

•

Bypass Option

CLK

CLK_EN

Reset

Prog.

Bus Hold

Pull-up

Latch

(VCCIO)

Prog. Open Drain

2.5V/3.3V Output

Prog. Slew Rate

Boundary Scan Cell

I/O Pin

I/O Cell N

Specifications ispGDX160V/VA

I/O MUX Operation

MUX1 MUX0 Data Input Selected

00 M0 01 M1 11 M2 10 M3

Flexible mapping of MUXselx to MUXx allows the user to change the MUX select assignment after the ispGDXV/ VA device has been soldered to the board. Figure 1 shows that the I/O cell can accept (by programming the appropriate fuses) inputs from the MUX outputs of four adjacent I/O cells, two above and two below. This enables cascading of the MUXes to enable wider (up to 16:1) MUX implementations.

The I/O cell also includes a programmable flow-through latch or register that can be placed in the input or output path and bypassed for combinatorial outputs. As shown in Figure 1, when the input control MUX of the register/ latch selects the “A” path, the register/latch gets its inputs from the 4:1 MUX and drives the I/O output. When selecting the “B” path, the register/latch is directly driven by the I/O input while its output feeds the GRP. The programmable polarity Clock to the latch or register can be connected to any I/O in the I/O-CLK/CLKEN set (onequarter of total I/Os) or to one of the dedicated clock input pins (Yx). The programmable polarity Clock Enable input to the register can be programmed to connect to any of the I/O-CLK/CLKEN input pin set or to the global clock enable inputs (CLKENx). Use of the dedicated clock inputs gives minimum clock-to-output delays and minimizes delay variation with fanout. Combinatorial output mode may be implemented by a dedicated architecture bit and bypass MUX. I/O cell output polarity can be programmed as active high or active low.

allow adjacent I/O cell outputs to be directly connected

without passing through the global routing pool. The

relationship between the [N+i] adjacent cells and A, B, C

and D inputs will vary depending on where the I/O cell is

located on the physical die. The I/O cells can be grouped

into “normal” and “reflected” I/O cells or I/O “hemi-

spheres.” These are defined as:

Device Normal I/O Cells Reflected I/O Cells

ispGDX80VA

ispGDX160V/VA

ispGDX240VA B29-B0, A59-A0,

B9-B0, A19-A0,

D19-D10

B19-B0, A39-A0,

D39-D20

D59-D30

B10-B19, C0-C19,

D0-D9

B20-B39, C0-C39,

D0-D19

B30-B59, C0-C59,

D0-D29

Table 2 shows the relationship between adjacent I/O

cells as well as their relationship to direct MUX inputs.

Note that the MUX expansion is circular and that I/O cell

B20, for example, draws on I/Os B19 and B18, as well as

B21 and B22, even though they are in different hemi-

spheres of the physical die. Table 2 shows some typical

cases and all boundary cases. All other cells can be

extrapolated from the pattern shown in the table.

Figure 2. I/O Hemisphere Configuration of

ispGDX160V/VA

I/O cell 0 I/O cell 159

D39

D20 D19

C39 C0

MUX Expander Using Adjacent I/O Cells

The ispGDXV/VA allows adjacent I/O cell MUXes to be cascaded to form wider input MUXes (up to 16 x 1) without incurring an additional full Tpd penalty. However, there are certain dependencies on the locality of the adjacent MUXes when used along with direct MUX inputs.

Adjacent I/O Cells

Expansion inputs MUXOUT[n-2], MUXOUT[n-1], MUXOUT[n+1], and MUXOUT[n+2] are fuse-selectable for each I/O cell MUX. These expansion inputs share the same path as the standard A, B, C and D MUX inputs, and

I/O cell index increases in this direction

A39

I/O cell 79 I/O cell 80

B19 B20

B39

Direct and Expander Input Routing

Table 2 also illustrates the routing of MUX direct inputs

that are accessible when using adjacent I/O cells as

inputs. Take I/O cell D23 as an example, which is also

shown in Figure 3.

I/O cell index increases in this direction

Specifications ispGDX160V/VA

Figure 3. Adjacent I/O Cells vs. Direct Input Path for ispGDX160V/VA, I/O D23

ispGDX160V/VA I/O Cell

I/O Group A D21 MUX Out I/O Group B D22 MUX Out

I/O Group C D24 MUX Out

I/O Group D D25 MUX Out

4 x 4

Crossbar

Switch

.m0 .m1 .m2 .m3

S0S1

D23

It can be seen from Figure 3 that if the D21 adjacent I/O cell is used, the I/O group “A” input is no longer available as a direct MUX input.

The ispGDXV/VA can implement MUXes up to 16 bits wide in a single level of logic, but care must be taken when combining adjacent I/O cell outputs with direct MUX inputs. Any particular combination of adjacent I/O cells as MUX inputs will dictate what I/O groups (A, B, C or D) can be routed to the remaining inputs. By properly choosing the adjacent I/O cells, all of the MUX inputs can be utilized.

Special Features

Slew Rate Control

All output buffers contain a programmable slew rate

control that provides software-selectable slew rate op-

tions.

Open Drain Control

All output buffers provide a programmable Open-Drain

option which allows the user to drive system level reset,

interrupt and enable/disable lines directly without the

need for an off-chip Open-Drain or Open-Collector buffer.

Wire-OR logic functions can be performed at the printed

circuit board level.

Pull-up Resistor

All pins have a programmable active pull-up. A typical

resistor value for the pull-up ranges from 50kΩ to 80kΩ.

Output Latch (Bus Hold)

All pins have a programmable circuit that weakly holds

the previously driven state when all drivers connected to

the pin (including the pin's output driver as well as any

other devices connected to the pin by external bus) are

tristated.

Table 2. Adjacent I/O Cells (Mapping of ispGDX160V/VA)

Data C/

MUXOUT

Reflected

I/O Cells

Normal

I/O Cells

B20 B21 B22 B23 D16 D17 D18 D19 D20 D21 D22 D23 B16 B17 B18 B19

Data A/

MUXOUT

B22 B23 B24 B25 D18 D19 D20 D21 D18 D19 D20 D21 B14 B15 B16 B17

Data B/

MUXOUT

B21 B22 B23 B24 D17 D18 D19 D20 D19 D20 D21 D22 B15 B16 B17 B18

B19 B20 B21 B22 D15 D16 D17 D18 D21 D22 D23 D24 B17 B18 B19 B20

Data D/

MUXOUT

B18 B19 B20 B21 D14 D15 D16 D17 D22 D23 D24 D25 B18 B19 B20 B21

ispGDX160VA New Features

Unique to the ispGDX160VA are user-programmable

I/Os supporting either 3.3V or 2.5V output voltage level

options. The ispGDX160VA uses a VCCIO pin to provide

the 2.5V reference voltage when used. The ispGDX160VA

VCCIO pin occupies the same location as VCC on the

ispGDX160V, allowing drop-in replacement. The

ispGDX160VA offers improved performance by reducing

fanout delays and has PCI compatible drive capability.

Only the ispGDX160VA is available in the fastest (3.5ns)

Commercial speed grade and in -5,-7, and -9ns Industrial

grades in all packages.

The ispGDX160VA has a device ID different from the

ispGDX160V requiring that the latest Lattice download

software be used for programming and verification. Al-

though the ispGDX160VA and ispGDX160V are

functionally equivalent, they are not 100% JEDEC com-

patible. All design files must be recompiled targeting the

ispGDX160VA.

Applications

Specifications ispGDX160V/VA

The ispGDXV/VA Family architecture has been developed to deliver an in-system programmable signal routing solution with high speed and high flexibility. The devices are targeted for three similar but distinct classes of endsystem applications:

Programmable, Random Signal Interconnect (PRSI)

This class includes PCB-level programmable signal routing and may be used to provide arbitrary signal swapping between chips. It opens up the possibilities of programmable system hardware. It is characterized by the need to provide a large number of 1:1 pin connections which are statically configured, i.e., the pin-to-pin paths do not need to change dynamically in response to control inputs.

Programmable Data Path (PDP)

This application area includes system data path transceiver, MUX and latch functions. With today’s 32- and 64-bit microprocessor buses, but standard data path glue components still relegated primarily to eight bits, PCBs are frequently crammed with a dozen or more data path glue chips that use valuable real estate. Many of these applications consist of “on-board” bus and memory interfaces that do not require the very high drive of standard glue functions but can benefit from higher integration. Therefore, there is a need for a flexible means to integrate these on-board data path functions in an analogous way to programmable logic’s solution to control logic integration. Lattice’s CPLDs make an ideal control logic complement to the ispGDXV/VA in-system programmable data path devices as shown below.

Figure 4. ispGDXV/VA Complements Lattice CPLDs

Address

Inputs

(from P)

Control

Inputs

(from P)

Data Path

Bus #1

Programmable Switch Replacement (PSR)

Includes solid-state replacement and integration of me-

chanical DIP Switch and jumper functions. Through

in-system programming, pins of the ispGDXV/VA de-

vices can be driven to HIGH or LOW logic levels to

emulate the traditional device outputs. PSR functions do

not require any input pin connections.

These applications actually require somewhat different

silicon features. PRSI functions require that the device

support arbitrary signal routing on-chip between any two

pins with no routing restrictions. The routing connections

are static (determined at programming time) and each

input-to-output path operates independently. As a result,

there is little need for dynamic signal controls (OE,

clocks, etc.). Because the ispGDXV/VA device will inter-

face with control logic outputs from other components

(such as ispLSI or ispMACH) on the board (which fre-

quently change late in the design process as control logic

is finalized), there must be no restrictions on pin-to-pin

signal routing for this type of application.

PDP functions, on the other hand, require the ability to

dynamically switch signal routing (MUXing) as well as

latch and tri-state output signals. As a result, the pro-

grammable interconnect is used to define

routes that are then selected dynamically by control

signals from an external MPU or control logic. These

functions are usually formulated early in the conceptual

design of a product. The data path requirements are

driven by the microprocessor, bus and memory architec-

ture defined for the system. This part of the design is the

earliest portion of the system design frozen, and will not

usually change late in the design because the result

would be total system and PCB redesign. As a result, the

ability to accommodate

arbitrary

any pin-to-any pin rerouting is not a strong requirement as long as the designer has the ability to define his functions with a reasonable degree of freedom initially.

possible

signal

ispMACH

System

Clock(s)

ispLSI/ Device

Control

Outputs

Buffers / RegistersState Machines

ispGDXV/VA

Device

Buffers / RegistersDecoders

Data Path

Bus #2

ISP/JTAG

Interface

Configuration

(Switch) Outputs

As a result, the ispGDXV/VA architecture has been defined to support PSR and PRSI applications (including bidirectional paths) with no restrictions, while PDP applications (using dynamic MUXing) are supported with a minimal number of restrictions as described below. In this way, speed and cost can be optimized and the devices can still support the system designer’s needs.

The following diagrams illustrate several ispGDXV/VA applications.

Applications (Continued)

Specifications ispGDX160V/VA

Figure 5. Address Demultiplex/Data Buffering

XCVR

Control Bus

MUXed Address Data Bus

I/OA I/OB

OEA OEB

Address

Latch

CLK

Buffered Data

To Memory/ Peripherals

Address

Figure 6. Data Bus Byte Swapper

XCVR

I/OA

I/OB

OEA OEB

XCVR

I/OA I/OB

OEA OEB

D0-7

XCVR

I/OA I/OB

OEA OEB

XCVR

I/OA I/OB

OEA OEB

Control Bus

D0-7

Data Bus A

D8-15 D8-15

Data Bus B

Designing with the ispGDXV/VA

As mentioned earlier, this architecture satisfies the PRSI class of applications without restrictions: any I/O pin as a single input or bidirectional can drive any other I/O pin as output.

For the case of PDP applications, the designer does have to take into consideration the limitations on pins that can be used as control (MUX0, MUX1, OE, CLK) or data (MUXA-D) inputs. The restrictions on control inputs are not likely to cause any major design issues because the input possibilities span 25% of the total pins.

The MUXA-D input partitioning requires that designers consciously assign pinouts so that MUX inputs are in the appropriate, disjoint groups. For example, since the MUXA group includes I/O0-39 (160 I/O device), it is not possible to use I/O0 and I/O9 in the same MUX function. As previously discussed, data path functions will be assigned early in the design process and these restrictions are reasonable in order to optimize speed and cost.

User Electronic Signature

The ispGDXV/VA Family includes dedicated User Electronic Signature (UES) E2CMOS storage to allow users to code design-specific information into the devices to identify particular manufacturing dates, code revisions, or the like. The UES information is accessible through the boundary scan programming port via a specific command. This information can be read even when the security cell is programmed.

Figure 7. Four-Port Memory Interface

4-to-1

16-Bit MUX

Bidirectional

Port #1 OE1

Port #2 OE2

Bus 4

Bus 3

Bus 2

Bus 1

Note: All OE and SEL lines driven by external arbiter logic (not shown).

Port #3 OE3

Port #4 OE4

Memory

Port

OEM

SEL0

SEL1

To Memory

Security

The ispGDXV/VA Family includes a security feature that prevents reading the device program once set. Even when set, it does not inhibit reading the UES or device ID code. It can be erased only via a device bulk erase.

Specifications ispGDX160VA

Absolute Maximum Ratings

1,2

Supply Voltage Vcc................................. -0.5 to +5.4V

Input Voltage Applied............................... -0.5 to +5.6V

Off-State Output Voltage Applied ............ -0.5 to +5.6V

Storage Temperature................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (TJ) with Power Applied ... 150 °C

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).

2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.

DC Recommended Operating Conditions

SYMBOL

VCC VCCIO

PARAMETER

Supply Voltage

I/O Reference Voltage

Commercial Industrial

= 0°C to +70°C

= -40°C to +85°C

MIN. MAX. UNITS

3.00

3.00 3.60 V

2.3

3.60

Table 2-0005/gdx160va

Capacitance (TA=25oC, f=1.0 MHz)

SYMBOL

I/O Capacitance

Dedicated Clock Capacitance

PARAMETER PACKAGE TYPE

BGA, fpBGA

PQFP

BGA, fpBGA

UNITSTYPICAL TEST CONDITIONS

7PQFP

10 pf

V = 3.3V, V = 2.0V

CC Y

I/O

Table 2-0006/gdx160va

Erase/Reprogram Specifications

PARAMETER MINIMUM MAXIMUM UNITS

Erase/Reprogram Cycles 10,000 — Cycles

Switching Test Conditions

CCIO

Device Output

Test

Point

includes Test Fixture and Probe Capacitance.

0213D

Input Pulse Levels Input Rise and Fall Time

Input Timing Reference Levels Output Timing Reference Levels Output Load

3-state levels are measured 0.5V from steady-state active level.

Output Load Conditions (See Figure 8)

3.3V 2.5V

TEST CONDITION R1

A 35pF

Active High

Active Low Active High to Z

at V -0.5V

D 35pF

Active Low to Z at V +0.5V

Slow Slew

R1 R2

153Ω

∞

153Ω

∞

153Ω

∞

GND to V

< 1.5ns 10% to 90%

V V

See Figure 8

156Ω

134Ω 134Ω

∞

134Ω

∞ ∞

∞

156Ω

∞

156Ω

∞

CCIO(MIN)

CCIO(MIN) CCIO(MIN)

/2 /2

R2 CL

144Ω 144Ω

35pF

∞

35pF

144Ω

∞ ∞

Table 2-0004A/gdx160va

Specifications ispGDX160VA

Figure 8. Test Load

5pF

DC Electrical Characteristics for 3.3V Range

Over Recommended Operating Conditions

SYMBOL

VCCIO VIL VIH

VOL

VOH

I/O Reference Voltage 3.0 –– 3.6 V Input Low Voltage Input High Voltage

Output Low Voltage

Output High Voltage

1. I/O voltage configuration must be set to VCC.

PARAMETER

VOH ≤ V VOH ≤ V

= V

CONDITION MIN. TYP. MAX. UNITS

0.8

or V

OUT

or V

OUT

CC (MIN)

≤ V

OUT OUT

≤ V

OL (MAX) OL(MAX)

IOL = +100µA

= +24mA

= -100µA

= -12mA

-0.3

2.0

– ––0.55 V

2.8

2.4 ––V

–

5.25

–

0.2

–

Table 2-0007/gdx160va

–

V V V

Specifications ispGDX160VA

DC Electrical Characteristics for 2.5V Range

Over Recommended Operating Conditions

SYMBOL

VCCIO VIL VIH

VOL

VOH

I/O Reference Voltage Input Low Voltage Input High Voltage

Output Low Voltage

Output High Voltage

PARAMETER

1. I/O voltage configuration must be set to VCCIO.

OH(MIN)

CCIO=MIN

CONDITION MIN. TYP. MAX. UNITS

≤ V ≤ V

, I , I

OUT OUT

= 100µA

= 8mA

= -100µA

= -8mA

or V or V

OUT OUT

≤ V ≤ V

OL(MAX)

2.3

-0.3

1.7

––0.2 V ––0.6 V

2.1 ––V

1.8

––

2.7

–

0.7

–

5.25

–

2.5V/gdx160va

DC Electrical Characteristics

Over Recommended Operating Conditions

SYMBOL

IIL IIH

IPU IBHLS

Input or I/O Low Leakage Current 0V ≤ V Input or I/O High Leakage Current

I/O Active Pullup Current Bus Hold Low Sustaining Current

IBHHS Bus Hold High Sustaining Current -40 ––µA IBHLO Bus Hold Low Overdrive Current ––550 µA IBHHO Bus Hold High Overdrive Current ––-550 µA IBHT IOS ICCQ

ICC

Bus Hold Trip Points

Output Short Circuit Current ––-250 mA

Quiescent Power Supply Current – 16.5 – mA Dynamic Power Supply Current

per Input Switching

PARAMETER

-0.2) ≤ V

CCIO

≤ VIN ≤ 5.25V

CCIO

≤ VIN ≤ V = V

IL (MAX)

VIN = V

IH (MIN)

0V ≤ V

= 3.3V, V

= 0.5V, V

One input toggling at 50% duty cycle, outputs open.

CONDITION MIN. TYP.2MAX. UNITS

≤ V

IL (MAX)

≤ V

IL (MAX)

CCIO

– – – –

40 ––µA

≤ V

CCIO

≤ V

CCIO

= 0.5V, TA = 25°C

OUT

= V

– V

– See

Note 3

-10 10 50

-200

– mA/

V V V

µA µA µA µA

MHz

Maximum Continuous I/O Pin Sink

ICONT

Current Through Any GND Pin

1. One output at a time for a maximum of one second. V

–

= 0.5V was selected to avoid test problems by

OUT

––160 mA

tester ground degradation. Characterized, but not 100% tested.

2. Typical values are at V

= 3.3V and T

= 25°C.

3. ICC / MHz = (0.003 x I/O cell fanout) + 0.029. e.g. An input driving four I/O cells at 40MHz results in a dynamic I

of approximately ((0.003 x 4) + 0.029) x 40 = 1.64mA.

4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bi-directionals.

5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin.

DC Char_gdx160va

External Timing Parameters

Over Recommended Operating Conditions

Specifications ispGDX160VA

PARAMETER

tpd

tsel

TEST COND.

fmax (Tog.) fmax (Ext.) tsu1 tsu2 tsu3 tsu4 tsuce1 tsuce2 tsuce3 th1 th2 th3 th4 thce1 thce2 thce3

tgco1

tgco2

tco1

tco2

ten

tdis

ttoeen

ttoedis twh twl trst trw tsl tsk

1. All timings measured with one output switching, fast output slew rate setting, except tsl.

2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is

used as I/O voltage reference.

A A

– – – – – – – – – – – – – – – –

A A A A B C B C

– – – –

D A

Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX)

Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX)

Clock Frequency, Max. Toggle

Clock Frequency with External Feedback

Input Latch or Register Setup Time Before Y

Input Latch or Register Setup Time Before I/O Clock

Output Latch or Register Setup Time Before Y

Output Latch or Register Setup Time Before I/O Clock

Global Clock Enable Setup Time Before Y

Global Clock Enable Setup Time Before I/O Clock

I/O Clock Enable Setup Time Before Y

Input Latch or Reg. Hold Time (Yx)

Input Latch or Reg. Hold Time (I/O Clock)

Output Latch or Reg. Hold Time (Y

Output Latch or Reg. Hold Time (I/O Clock)

Global Clock Enable Hold Time (Y

Global Clock Enable Hold Time (I/O Clock)

I/O Clock Enable Hold Time (Y

Output Latch or Reg. Clock (from Y

Input Latch or Register Clock (from Y

Output Latch or Register Clock (from I/O pin) to Output Delay

Input Latch or Register Clock (from I/O pin) to Output Delay

Input to Output Enable

Input to Output Disable

Test OE Output Enable

Test OE Output Disable

Clock Pulse Duration, High

Clock Pulse Duration, Low

Reset Pulse Width

Output Delay Adder for Output Timings Using Slow Slew Rate

Output Skew (tgco1 Across Chip)

DESCRIPTION

)

) to Output Delay

( )

tsu3+tgco1

-3

MIN. MAX.

3.5

–

3.5

–

250

3.0

2.5

2.0

2.5

1.5

3.0

0.0

0.5

0.0

1.0

0.0

1.0

0.0

– – – – – – – –

2.0

–

5.0

– –

– – – – – – – – – – – – – – –

3.5

6.0

4.0

7.0

5.0

6.0

– –

8.0

–

3.5

0.5

166.7

-5

MIN. MAX.

5.0

–

5.0

–

4.0

3.0

4.0

3.0

2.5

1.5

4.5

0.0

1.5

0.0

1.5

0.0

1.5

0.0

– – – – – – – –

3.5

–

– –

– – – – – – – – – – – – – – – –

5.0

8.5

6.0

9.5

6.0

– –

14.0

–

5.0

0.5

143 111

10.0

UNITS

MHz MHz

ns ns

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

External Timing Parameters

Over Recommended Operating Conditions

Specifications ispGDX160VA

PARAMETER

tpd

tsel

TEST COND.

fmax (Tog.) fmax (Ext.) tsu1 tsu2 tsu3 tsu4 tsuce1 tsuce2 tsuce3 th1 th2 th3 th4 thce1 thce2 thce3

tgco1

tgco2

tco1

tco2

ten

tdis

ttoeen

ttoedis twh twl trst trw tsl tsk

1. All timings measured with one output switching, fast output slew rate setting, except tsl.

2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is

used as I/O voltage reference.

A A

– – – – – – – – – – – – – – – –

A A A A B C B C

– – – –

D A

Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX)

Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX)

Clock Frequency, Max. Toggle

Clock Frequency with External Feedback

Input Latch or Register Setup Time Before Y

Input Latch or Register Setup Time Before I/O Clock

Output Latch or Register Setup Time Before Y

Output Latch or Register Setup Time Before I/O Clock

Global Clock Enable Setup Time Before Y

Global Clock Enable Setup Time Before I/O Clock

I/O Clock Enable Setup Time Before Y

Input Latch or Reg. Hold Time (Yx)

Input Latch or Reg. Hold Time (I/O Clock)

Output Latch or Reg. Hold Time (Y

Output Latch or Reg. Hold Time (I/O Clock)

Global Clock Enable Hold Time (Y

Global Clock Enable Hold Time (I/O Clock)

I/O Clock Enable Hold Time (Y

Output Latch or Reg. Clock (from Y

Input Latch or Register Clock (from Y

Output Latch or Register Clock (from I/O pin) to Output Delay

Input Latch or Register Clock (from I/O pin) to Output Delay

Input to Output Enable

Input to Output Disable

Test OE Output Enable

Test OE Output Disable

Clock Pulse Duration, High

Clock Pulse Duration, Low

Reset Pulse Width

Output Delay Adder for Output Timings Using Slow Slew Rate

Output Skew (tgco1 Across Chip)

DESCRIPTION

)

) to Output Delay

( )

tsu3+tgco1

-7

MIN. MAX.

–

7.0

–

7.0

100

–

5.5

–

4.5

–

5.5

–

4.5

–

3.5

–

2.5

–

6.5

–

0.0

–

2.5

–

0.0

–

2.5

–

0.0

–

2.5

–

0.0

–

7.0

–

11.0

–

9.0

–

13.0

–

8.5

–

8.5

–

8.5

–

8.5

5.0

–

5.0

–

18.0

14.0

–

7.0

–

0.5

-9

MIN. MAX.

9.0

–

9.0

–

7.0

6.0

7.0

6.0

4.0

3.0

8.5

0.0

3.0

0.0

3.0

0.0

3.0

0.0

– – – – – – – –

6.0

–

– –

– – – – – – – – – – – – – – –

9.0

13.5

11.5

15.7

10.5

– –

22.0

–

9.0

1.0

62.5

18.0

UNITS

MHz MHz

ns ns

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

External Timing Parameters (Continued)

Specifications ispGDX160VA

ispGDX160VA timings are specified with a GRP load (fanout) of four I/O cells. The figure below shows the ∆ GRP Delay with increased GRP loads. These deltas

ispGDX160VA Maximum ∆ GRP Delay vs. I/O Cell Fanout

1.6

1.4

1.2

1.0

0.8

0.6

∆ GRP Delay (ns)

0.4

0.2

0.0 0 4 10 20 30 40 50 60 70

I/O Cell Fanout

apply to any signal path traversing the GRP (MUXA-D, OE, CLK/CLKEN, MUXsel0-1). Global Clock signals which do not use the GRP have no fanout delay adder.

Specifications ispGDX160VA

Internal Timing Parameters

Over Recommended Operating Conditions

PARAMETER # DESCRIPTION

Inputs t

32 Input Buffer Delay — 0.4 — 0.9 ns

GRP t

grp

33 GRP Delay — 1.1 — 1.1 ns

MUX t

muxd

muxexp

muxs

muxsio

muxsg

muxselexp

34 I/O Cell MUX A/B/C/D Data Delay — 1.0 — 1.5 ns 35 I/O Cell MUX A/B/C/D Expander Delay — 1.5 — 2.0 ns 36 I/O Cell Data Select — 1.0 — 1.5 ns 37 I/O Cell Data Select (I/O Clock) — 1.5 — 3.0 ns 38 I/O Cell Data Select (Yx Clock) — 1.5 — 2.0 ns 39 I/O Cell MUX Data Select Expander Delay — 1.5 — 2.0 ns

iolat

iosu

ioh

ioco

ior

cesu

ceh

40 I/O Latch Delay — 1.0 — 1.0 ns 41 I/O Register Setup Time Before Clock — 0.8 — 2.0 ns 42 I/O Register Hold Time After Clock — 1.7 — 1.5 ns 43 I/O Register Clock to Output Delay — 1.2 — 0.5 ns 44 I/O Reset to Output Delay — 1.0 — 1.5 ns 45 I/O Clock Enable Setup Time Before Clock — 2.3 — 2.0 ns 46 I/O Clock Enable Hold Time After Clock — 0.2 — 0.5 ns

Data Path t

fdbk

iobp

ioob

muxcg

muxcio

iodg

iodio

47 I/O Register Feedback Delay — 0.6 — 0.9 ns 48 I/O Register Bypass Delay — 0.0 — 0.0 ns 49 I/O Register Output Buffer Delay — 0.0 — 0.0 ns 50 I/O Register A/B/C/D Data Input MUX Delay (Yx Clock) — 1.5 — 2.0 ns 51 I/O Register A/B/C/D Data Input MUX Delay (I/O Clock) — 1.5 — 3.0 ns 52 I/O Register I/O MUX Delay (Yx Clock) — 3.5 — 4.0 ns 53 I/O Register I/O MUX Delay (I/O Clock) — 3.5 — 5.0 ns

Outputs t

obs

oeen

oedis

goe

toe

54 Output Buffer Delay — 1.0 — 1.5 ns 55 Output Buffer Delay (Slow Slew Option) — 4.5 — 6.5 ns 56 I/O Cell OE to Output Enable — 3.5 — 4.0 ns 57 I/O Cell OE to Output Disable — 3.5 — 4.0 ns 58 GRP Output Enable and Disable Delay — 0.0 — 0.0 ns 59 Test OE Enable and Disable Delay — 2.5 — 2.0 ns

Clocks t

ioclk

gclk

gclkeng

gclkenio

ioclkeng

60 I/O Clock Delay — 0.3 — 2.0 ns 61 Global Clock Delay — 1.3 — 2.0 ns 62 Global Clock Enable (Yx Clock) — 1.5 — 2.5 ns 63 Global Clock Enable (I/O Clock) — 1.0 — 3.5 ns 64 I/O Clock Enable (Yx Clock) — 0.5 — 2.5 ns

Global Reset

65 Global Reset to I/O Register Latch — 6.0 — 11.0 ns

1. Internal Timing Parameters are not tested and are for reference only .

2. Refer to the Timing Model in this data sheet for further details.

-3 -5

MIN. MAX. MIN. MAX. UNITS

Specifications ispGDX160VA

Internal Timing Parameters

Over Recommended Operating Conditions

PARAMETER # DESCRIPTION

Inputs t

32 Input Buffer Delay — 1.4 — 1.9 ns

GRP t

grp

33 GRP Delay — 1.1 — 1.1 ns

MUX t

muxd

muxexp

muxs

muxsio

muxsg

muxselexp

34 I/O Cell MUX A/B/C/D Data Delay — 2.0 — 2.5 ns 35 I/O Cell MUX A/B/C/D Expander Delay — 2.5 — 3.0 ns 36 I/O Cell Data Select — 2.0 — 2.5 ns 37 I/O Cell Data Select (I/O Clock) — 4.5 — 6.0 ns 38 I/O Cell Data Select (Yx Clock) — 2.5 — 3.0 ns 39 I/O Cell MUX Data Select Expander Delay — 2.5 — 3.0 ns

iolat

iosu

ioh

ioco

ior

cesu

ceh

40 I/O Latch Delay — 1.0 — 1.0 ns 41 I/O Register Setup Time Before Clock — 3.2 — 4.4 ns 42 I/O Register Hold Time After Clock — 2.3 — 2.6 ns 43 I/O Register Clock to Output Delay — 0.5 — 0.5 ns 44 I/O Reset to Output Delay — 1.5 — 1.5 ns 45 I/O Clock Enable Setup Time Before Clock — 2.5 — 2.0 ns 46 I/O Clock Enable Hold Time After Clock — 1.0 — 2.0 ns

Data Path t

fdbk

iobp

ioob

muxcg

muxcio

iodg

iodio

47 I/O Register Feedback Delay — 1.2 — 1.3 ns 48 I/O Register Bypass Delay — 0.3 — 0.6 ns 49 I/O Register Output Buffer Delay — 0.6 — 0.7 ns 50 I/O Register A/B/C/D Data Input MUX Delay (Yx Clock) — 2.5 — 3.0 ns 51 I/O Register A/B/C/D Data Input MUX Delay (I/O Clock) — 4.5 — 6.0 ns 52 I/O Register I/O MUX Delay (Yx Clock) — 5.0 — 6.0 ns 53 I/O Register I/O MUX Delay (I/O Clock) — 7.0 — 9.0 ns

Outputs t

obs

oeen

oedis

goe

toe

54 Output Buffer Delay — 2.2 — 2.9 ns 55 Output Buffer Delay (Slow Slew Option) — 9.2 — 11.9 ns 56 I/O Cell OE to Output Enable — 6.0 — 7.5 ns 57 I/O Cell OE to Output Disable — 6.0 — 7.5 ns 58 GRP Output Enable and Disable Delay — 0.0 — 0.0 ns 59 Test OE Enable and Disable Delay — 2.5 — 3.0 ns

Clocks t

ioclk

gclk

gclkeng

gclkenio

ioclkeng

60 I/O Clock Delay — 3.2 — 4.4 ns 61 Global Clock Delay — 2.7 — 3.4 ns 62 Global Clock Enable (Yx Clock) — 3.7 — 5.4 ns 63 Global Clock Enable (I/O Clock) — 5.7 — 8.4 ns 64 I/O Clock Enable (Yx Clock) — 4.2 — 6.4 ns

Global Reset

65 Global Reset to I/O Register Latch — 13.7 — 16.4 ns

1. Internal Timing Parameters are not tested and are for reference only .

2. Refer to the Timing Model in this data sheet for further details.

-7 -9

MIN. MAX. MIN. MAX. UNITS

Specifications ispGDX160V

Absolute Maximum Ratings

1,2

Supply Voltage Vcc................................. -0.5 to +5.4V

Input Voltage Applied............................... -0.5 to +5.6V

Off-State Output Voltage Applied ............ -0.5 to +5.6V

Storage Temperature................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (TJ) with Power Applied ... 150°C

2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.

DC Recommended Operating Conditions

SYMBOL

1. Typical 100mV of input hysteresis.

Supply Voltage

Input Low Voltage Input High Voltage

PARAMETER

Commercial Industrial

TA = 0°C to +70°C

= -40°C to +85°C

MIN. MAX. UNITS

3.0

-0.3

2.0

3.6

0.8

5.25

V V V V

Table 2-0005/gdxv

Capacitance (TA=25oC, f=1.0 MHz)

SYMBOL

PARAMETER

Dedicated Clock Capacitance

8I/O Capacitance

UNITSTYPICAL TEST CONDITIONS

pf pf

V = 3.3V, V = 2.0V

CC Y

I/O

Erase/Reprogram Specifications

PARAMETER MINIMUM MAXIMUM UNITS

Erase/Reprogram Cycles 10,000 — Cycles

Table 2 - 0006

Switching Test Conditions

+ 3.3V

Device Output

Test

Point

includes Test Fixture and Probe Capacitance.

Input Pulse Levels GND to 3.0V Input Rise and Fall Time ≤ 1.5ns 10% to 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load See figure at right

3-state levels are measured 0.5V from steady-state active level.

Output Load Conditions

TEST CONDITION R1 R2 CL

A 153Ω 134Ω 35pF

Active High

Active Low Active High to Z

at V -0.5V

Active Low to Z at V +0.5V

Slow Slew

∞

153Ω

∞

153Ω

∞

134Ω 35pF

∞

134Ω 5pF

∞ ∞

Table 2-0004A

Specifications ispGDX160V

35pF

5pF

35pF

DC Electrical Characteristics

Over Recommended Operating Conditions

– – – – – – – – – – –

See

Note 3

–

0.55

–

-10 10

-150

– –

550

-550 V

-250

– –

SYMBOL

VOL VOH IIL IIH IIL-PU IBHLS IBHHS IBHLO IBHHO IBHT

IOS

ICCQ ICC

ICONT

Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current I/O Active Pull-Up Current Bus Hold Low Sustaining Current Bus Hold High Sustaining Current Bus Hold Low Overdrive Current Bus Hold High Overdrive Current Bus Hold Trip Points Output Short Circuit Current Quiescent Power Supply Current Dynamic Power Supply Current

per Input Switching

Maximum Continuous I/O Pin Sink

PARAMETER

CONDITION

=24 mA

=-12 mA

0V ≤ V V 0V ≤ V VIN = V V 0V ≤ V 0V ≤ VIN ≤ V

VCC = 3.3V, V V

≤ VIL (Max.)

≤ VIN ≤ 5.25V

≤ V

(Max.)

= V

(Min.)

≤ V

= 0.5V, V

= 0.5V, TA = 25˚C

OUT

= V

One input toggling @ 50% duty cycle, outputs open.

MIN. MAX.TYP.

–

2.4

– – –

-50

– –

– – –

–

Current Through Any GND Pin

1. One output at a time for a maximum duration of one second. V

2. Typical values are at VCC = 3.3V and T

3. I

4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bidirectionals.

degradation. Characterized but not 100% tested.

= 25oC.

/ MHz = (0.01 x I/O cell fanout) + 0.04

e.g. An input driving four I/O cells at 40 MHz results in a dynamic ICC of approximately ((0.01 x 4) + 0.04) x 40 = 3.2 mA.

= 0.5V was selected to avoid test problems by tester ground

OUT

5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin.

UNITS

V V

µA µA µA µA µA µA µA

V mA mA

mA/MHz

External Timing Parameters

Over Recommended Operating Conditions

Specifications ispGDX160V

TEST COND.

tpd tsel fmax (Tog.) fmax (Ext.) tsu1 tsu2 tsu3 tsu4 tsuce1 tsuce2 tsuce3 th1 th2 th3 th4 thce1 thce2 thce3 tgco1 tgco2 tco1 tco2 ten tdis ttoeen ttoedis twh twl trst trw tsl tsk

1. All timings measured with one output switching, fast output slew rate setting, except tsl.

A A

– – – – – – – – – – – – – – – –

A A A A B C B C

– – – –

D A

Data Prop. Delay from Any I/O pin to Any I/O pin (4:1 MUX)

Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX)

Clock Frequency, Max. Toggle

Clock Frequency with External Feedback

Input Latch or Register Setup Time Before Y

Input Latch or Register Setup Time Before I/O Clock

Output Latch or Register Setup Time Before Y

Output Latch or Register Setup Time Before I/O Clock

Global Clock Enable Setup Time Before Y

Global Clock Enable Setup Time Before I/O Clock

I/O Clock Enable Setup Time Before Y

Input Latch or Register Hold Time (Yx)

Input Latch or Register Hold Time (I/O Clock)

Output Latch or Register Hold Time (Y

Output Latch or Register Hold Time (I/O Clock)

Global Clock Enable Hold Time (Y

Global Clock Enable Hold Time (I/O Clock)

I/O Clock Enable Hold Time (Y

Output Latch or Register Clock (from Y

Input Latch or Register Clock (from Y

Output Latch or Register Clock (from I/O pin) to Output Delay

Input Latch or Register Clock (from I/O pin) to Output Delay

Input to Output Enable

Input to Output Disable

Test OE Output Enable

Test OE Output Disable

Clock Pulse Duration, High

Clock Pulse Duration, Low

Reset Pulse Width

Output Delay Adder for Output Timings Using Slow Slew Rate

Output Skew (tgco1 Across Chip)

DESCRIPTIONPARAMETER

( )

tsu3+tgco1

)

) to Output Delay

-5

MIN. MAX.

–

5.0

–

6.5 143 110

10.0

4.0

3.0

4.0

3.0

2.5

1.5

4.5

0.0

1.5

0.0

1.5

0.0

1.5

0.0

– – – – – – – –

3.5

–

– –

– – – – – – – – – – – – – – – –

5.0

8.5

6.0

9.5

6.0

9.0

– –

14.0

–

8.0

0.5

-7

MIN. MAX.

–

7.0

–

9.0

100

80.0

14.0

5.5

4.5

5.5

4.5

3.5

2.5

6.5

0.0

2.5

0.0

2.5

0.0

2.5

0.0

– – – – – – – –

5.0

–

– –

– – – – – – – – – – – – – – – –

7.0

11.0

9.0

13.0

8.5

12.0

– –

18.0

–

12.0

0.5

UNITS

ns MHz MHz

External Timing Parameters (Continued)

Specifications ispGDX160V

ispGDX160V timings are specified with a GRP load (fanout) of four I/O cells. The figure below shows the ∆ GRP Delay with increased GRP loads. These deltas

ispGDX160V Maximum ∆ GRP Delay vs. I/O Cell Fanout

8 6

∆ GRP Delay (ns)

0104 203040506070

apply to any signal path traversing the GRP (MUXA-D, OE, CLK/CLKEN, MUXsel0-1). Global Clock signals which do not use the GRP have no fanout delay adder.

I/O Cell Fanout

Specifications ispGDX160V

Internal Timing Parameters

Over Recommended Operating Conditions

PARAMETER # DESCRIPTION

Inputs t

32 Input Buffer Delay — 0.9 — 1.4 ns

GRP t

grp

33 GRP Delay — 1.1 — 1.1 ns

MUX t

muxd

muxexp

muxs

muxsio

muxsg

muxselexp

34 I/O Cell MUX A/B/C/D Data Delay — 1.5 — 2.0 ns 35 I/O Cell MUX A/B/C/D Expander Delay — 2.0 — 2.5 ns 36 I/O Cell Data Select — 3.0 — 4.0 ns 37 I/O Cell Data Select (I/O Clk) — 4.5 — 6.5 ns 38 I/O Cell Data Select (Yx Clk) — 3.5 — 4.5 ns 39 I/O Cell MUX Data Select Expander Delay — 3.5 — 4.5 ns

iolat

iosu

ioh

ioco

ior

cesu

ceh

40 I/O Latch Delay — 1.0 — 1.0 ns 41 I/O Register Setup Time Before Clock — 2.0 — 3.2 ns 42 I/O Register Hold Time After Clock — 1.5 — 2.3 ns 43 I/O Register Clock to Output Delay — 0.5 — 0.5 ns 44 I/O Reset to Output Delay — 1.5 — 1.5 ns 45 I/O Clock Enable Setup Time Before Clock — 2.0 — 2.5 ns 46 I/O Clock Enable Hold Time After Clock — 0.5 — 1.0 ns

Data Path t

fdbk

iobp

ioob

muxcg

muxcio

iodg

iodio

47 I/O Register Feedback Delay — 0.9 — 1.2 ns 48 I/O Register Bypass Delay — 0.0 — 0.3 ns 49 I/O Register Output Buffer Delay — 0.0 — 0.6 ns 50 I/O Register A/B/C/D Data Input MUX Delay (Yx Clk) — 2.0 — 2.5 ns 51 I/O Register A/B/C/D Data Input MUX Delay (I/O Clk) — 3.0 — 4.5 ns 52 I/O Register I/O MUX Delay (Yx Clk) — 4.0 — 5.0 ns 53 I/O Register I/O MUX Delay (I/O Clk) — 5.0 — 7.0 ns

Outputs t

obs

oeen

oedis

goe

toe

54 Output Buffer Delay — 1.5 — 2.2 ns 55 Output Buffer Delay (Slow Slew Option) — 9.5 — 14.2 ns 56 I/O Cell OE to Output Enable — 4.0 — 6.0 ns 57 I/O Cell OE to Output Disable — 4.0 — 6.0 ns 58 GRP Output Enable and Disable Delay — 0.0 — 0.0 ns 59 Test OE Enable and Disable Delay — 5.0 — 6.0 ns

Clocks t

ioclk

gclk

gclkeng

gclkenio

ioclkeng

60 I/O Clock Delay — 2.0 — 3.2 ns 61 Global Clock Delay — 2.0 — 2.7 ns 62 Global Clock Enable (Yx Clk) — 2.5 — 3.7 ns 63 Global Clock Enable (I/O Clk) — 3.5 — 5.7 ns 64 I/O Clock Enable (Yx Clk) — 2.5 — 4.2 ns

Global Reset

65 Global Reset to I/O Register Latch — 11.0 — 13.7 ns

1. Internal Timing Parameters are not tested and are for reference only .

2. Refer to the Timing Model in this data sheet for further details.

-5 -7

MIN. MAX. MIN. MAX. UNITS

Switching Waveforms

Specifications ispGDX160V/VA

MUXSEL (I/O INPUT)

DATA (I/O INPUT)

COMBINATORIAL I/O OUTPUT

OE (I/O INPUT)

COMBINATORIAL I/O OUTPUT

CLK (I/O INPUT)

VALID INPUT

sel

VALID INPUT

Combinatorial Output

dis

I/O Output Enable/Disable

Clock Width

DATA (I/O INPUT)

CLK

REGISTERED I/O OUTPUT

CLKEN

RESET

REGISTERED I/O OUTPUT

VALID INPUT

1/fmax

gco

ceh

(external fdbk)

suce

Registered Output

rst

Reset

ispGDXV Timing Model

MUX Expander Input

A B C D

MUX0 MUX1

GRP

tgrp #33

CLKEN CLK

Y0,1,2,3

tioclkeg #64

tioclk #60

tgclk #61

tmuxd #34 tmuxs #36 tmuxio #37 tmuxg #38 tmuxcg #50 tmuxcio #51

tiod #52, #53

tio #32

tgoe #58

tmuxexp #35

tmuxselexp #39

tiolat #40 tiosu #41 tioh #42 tioco #43 tior #44 tcesu #45 tceh #46

MUX Expander Output

tiobp #48

CLKEN

CLK

tfdbk #47

tioob #49

tgr #65

TOE

ttoe #59

I/O Pin

tob #54 tobs #55 toeen #56 toedis #57

RESET

0902/gdx160v/va

Y0,1,2,3, Enable

tgclkeng #62 tgclkenio #63

ispGDX Development System

Specifications ispGDX160V/VA

The ispGDX Development System supports ispGDX design using a simple language syntax and an easy-touse Graphical User Interface (GUI) called Design Manager. From creation to In-System Programming, the ispGDX system is an easy-to-use, self-contained design tool delivered on CD-ROM media.

Features

• Easy-to-use Text Entry System

• ispGDX Design Compiler

- Design Rule Checker

- I/O Connectivity Checker

- Automatic Compiler Function

• Industry Standard JEDEC File for Programming

• Min / Max Timing Report

• Interfaces To Popular Timing Simulators

• User Electronic Signature (UES) Support

• Detailed Log and Report Files For Easy Design Debug

• On-Line Help

• Windows® 3.1x, Windows 95, Windows 98 and Win-

dows NT® Compatible Graphical User Interface

• SUN O/S, Command Line Driven version available

PC Version

With the ispGDX GUI for the PC, command line entry is not required. The tools run under Microsoft Windows 3.1, Windows 95, Windows 98 and Windows NT. When the ispGDX software is invoked, the Design Manager and an accompanying message window are displayed. The Design Manager consists of the Menu Bar, Tool Bar,

Status Bar and the work area. The figure below shows these elements of the ispGDX GUI.

The Menu Bar displays topics related to functions used in the design process. Access the various drop-down menus and submenus by using the mouse or “hot” keys. The menu items available in the ispGDX system are FILE, EDIT, DEVICE, INVOKE, INTERFACES, VIEW, WINDOW and HELP.

The Tool Bar is a quick and easy way to perform many of the functions found in the menus with a single click of the mouse. File, Edit, Undo, Redo, Find, Print Download and Compiler are just some of the Icons found in the ispGDX Tool Bar. For instance, the Compiler Icon performs the same function as the Invoke => Compiler menu commands, including design analysis and rule checking and the fitting operation.

The Status Bar displays action prompts and the line and column numbers reflect the location of the cursor within the message window or the work area.

Workstation Version

The ispGDX software is also available for use under the Sun O/S 4.1.x or Solaris 2.4 or 2.5. The Sun version of the ispGDX software is invoked from the command line under the UNIX operating system. A GUI is not supported in this environment.

In the UNIX environment, the ispGDX Design File (GDF) must be created using a text editor. Once the GDF has been created, invoke the ispGDX workstation software from the UNIX command line. The following is an example of how to invoke ispGDX software.

Lattice’s ispGDX Development System Interface

Usage:

ispGDX [-i input_file] [-of[edif|orcad|viewlogic|verilog|vhdl]] [-p part name] [-r par_file]

Where:

-i input_file ispGDX design file

-of [edif | orcad | viewlogic | Output format verilog | vhdl]

-p part_name ispGDX part number

-r par_file Read parameters from parameter file

Type Dot Ext. Description

MUX Input

MUX

Selection

Control

MUX

Output

.M0 MUXA Data input to 4:1 MUX .M1 MUXB Data input to 4:1 MUX

MUX0 Selection input to 4:1 MUX MUX1 Selection input to 4:1 MUX

.M2 MUXC Data Input to 4:1 MUX .M3

.S0 .S1

MUXD Data input to 4:1 MUX

.CLK Clock for a register

.CE Clock enable for register clock

.A Adjacent MUX output of an I/O cell

.EN Latch enable for a latch signal .OE Output enable for 3-state output

or bidirectional signal

ispGDXV Dot Ext

ispGDX Development System (Continued)

Specifications ispGDX160V/VA

The GDF File

The GDF file is a simple text description of the design function, device and pin parameters. The file has four parts: device selection, set and constant statements, a pin section and a connection section. A sample file looks like this:

// 32-Bit Data 3 to 1 Mux

DESIGN datamux;

PART ispGDX160V-7Q208; PARAM SECURITY ON; PARAM OPENDRAIN ON; // USE OPEN DRAIN

// OPTION

PARAM PULL HOLD; // USE BUS HOLD

// LATCH OPTION

SET BUS_A [dataA31..dataA0]; SET BUS_B [dataB31..dataB0]; SET BUS_C [dataC31..dataC0]; SET BUS_D [dataD31..dataD0];

INPUT BUS_A {A31..A0}; INPUT BUS_B {B31..B0}; INPUT BUS_C {C31..C0}; OUTPUT BUS_D {D31..D0};

This example shows a simple, but complete, 32-bit 3:1 MUX design. Once completed, the compiler takes over.

Powerful Syntax

Lattice’s ispGDX Design System uses simple, but powerful, syntax to easily define a design. The !(bang) operator controls pin polarity and can be used in both the pin and connection sections of the design definition. Dot extensions define data inputs, select controls for the 4:1 multiplexor, and control inputs of sequential elements and tri-state buffers. Dot extensions are .M# (MUX Input), .S# (MUX Select), and control functions, such as .CLK, .EN, .OE and .A (shown in adjacent table). Pin Attributes are assigned in the pin section of the GDF as well. SLOWSLEW selects the slow slew rate for an output buffer. The Pull parameter can be used to select the internal pull-up or bus hold latch. OPEN drain can be used to select open drain operation. The COMB attribute distinguishes the structure for bidirectional pins. If COMB is used, the input register, or latch, of an output buffer will be applied to bidirectional pins.

Please consult the ispGDX Development System Manual for full details.

ispGDX GDF File Dot Extensions

INPUT [oe] {B37}; INPUT [clk] {B36};

INPUT [sel1] {B38}; INPUT [sel0] {B39};

BEGIN

BUS_D.m0 = BUS_A; BUS_D.m1 = BUS_B;

END

BUS_D.m2 = BUS_C; BUS_D.m3 = VCC; // Default all

BUS_D.s1 = sel1; BUS_D.s0 = sel0;

BUS_D.oe = oe; BUS_D.clk = clk;

// outputs to VCC

ispGDX Development System (Continued)

Specifications ispGDX160V/VA

The ispGDX Design System Compiler

After the GDF file is created, the compiler checks the syntax and provides helpful hints and the location of any syntax errors. The compiler performs design rule checks, such as, clock and enable designations, the use of input/ output/BIDI usage, and the proper use of attributes. I/O connectivity is also checked to ensure polarity, MUX selection controls, and connections are properly made. Compilation is completed automatically and report and programming files are saved.

Reports Generated

When the ispGDX system compiles a design and generates the specified netlists, the following output files are created:

Report Files:

.log Compiler History .rpt Compiler Report .mfr Maximum Frequency Timing Report .tsu Set-up and Hold Timing Report .tco Clock to Out Timing Report .tpt Timing Report

Third-Party Timing Simulation

The ispGDX Design System will generate simulation netlists as specified by a user. The simulation netlist formats available are: EDIF, Verilog (OVI compliant), VHDL (VITAL compliant), Viewlogic, and OrCAD.

For In-System Programming, Lattice’s ispGDX devices may be programmed, alone or in a chain with up to 100 other Lattice ISP devices, using Lattice’s ISP Daisy Chain Download software. This powerful Windows-based tool can be launched from the Tool Bar or by Invoking the Download option from the drop down menu within the ispGDX Design System. ISP Daisy Chain Download version 7.1 or above supports the ispGDX Family devices.

Simulation File:

.sim Post-Route Simulation With LAC Format

Netlists:

.edo EDIF Output .vlo Verilog Output .ifo OrCAD Output .vho VHDL non-VITAL with Maximum Delays Output .vhn VHDL non-VITAL with Maximum Delays Output .vto VHDL VITAL Output

Download:

.jed JEDEC Device Programming File

In-System Programmability

Specifications ispGDX160V/VA

All necessary programming of the ispGDXV/VA is done via four TTL level logic interface signals. These four signals are fed into the on-chip programming circuitry where a state machine controls the programming.

On-chip programming can be accomplished using an IEEE 1149.1 boundary scan protocol. The IEEE 1149.1compliant interface signals are Test Data In (TDI), Test Data Out (TDO), Test Clock (TCK) and Test Mode Select (TMS) control. The EPEN pin is also used to enable or disable the JTAG port.

The embedded controller port enable pin (EPEN) is used to enable the JTAG tap controller and in that regard has similar functionality to a TRST pin. When the pin is driven high, the JTAG TAP controller is enabled. This is also true

Figure 9. ispJTAG Device Programming Interface

TDO

TDI

TMS

TCK

ispJTAG Programming Interface

EPEN

when the pin is left unconnected, in which case the pin is pulled high by the permanent internal pullup. This allows ISP programming and BSCAN testing to take place as specified by the Instruction Table.

When the pin is driven low, the JTAG TAP controller is driven to a reset state asynchronously. It stays there while the pin is held low. After pulling the pin high the JTAG controller becomes active. The intent of this feature is to allow the JTAG interface to be directly controlled by the data bus of an embedded controller (hence the name Embedded Port Enable). The EPEN signal is used as a “device select” to prevent spurious programming and/or testing from occuring due to random bit patterns on the data bus. Figure 9 illustrates the block diagram for the ispJTAG interface.

ispGDX

160V/VA

Device

ispLSI

Device

ispMACH

Device

ispGDX

160V/VA

Device

ispGDX

160V/VA

Device

Boundary Scan

Specifications ispGDX160V/VA

The ispGDXV/VA devices provide IEEE1149.1a test capability and ISP programming through a standard Boundary Scan Test Access Port (TAP) interface.

The boundary scan circuitry on the ispGDXV/VA Family operates independently of the programmed pattern. This

Figure 10. Boundary Scan Register Circuit for I/O Pins

SCANIN

(from previous

cell

BSCAN

Registers

DQ DQ

BSCAN Latches

allows customers using boundary scan test to have full test capability with only a single BSDL file.

The ispGDXV/VA devices are identified by the 32-bit JTAG IDCODE register. The device ID assignments are listed in Table 4.

HIGHZ

EXTEST

TOE

Normal

Function

EXTEST

PROG_MODE

Normal

Function

0 1

I/O Pin

Shift DR

Clock DR

Update DR

Reset

SCANOUT (to next cell)

Table 3. I/O Shift Register Order

I/O SHIFT REGISTER ORDERDEVICE

ispGDX160V/VA TDI, TOE, Y2, Y3, RESET, Y1, Y0, I/O B20 .. B39, I/O C0 .. C39, I/O D0 .. D19, I/O B19 .. B0,

I/O A39.. A0, I/O D39 .. D20, TDO

I/O Shift Reg Order/ispGDXVA

Table 4. ispGDX160V/VA Device ID Codes

32-BIT BOUNDARY SCAN ID CODEDEVICE

ispGDX160V 0000, 0000, 0011, 0101, 0011, 0000, 0100, 0011 ispGDX160VA 0001, 0000, 0011, 0101, 0011, 0000, 0100, 0011

ID Code/GDX160V/VA

Boundary Scan (Continued)

Specifications ispGDX160V/VA

The ispJTAG programming is accomplished by executing Lattice private instructions under the Boundary Scan State Machine.

Downlowad (ispDCD™), ispCODE ‘C’ routines or any third-party programmers. Contact Lattice Technical Support to obtain more detailed programming information.

Details of the programming sequence are transparent to the user and are handled by Lattice ISP Daisy Chain

Figure 11. Boundary Scan Register Circuit for Input-Only Pins

Input Pin

SCANIN

(from previous

cell

Shift DR

Clock DR

Figure 12. Boundary Scan State Machine

Test-Logic-Reset

Run-Test/Idle

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

SCANOUT (to next cell)

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

111

Pause-DR

Exit2-DR

Update-DR

Pause-IR

Exit2-IR

Update-IR

0101

Specifications ispGDX160V/VA

Boundary Scan (Continued)

Figure 13. Boundary Scan Waveforms and Timing Specifications

TMS

TDI

TCK

TDO

Data to be

captured

Data to be

driven out

btch

btsu

btcl

btvo

btcsu

Data Captured

btuov

bth

btcp

btco

Valid Data Valid Data

btch

btuco

Valid Data Valid Data

btoz

btuoz

Symbol Parameter Min Max Units

btcp

btch

btcl

btsu

bth

btco

btoz

btvo

btcpsu

btcph

btuco

btuoz

btuov

TCK [BSCAN test] clock pulse width 100 – ns TCK [BSCAN test] pulse width high 50 – ns TCK [BSCAN test] pulse width low 50 – ns TCK [BSCAN test] setup time 20 – ns TCK [BSCAN test] hold time 25 – ns TCK [BSCAN test] rise and fall time 50 – mV/ns TAP controller falling edge of clock to valid output – 25 ns TAP controller falling edge of clock to data output disable – 25 ns TAP controller falling edge of clock to data output enable – 25 ns BSCAN test Capture register setup time 20 – ns BSCAN test Capture register hold time 25 – ns BSCAN test Update reg, falling edge of clock to valid output – 50 ns BSCAN test Update reg, falling edge of clock to output disable – 50 ns BSCAN test Update reg, falling edge of clock to output enable – 50 ns

Specifications ispGDX160V/VA

Signal Descriptions

Signal Name Description

I/O Input/Output Pins – These are the general purpose bidirectional data pins. When used as outputs,

each may be independently latched, registered or tristated. They can also each assume one other

control function (OE, CLK/CLKEN, and MUXsel as described in the text). TOE Test Output Enable Pin – This pin tristates all I/P pins when a logic low is driven. RESET Active LOW Input Pin – Resets all I/O register outputs when LOW. Yx/CLKENx Input Pins –These can be either Global Clocks or Clock Enables. EPEN Input Pin – JTAG TAP Controller Enable Pin. When high, JTAG operation is enabled. When low,

JTAG TAP controller is driven to reset. TDI Input Pin – Serial data input during ISP programming or Boundary Scan mode. TCK Input Pin – Serial data clock during ISP programming or Boundary Scan mode. TMS Input Pin – Control input during ISP programming or Boundary Scan mode. TDO Output Pin – Serial data output during ISP programming or Boundary Scan mode. GND Ground (GND) VCC Vcc – Supply voltage (3.3V).

VCCIO

1. NC pins are not to be connected to any active signals, VCC or GND.

2. “VA” version only.

Input – This pin is used if optional 2.5V output is to be used. Every I/O can independently select either

3.3V or the optional voltage as its output level. If the optional output voltage is not required, this pin

must be connected to the VCC supply. Programmable pull-up resistors and bus-hold latches only draw

current from this supply.

No Connect.

Specifications ispGDX160V/VA

Signal Locations: ispGDX160V/VA

Signal 208-Pin PQFP 208-Ball fpBGA 272-Ball BGA

TOE 178 D9 A12 RESET 185 A8 D10 Y0/CLKEN0 75 N8 V10 Y1/CLKEN1 76 R8 Y10 Y2/CLKEN2 180 B9 C11 Y3/CLKEN3 181 C9 A11 EPEN 183 A9 B10 TDI 81 P9 Y12 TCK 80 T9 U11 TMS 79 T8 V11 TDO 78 P8 W11 GND 6, 15, 25, 35, 44, 54, 63, D4, D13, G7, G8, G9, A1, D4, D8, D13, D17, H4, H17, J9, J10, J11, J12,

77, 91, 100, 110, 119, 129, G10, H7, H8, H9, H10, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10, 139, 148, 159, 168, 182, J7, J8, J9, J10, K7, K8, M11, M12, N4, N17, U4, U8, U13, U17 195, 204 K9, K10, N4, N13

VCC 1, 17, 33, 49, 65, 89, 105, E13

121, 137, 153, 1561, 170, M4, M13, N5, N11, N12 U10, U15 184, 193 D5, D6, D12, E4

VCCIO 156

NC 73, 74, 179 A10, P7, T7 A2, A6, A7, A10, A15, A19, A20, B1, B2, B4, B11,

1. VCC on ispGDX160V, VCCIO on ispGDX160VA.

, F4, F13, L4, L13, C181, D6, D11, D15, F4, F17, K4, L17, R4, R17, U6,

E13

C18

B14, B18, B19, B20, C2, C3, C10, D2, D3, D16, E2, E17, E19, H1, H3, H18, H20, K20, L1, N1, N3, N18 N20, T2, T4, T19, U5, U18, U19, V3, V14, V18, V19, W1, W2, W3, W7, W10, W14, W19, W20, Y1, Y2, Y6, Y9, Y11, Y18, Y20

Specifications ispGDX160V/VA

I/O Locations: ispGDX160V/VA (Ordered by I/O Signal Name and 208-Pin PQFP Location)

I/O Control 208 208 272

Signal Signal PQFP fpBGA BGA

VCC I/O A0 CLK/CLKEN 2 B2 E4 I/O A1 OE 3 B1 C1 I/O A2 MUXsel1 4 C2 D1 I/O A3 MUXsel2 5 A1 E3 GND I/O A4 CLK/CLKEN 7 C1 E1 I/O A5 OE 8 D3 F3 I/O A6 MUXsel1 9 D2 G4 I/O A7 MUXsel2 10 D1 F2 I/O A8 CLK/CLKEN 11 E3 F1 I/O A9 OE 12 E2 G3 I/O A10 MUXsel1 13 E1 G2 I/O A11 MUXsel2 14 F3 G1 GND I/O A12 CLK/CLKEN 16 F2 H2 VCC I/O A13 OE 18 F1 J4 I/O A14 MUXsel1 19 G4 J3 I/O A15 MUXsel2 20 G2 J2 I/O A16 CLK/CLKEN 21 G3 J1 I/O A17 OE 22 G1 K2 I/O A18 MUXsel1 23 H4 K3 I/O A19 MUXsel2 24 H2 K1 GND I/O A20 CLK/CLKEN 26 H3 L2 I/O A21 OE 27 H1 L3 I/O A22 MUXsel1 28 J1 L4 I/O A23 MUXsel2 29 J3 M1 I/O A24 CLK/CLKEN 30 J2 M2 I/O A25 OE 31 J4 M3 I/O A26 MUXsel1 32 K1 M4 VCC I/O A27 MUXsel2 34 K3 N2 GND I/O A28 CLK/CLKEN 36 K2 P1 I/O A29 OE 37 K4 P2 I/O A30 MUXsel1 38 L1 R1 I/O A31 MUXsel2 39 L2 P3 I/O A32 CLK/CLKEN 40 L3 R2 I/O A33 OE 41 M1 T1 I/O A34 MUXsel1 42 M2 P4 I/O A35 MUXsel2 43 M3 R3 GND I/O A36 CLK/CLKEN 45 N1 U1 I/O A37 OE 46 N2 T3 I/O A38 MUXsel1 47 N3 U2 I/O A39 MUXsel2 48 P1 V1 VCC I/O B0 CLK/CLKEN 50 P2 U3 I/O B1 OE 51 R1 V2 I/O B2 MUXsel1 52 R2 W4 I/O B3 MUXsel2 53 T1 V4 GND I/O B4 CLK/CLKEN 55 P3 Y3 I/O B5 OE 56 T2 Y4 I/O B6 MUXsel1 57 R3 V5 I/O B7 MUXsel2 58 P4 W5 I/O B8 CLK/CLKEN 59 T3 Y5 I/O B9 OE 60 R4 V6 I/O B10 MUXsel1 61 T4 U7 I/O B11 MUXsel2 62 P5 W6 GND I/O B12 CLK/CLKEN 64 R5 V7 VCC

I/O Control 208 208 272

Signal Signal PQFP fpBGA BGA

I/O B13 OE 66 N6 Y7 I/O B14 MUXsel1 67 T5 V8 I/O B15 MUXsel2 68 R6 W8 I/O B16 CLK/CLKEN 69 P6 Y8 I/O B17 OE 70 T6 U9 I/O B18 MUXsel1 71 N7 V9 I/O B19 MUXsel2 72 R7 W9 GND I/O B20 CLK/CLKEN 82 R9 W12 I/O B21 OE 83 N9 V12 I/O B22 MUXsel1 84 T10 U12 I/O B23 MUXsel2 85 P10 Y13 I/O B24 CLK/CLKEN 86 R10 W13 I/O B25 OE 87 N10 V13 I/O B26 MUXsel1 88 T11 Y14 VCC I/O B27 MUXsel2 90 P11 Y15 GND I/O B28 CLK/CLKEN 92 R11 W15 I/O B29 OE 93 T12 Y16 I/O B30 MUXsel1 94 P12 U14 I/O B31 MUXsel2 95 R12 V15 I/O B32 CLK/CLKEN 96 T13 W16 I/O B33 OE 97 R13 Y17 I/O B34 MUXsel1 98 T14 V16 I/O B35 MUXsel2 99 P13 W17 GND I/O B36 CLK/CLKEN 101 R14 U16 I/O B37 OE 102 T15 V17 I/O B38 MUXsel1 103 T16 W18 I/O B39 MUXsel2 104 R15 Y19 VCC I/O C0 CLK/CLKEN 106 P14 T17 I/O C1 OE 107 P15 V20 I/O C2 MUXsel1 108 R16 U20 I/O C3 MUXsel2 109 N14 T18 GND I/O C4 CLK/CLKEN 111 P16 T20 I/O C5 OE 112 N15 R18 I/O C6 MUXsel1 113 N16 P17 I/O C7 MUXsel2 114 M14 R19 I/O C8 CLK 115 M15 R20 I/O C9 OE 116 M16 P18 I/O C10 MUXsel1 117 L15 P19 I/O C11 MUXsel2 118 L14 P20 GND I/O C12 CLK/CLKEN 120 L16 N19 VCC I/O C13 OE 122 K13 M17 I/O C14 MUXsel1 123 K15 M18 I/O C15 MUXsel2 124 K14 M19 I/O C16 CLK/CLKEN 125 K16 M20 I/O C17 OE 126 J13 L19 I/O C18 MUXsel1 127 J15 L18 I/O C19 MUXsel2 128 J14 L20 GND I/O C20 CLK/CLKEN 130 J16 K19 I/O C21 OE 131 H14 K18 I/O C22 MUXsel1 132 H16 K17 I/O C23 MUXsel2 133 H15 J20 I/O C24 CLK/CLKEN 134 H13 J19 I/O C25 OE 135 G16 J18 I/O C26 MUXsel1 136 G14 J17 VCC I/O C27 MUXsel2 138 G15 H19

NOTE: VCC and GND Pads Shown for Reference, 1VCC in ispGDX160V

I/O Control 208 208 272

Signal Signal PQFP fpBGA BGA

GND I/O C28 CLK/CLKEN 140 G13 G20 I/O C29 OE 141 F16 G19 I/O C30 MUXsel1 142 F14 F20 I/O C31 MUXsel2 143 F15 G18 I/O C32 CLK/CLKEN 144 E16 F19 I/O C33 OE 145 E14 E20 I/O C34 MUXsel1 146 E15 G17 I/O C35 MUXsel2 147 D16 F18 GND I/O C36 CLK/CLKEN 149 C16 D20 I/O C37 OE 150 D15 E18 I/O C38 MUXsel1 151 D14 D19 I/O C39 MUXsel2 152 C15 C20 VCC I/O D0 CLK/CLKEN 154 B16 D18 I/O D1 OE 155 A16 C19 VCC/VCCIO I/O D2 MUXsel1 157 B15 B17 I/O D3 MUXsel2 158 A15 C17 GND I/O D4 CLK/CLKEN 160 C14 A18 I/O D5 OE 161 B14 A17 I/O D6 MUXsel1 162 A14 C16 I/O D7 MUXsel2 163 C13 B16 I/O D8 CLK/CLKEN 164 B13 A16 I/O D9 OE 165 A13 C15 I/O D10 MUXsel1 166 C12 D14 I/O D11 MUXsel2 167 B12 B15 GND I/O D12 CLK/CLKEN 169 D11 C14 VCC I/O D13 OE 171 A12 A14 I/O D14 MUXsel1 172 C11 C13 I/O D15 MUXsel2 173 B11 B13 I/O D16 CLK/CLKEN 174 D10 A13 I/O D17 OE 175 A11 D12 I/O D18 MUXsel1 176 B10 C12 I/O D19 MUXsel2 177 C10 B12 GND VCC I/O D20 CLK/CLKEN 186 C8 A9 I/O D21 OE 187 B8 B9 I/O D22 MUXsel1 188 D8 C9 I/O D23 MUXsel2 189 A7 D9 I/O D24 CLK/CLKEN 190 C7 A8 I/O D25 OE 191 B7 B8 I/O D26 MUXsel1 192 D7 C8 VCC I/O D27 MUXsel2 194 A6 B7 GND I/O D28 CLK/CLKEN 196 C6 C7 I/O D29 OE 197 B6 B6 I/O D30 MUXsel1 198 A5 A5 I/O D31 MUXsel2 199 C5 D7 I/O D32 CLK/CLKEN 200 B5 C6 I/O D33 OE 201 A4 B5 I/O D34 MUXsel1 202 B4 A4 I/O D35 MUXsel2 203 C4 C5 GND I/O D36 CLK/CLKEN 205 A3 A3 I/O D37 OE 206 C3 D5 I/O D38 MUXsel1 207 B3 C4 I/O D39 MUXsel2 208 A2 B3

Specifications ispGDX160V/VA

I/O Locations: ispGDX160V/VA (Ordered by 208-Ball BGA Location)

I/O Control 208 208 272

Signal Signal PQFP fpBGA BGA

I/O A3 MUXsel2 5 A1 E3 I/O D39 MUXsel2 208 A2 B3 I/O D36 CLK/CLKEN 205 A3 A3 I/O D33 OE 201 A4 B5 I/O D30 MUXsel1 198 A5 A5 I/O D27 MUXsel2 194 A6 B7 I/O D23 MUXsel2 189 A7 D9 I/O D17 OE 175 A11 D12 I/O D13 OE 171 A12 A14 I/O D9 OE 165 A13 C15 I/O D6 MUXsel1 162 A14 C16 I/O D3 MUXsel2 158 A15 C17 I/O D1 OE 155 A16 C19 I/O A1 OE 3 B1 C1 I/O A0 CLK/CLKEN 2 B2 E4 I/O D38 MUXsel1 207 B3 C4 I/O D34 MUXsel1 202 B4 A4 I/O D32 CLK/CLKEN 200 B5 C6 I/O D29 OE 197 B6 B6 I/O D25 OE 191 B7 B8 I/O D21 OE 187 B8 B9 I/O D18 MUXsel1 176 B10 C12 I/O D15 MUXsel2 173 B11 B13 I/O D11 MUXsel2 167 B12 B15 I/O D8 CLK/CLKEN 164 B13 A16 I/O D5 OE 161 B14 A17 I/O D2 MUXsel1 157 B15 B17 I/O D0 CLK/CLKEN 154 B16 D18 I/O A4 CLK/CLKEN 7 C1 E1 I/O A2 MUXsel1 4 C2 D1 I/O D37 OE 206 C3 D5 I/O D35 MUXsel2 203 C4 C5 I/O D31 MUXsel2 199 C5 D7 I/O D28 CLK/CLKEN 196 C6 C7 I/O D24 CLK/CLKEN 190 C7 A8 I/O D20 CLK/CLKEN 186 C8 A9 I/O D19 MUXsel2 177 C10 B12 I/O D14 MUXsel1 172 C11 C13 I/O D10 MUXsel1 166 C12 D14 I/O D7 MUXsel2 163 C13 B16 I/O D4 CLK/CLKEN 160 C14 A18 I/O C39 MUXsel2 152 C15 C20 I/O C36 CLK/CLKEN 149 C16 D20 I/O A7 MUXsel2 10 D1 F2 I/O A6 MUXsel1 9 D2 G4 I/O A5 OE 8 D3 F3 I/O D26 MUXsel1 192 D7 C8 I/O D22 MUXsel1 188 D8 C9 I/O D16 CLK/CLKEN 174 D10 A13 I/O D12 CLK/CLKEN 169 D11 C14 I/O C38 MUXsel1 151 D14 D19 I/O C37 OE 150 D15 E18 I/O C35 MUXsel2 147 D16 F18 I/O A10 MUXsel1 13 E1 G2

I/O Control 208 208 272

Signal Signal PQFP fpBGA BGA

I/O A9 OE 12 E2 G3 I/O A8 CLK/CLK_EN 11 E3 F1 I/O C33 OE 145 E14 E20 I/O C34 MUXsel1 146 E15 G17 I/O C32 CLK/CLKEN 144 E16 F19 I/O A13 OE 18 F1 J4 I/O A12 CLK/CLKEN 16 F2 H2 I/O A11 MUXsel2 14 F3 G1 I/O C30 MUXsel1 142 F14 F20 I/O C31 MUXsel2 143 F15 G18 I/O C29 OE 141 F16 G19 I/O A17 OE 22 G1 K2 I/O A15 MUXsel2 20 G2 J2 I/O A16 CLK/CLKEN 21 G3 J1 I/O A14 MUXsel1 19 G4 J3 I/O C28 CLK/CLKEN 140 G13 G20 I/O C26 MUXsel1 136 G14 J17 I/O C27 MUXsel2 138 G15 H19 I/O C25 OE 135 G16 J18 I/O A21 OE 27 H1 L3 I/O A19 MUXsel2 24 H2 K1 I/O A20 CLK/CLKEN 26 H3 L2 I/O A18 MUXsel1 23 H4 K3 I/O C24 CLK/CLKEN 134 H13 J19 I/O C21 OE 131 H14 K18 I/O C23 MUXsel2 133 H15 J20 I/O C22 MUXsel1 132 H16 K17 I/O A22 MUXsel1 28 J1 L4 I/O A24 CLK/CLKEN 30 J2 M2 I/O A23 MUXsel2 29 J3 M1 I/O A25 OE 31 J4 M3 I/O C17 OE 126 J13 L19 I/O C19 MUXsel2 128 J14 L20 I/O C18 MUXsel1 127 J15 L18 I/O C20 CLK/CLKEN 130 J16 K19 I/O A26 MUXsel1 32 K1 M4 I/O A28 CLK/CLKEN 36 K2 P1 I/O A27 MUXsel2 34 K3 N2 I/O A29 OE 37 K4 P2 I/O C13 OE 122 K13 M17 I/O C15 MUXsel2 124 K14 M19 I/O C14 MUXsel1 123 K15 M18 I/O C16 CLK/CLKEN 125 K16 M20 I/O A30 MUXsel1 38 L1 R1 I/O A31 MUXsel2 39 L2 P3 I/O A32 CLK/CLKEN 40 L3 R2 I/O C11 MUXsel2 118 L14 P20 I/O C10 MUXsel1 117 L15 P19 I/O C12 CLK/CLKEN 120 L16 N19 I/O A33 OE 41 M1 T1 I/O A34 MUXsel1 42 M2 P4 I/O A35 MUXsel2 43 M3 R3 I/O C7 MUXsel2 114 M14 R19

I/O Control 208 208 272

Signal Signal PQFP fpBGA BGA

I/O C8 CLK 115 M15 R20 I/O C9 OE 116 M16 P18 I/O A36 CLK/CLKEN 45 N1 U1 I/O A37 OE 46 N2 T3 I/O A38 MUXsel1 47 N3 U2 I/O B13 OE 66 N6 Y7 I/O B18 MUXsel1 71 N7 V9 I/O B21 OE 83 N9 V12 I/O B25 OE 87 N10 V13 I/O C3 MUXsel2 109 N14 T18 I/O C5 OE 112 N15 R18 I/O C6 MUXsel1 113 N16 P17 I/O A39 MUXsel2 48 P1 V1 I/O B0 CLK/CLKEN 50 P2 U3 I/O B4 CLK/CLKEN 55 P3 Y3 I/O B7 MUXsel2 58 P4 W5 I/O B11 MUXsel2 62 P5 W6 I/O B16 CLK/CLKEN 69 P6 Y8 I/O B23 MUXsel2 85 P10 Y13 I/O B27 MUXsel2 90 P11 Y15 I/O B30 MUXsel1 94 P12 U14 I/O B35 MUXsel2 99 P13 W17 I/O C0 CLK/CLKEN 106 P14 T17 I/O C1 OE 107 P15 V20 I/O C4 CLK/CLKEN 111 P16 T20 I/O B1 OE 51 R1 V2 I/O B2 MUXsel1 52 R2 W4 I/O B6 MUXsel1 57 R3 V5 I/O B9 OE 60 R4 V6 I/O B12 CLK/CLKEN 64 R5 V7 I/O B15 MUXsel2 68 R6 W8 I/O B19 MUXsel2 72 R7 W9 I/O B20 CLK/CLKEN 82 R9 W12 I/O B24 CLK/CLKEN 86 R10 W13 I/O B28 CLK/CLKEN 92 R11 W15 I/O B31 MUXsel2 95 R12 V15 I/O B33 OE 97 R13 Y17 I/O B36 CLK/CLKEN 101 R14 U16 I/O B39 MUXsel2 104 R15 Y19 I/O C2 MUXsel1 108 R16 U20 I/O B3 MUXsel2 53 T1 V4 I/O B5 OE 56 T2 Y4 I/O B8 CLK/CLKEN 59 T3 Y5 I/O B10 MUXsel1 61 T4 U7 I/O B14 MUXsel1 67 T5 V8 I/O B17 OE 70 T6 U9 I/O B22 MUXsel1 84 T10 U12 I/O B26 MUXsel1 88 T11 Y14 I/O B29 OE 93 T12 Y16 I/O B32 CLK/CLKEN 96 T13 W16 I/O B34 MUXsel1 98 T14 V16 I/O B37 OE 102 T15 V17 I/O B38 MUXsel1 103 T16 W18

Specifications ispGDX160V/VA

I/O Locations: ispGDX160V/VA (Ordered by 272-Ball BGA Location)

I/O Control 208 208 272

Signal Signal PQFP fpBGA BGA

I/O D36 CLK/CLKEN 205 A3 A3 I/O D34 MUXsel1 202 B4 A4 I/O D30 MUXsel1 198 A5 A5 I/O D24 CLK/CLKEN 190 C7 A8 I/O D20 CLK/CLKEN 186 C8 A9 I/O D16 CLK/CLKEN 174 D10 A13 I/O D13 OE 171 A12 A14 I/O D8 CLK/CLKEN 164 B13 A16 I/O D5 OE 161 B14 A17 I/O D4 CLK/CLKEN 160 C14 A18 I/O D39 MUXsel2 208 A2 B3 I/O D33 OE 201 A4 B5 I/O D29 OE 197 B6 B6 I/O D27 MUXsel2 194 A6 B7 I/O D25 OE 191 B7 B8 I/O D21 OE 187 B8 B9 I/O D19 MUXsel2 177 C10 B12 I/O D15 MUXsel2 173 B11 B13 I/O D11 MUXsel2 167 B12 B15 I/O D7 MUXsel2 163 C13 B16 I/O D2 MUXsel1 157 B15 B17 I/O A1 OE 3 B1 C1 I/O D38 MUXsel1 207 B3 C4 I/O D35 MUXsel2 203 C4 C5 I/O D32 CLK/CLKEN 200 B5 C6 I/O D28 CLK/CLKEN 196 C6 C7 I/O D26 MUXsel1 192 D7 C8 I/O D22 MUXsel1 188 D8 C9 I/O D18 MUXsel1 176 B10 C12 I/O D14 MUXsel1 172 C11 C13 I/O D12 CLK/CLKEN 169 D11 C14 I/O D9 OE 165 A13 C15 I/O D6 MUXsel1 162 A14 C16 I/O D3 MUXsel2 158 A15 C17 I/O D1 OE 155 A16 C19 I/O C39 MUXsel2 152 C15 C20 I/O A2 MUXsel1 4 C2 D1 I/O D37 OE 206 C3 D5 I/O D31 MUXsel2 199 C5 D7 I/O D23 MUXsel2 189 A7 D9 I/O D17 OE 175 A11 D12 I/O D10 MUXsel1 166 C12 D14 I/O D0 CLK/CLKEN 154 B16 D18 I/O C38 MUXsel1 151 D14 D19 I/O C36 CLK/CLKEN 149 C16 D20 I/O A4 CLK/CLK_EN 7 C1 E1 I/O A3 MUXsel2 5 A1 E3 I/O A0 CLK/CLKEN 2 B2 E4 I/O C37 OE 150 D15 E18 I/O C33 OE 145 E14 E20 I/O A8 CLK/CLKEN 11 E3 F1 I/O A7 MUXsel2 10 D1 F2 I/O A5 OE 8 D3 F3 I/O C35 MUXsel2 147 D16 F18

I/O Control 208 208 272

Signal Signal PQFP fpBGA BGA

I/O C32 CLK/CLKEN 144 E16 F19 I/O C30 MUXsel1 142 F14 F20 I/O A11 MUXsel2 14 F3 G1 I/O A10 MUXsel1 13 E1 G2 I/O A9 OE 12 E2 G3 I/O A6 MUXsel1 9 D2 G4 I/O C34 MUXsel1 146 E15 G17 I/O C31 MUXsel2 143 F15 G18 I/O C29 OE 141 F16 G19 I/O C28 CLK/CLKEN 140 G13 G20 I/O A12 CLK/CLKEN 16 F2 H2 I/O C27 MUXsel2 138 G15 H19 I/O A16 CLK/CLKEN 21 G3 J1 I/O A15 MUXsel2 20 G2 J2 I/O A14 MUXsel1 19 G4 J3 I/O A13 OE 18 F1 J4 I/O C26 MUXsel1 136 G14 J17 I/O C25 OE 135 G16 J18 I/O C24 CLK/CLKEN 134 H13 J19 I/O C23 MUXsel2 133 H15 J20 I/O A19 MUXsel2 24 H2 K1 I/O A17 OE 22 G1 K2 I/O A18 MUXsel1 23 H4 K3 I/O C22 MUXsel1 132 H16 K17 I/O C21 OE 131 H14 K18 I/O C20 CLK/CLKEN 130 J16 K19 I/O A20 CLK/CLKEN 26 H3 L2 I/O A21 OE 27 H1 L3 I/O A22 MUXsel1 28 J1 L4 I/O C18 MUXsel1 127 J15 L18 I/O C17 OE 126 J13 L19 I/O C19 MUXsel2 128 J14 L20 I/O A23 MUXsel2 29 J3 M1 I/O A24 CLK/CLKEN 30 J2 M2 I/O A25 OE 31 J4 M3 I/O A26 MUXsel1 32 K1 M4 I/O C13 OE 122 K13 M17 I/O C14 MUXsel1 123 K15 M18 I/O C15 MUXsel2 124 K14 M19 I/O C16 CLK/CLKEN 125 K16 M20 I/O A27 MUXsel2 34 K3 N2 I/O C12 CLK/CLKEN 120 L16 N19 I/O A28 CLK/CLKEN 36 K2 P1 I/O A29 OE 37 K4 P2 I/O A31 MUXsel2 39 L2 P3 I/O A34 MUXsel1 42 M2 P4 I/O C6 MUXsel1 113 N16 P17 I/O C9 OE 116 M16 P18 I/O C10 MUXsel1 117 L15 P19 I/O C11 MUXsel2 118 L14 P20 I/O A30 MUXsel1 38 L1 R1 I/O A32 CLK/CLKEN 40 L3 R2 I/O A35 MUXsel2 43 M3 R3

I/O Control 208 208 272

Signal Signal PQFP fpBGA BGA

I/O C5 OE 112 N15 R18 I/O C7 MUXsel2 114 M14 R19 I/O C8 CLK 115 M15 R20 I/O A33 OE 41 M1 T1 I/O A37 OE 46 N2 T3 I/O C0 CLK/CLKEN 106 P14 T17 I/O C3 MUXsel2 109 N14 T18 I/O C4 CLK/CLKEN 111 P16 T20 I/O A36 CLK/CLKEN 45 N1 U1 I/O A38 MUXsel1 47 N3 U2 I/O B0 CLK/CLKEN 50 P2 U3 I/O B10 MUXsel1 61 T4 U7 I/O B17 OE 70 T6 U9 I/O B22 MUXsel1 84 T10 U12 I/O B30 MUXsel1 94 P12 U14 I/O B36 CLK/CLKEN 101 R14 U16 I/O C2 MUXsel1 108 R16 U20 I/O A39 MUXsel2 48 P1 V1 I/O B1 OE 51 R1 V2 I/O B3 MUXsel2 53 T1 V4 I/O B6 MUXsel1 57 R3 V5 I/O B9 OE 60 R4 V6 I/O B12 CLK/CLKEN 64 R5 V7 I/O B14 MUXsel1 67 T5 V8 I/O B18 MUXsel1 71 N7 V9 I/O B21 OE 83 N9 V12 I/O B25 OE 87 N10 V13 I/O B31 MUXsel2 95 R12 V15 I/O B34 MUXsel1 98 T14 V16 I/O B37 OE 102 T15 V17 I/O C1 OE 107 P15 V20 I/O B2 MUXsel1 52 R2 W4 I/O B7 MUXsel2 58 P4 W5 I/O B11 MUXsel2 62 P5 W6 I/O B15 MUXsel2 68 R6 W8 I/O B19 MUXsel2 72 R7 W9 I/O B20 CLK/CLKEN 82 R9 W12 I/O B24 CLK/CLKEN 86 R10 W13 I/O B28 CLK/CLKEN 92 R11 W15 I/O B32 CLK/CLKEN 96 T13 W16 I/O B35 MUXsel2 99 P13 W17 I/O B38 MUXsel1 103 T16 W18 I/O B4 CLK/CLKEN 55 P3 Y3 I/O B5 OE 56 T2 Y4 I/O B8 CLK/CLKEN 59 T3 Y5 I/O B13 OE 66 N6 Y7 I/O B16 CLK/CLKEN 69 P6 Y8 I/O B23 MUXsel2 85 P10 Y13 I/O B26 MUXsel1 88 T11 Y14 I/O B27 MUXsel2 90 P11 Y15 I/O B29 OE 93 T12 Y16 I/O B33 OE 97 R13 Y17 I/O B39 MUXsel2 104 R15 Y19

Signal Configuration: ispGDX160V/VA

ispGDX160V/VA 272-Ball BGA Signal Diagram

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Specifications ispGDX160V/VA

A B C D E F

H J K L

N P R T U V

I/O D4I/O D5I/O

NC1NC

NC1NC1NC

I/O

C39

I/O

C36

I/O

C33

I/O

C30

I/O

C28 NC

I/O

C23 NC

I/O

C19

I/O

C16 NC

I/O

C11

I/O C8I/O C7I/O

I/O C4

I/O C2

I/O C1

NC1NC

VCCIO

VCC

I/O

C38

D0 I/O

C37

I/O

C32

C35

I/O

C29

C31

I/O

C27

I/O

C24

I/O

C20

I/O

C17

I/O

C15

I/O

C12

I/O

C10

I/O

C25

I/O

C21

I/O

C18

I/O

C14 NC

I/O C9I/O

C5 I/O C3I/O

NC1GND

I/O

B38

I/O

B39

I/O D2I/O D7I/O

I/O D3I/O D6I/O D9I/O

GND NC

D11

VCC

I/O

D13 NC

D12

I/O

D10

I/O

D16

I/O

D15

I/O

D14

GND

TOE

I/O

D19

I/O

D18

I/O

D17

Y3/

CLKEN3

Y2/

CLKEN2

VCC

EPEN

RESET

I/O

D20

I/O

D21

I/O

D22

I/O

D23

I/O

D24

I/O

D25

I/O

D26

GND

I/O

D27

I/O

D28

I/O

D31

I/O

D29

I/O

D32 VCC

I/O

D30

I/O

D33

I/O

D35

I/O

D37

I/O

D34 NC

I/O

D38

GND NC

I/O A0I/O

VCC VCC

ispGDX160V/VA

I/O

C34

GND GND NC

I/O

C26

I/O

C22

Bottom View

GND GND GND GND

GND GND GND GND VCC

VCC GND GND GND GND

I/O

C13

GND GND NC

GND GND GND GND

VCC VCC

VCC

I/O

B31

I/O

B28

I/O

B27

I/O B30

I/O B26

I/O

B36

I/O B37

I/O B35

I/O B33

I/O

B34

I/O

B32

I/O

B29

GND

I/O

B25

I/O

B24

I/O

B23

I/O

B22

I/O

B21

I/O

B20

TDI

TCK

TMS

TDO

CLKEN0

CLKEN1

VCC

Y0/

Y1/

GND

I/O

B14

I/O

B15

I/O

B16

I/O

VCC NC

B10

I/O

I/O B9I/O B6I/O

B12

I/O

B11

I/O

B13

I/O

B17

I/O

B18

I/O

B19

I/O A6I/O A9I/O

I/O

A13

I/O

A22

I/O

A26

I/O

A34

GND

I/O B7I/O

I/O B8I/O B5I/O

I/O

D36

I/O

D39 NC

I/O A5I/O A7I/O

A10

I/O

A12

I/O

A14

A15

I/O

A18

A17

I/O

A21

A20

I/O

A25

A24

I/O

A27

I/O

A31

A29

I/O

A35

A32

I/O

A37

I/O B0I/O

A38

I/O B1I/O

NC1NC

GND

I/O

A11

I/O

A16

I/O

A19

I/O

A23

I/O

A28

I/O

A30

I/O

A33

I/O

A36

A39

B C D E F

H J K

N P R T U V

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

1. NCs are not to be connected to any active signals, Vcc or GND.

2. VCCIO on ispGDX160VA. VCC on ispGDX160V.

Specifications ispGDX160V/VA

Signal Configuration: ispGDX160V/VA

ispGDX160V/VA 208-Ball fpBGA Signal Diagram

16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

I/O D1I/O D3I/O D6I/O D9I/O

I/O D0I/O D2I/O D5I/O D8I/O

I/O

C36

C39

I/O

C35

C37

I/O

C32

C34

I/O

C29

C31

I/O

C25

C27

I/O

C22

C23

I/O

C20

C18

I/O

C16

C14

I/O

C12

C10

I/O C9I/O C8I/O

I/O C6I/O C5I/O

I/O C4I/O C1I/O C0I/O

I/O C2I/O

I/O

B38

B39

B37

I/O D4I/O D7I/O

I/O

C38

I/O

C33

I/O

C30

I/O

C26

I/O

C21

I/O

C19

I/O

C15

I/O

C11

I/O

B36

I/O

B34

I/O

D13

D17

I/O

D11

D15

I/O

D10

D14

GND VCC

VCCIO/

VCC

I/O

D12

VCC VCC

I/O

C28

I/O

C24

I/O

C17

I/O

C13

EPEN RESET

Y2/

I/O

CLKEN2

D18

I/O

D19

I/O

D16

CLKEN3

Y3/

TOE

D21

D20

D22

ispGDX160V/VA

Bottom View

GND GND GND GND

I/O

D23

D27

I/O

D25

D29

I/O

D24

D28

I/O

VCC VCC GND

D26

I/O

D30

I/O

D32

I/O

D31

D33

D34

D35

VCC

A14

A18

A25

A29

VCC VCC

I/O

GND VCC VCC

I/O

B35

B30

B27

I/O

B33

B31

B28

I/O

B32

B29

B26

B25

I/O

B23

I/O

B24

I/O

B22

I/O

CLKEN0

B21

TDI TDO

I/O

CLKEN1

B20

TCK TMS

Y0/

Y1/

I/O

B18

I/O

B19

I/O

VCC GND

B13

I/O

B11

I/O

B12

I/O

B14

B10

B16

B15

B17

I/O

D36

I/O

D39

I/O

D38

I/O

D37

I/O A0I/O

I/O A2I/O

I/O A5I/O A6I/O

I/O A8I/O A9I/O

A10

I/O

A11

A12

A13

I/O

A16

A15

A17

I/O

A20

A19

A21

I/O

A23

A24

A22

I/O

A27

A28

A26

I/O

A32

A31

A30

I/O

A35

A34

A33

I/O

A38

A37

A36

I/O B7I/O B4I/O B0I/O

A39

I/O B9I/O B6I/O B2I/O

I/O

I/O B8I/O B5I/O

16 15 14 13 12 11

987654321

1. NCs are not to be connected to any active signals, Vcc or GND.

2. VCCIO on ispGDX160VA. VCC on ispGDX160V.

Pin Configuration: ispGDX160V/VA

ispGDX160V/VA 208-Pin PQFP Pinout Diagram

Specifications ispGDX160V/VA

Control

—

CLK/CLKEN

OE MUXsel1 MUXsel2

—

CLK/CLKEN

OE MUXsel1 MUXsel2

CLK/CLKEN

OE MUXsel1 MUXsel2

—

CLK/CLKEN

—

OE MUXsel1 MUXsel2

CLK/CLKEN

OE MUXsel1 MUXsel2

—

CLK/CLKEN

OE MUXsel1 MUXsel2

CLK/CLKEN

OE MUXsel1

—

MUXsel2

—

CLK/CLKEN

OE MUXsel1 MUXsel2

CLK/CLKEN

OE MUXsel1 MUXsel2

—

CLK/CLKEN

OE MUXsel1 MUXsel2

—

CLK/CLKEN

OE MUXsel1

Data

VCC I/O A 0 I/O A 1 I/O A 2 I/O A 3

GND I/O A 4 I/O A 5 I/O A 6 I/O A 7 I/O A 8 I/O A 9

I/O A 10 I/O A 11

GND

I/O A 12

VCC I/O A 13 I/O A 14 I/O A 15 I/O A 16 I/O A 17 I/O A 18 I/O A 19

GND I/O A 20 I/O A 21 I/O A 22 I/O A 23 I/O A 24 I/O A 25 I/O A 26

VCC

I/O A 27

GND I/O A 28 I/O A 29 I/O A 30 I/O A 31 I/O A 32 I/O A 33 I/O A 34 I/O A 35

GND I/O A 36 I/O A 37 I/O A 38 I/O A 39

VCC I/O B 0 I/O B 1 I/O B 2

—

MUXsel2

MUXsel1

Control

Data

I/O D 39

I/O D 38

I/O D 37

208

207

206 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

5354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899

MUXsel2

MUXsel1

CLK/CLKEN

I/O D 36

GND

I/O D 35

I/O D 34

205

204

203

202

CLK/CLKEN

I/O D 33

I/O D 32

201

200

MUXsel2

MUXsel1

I/O D 31

I/O D 30

199

198

—

CLK/CLKEN

I/O D 29

I/O D 28

GND

197

196

195

MUXsel2—MUXsel1

I/O D 27

VCC

I/O D 26

I/O D 25

194

193

192

191

MUXsel2

MUXsel1

CLK/CLKEN

I/O D 24

I/O D 23

I/O D 22

I/O D 21

190

189

188

187

———————

CLK/CLKEN

I/O D 20

RESET

VCC

EPEN

186

185

184

183

GND

Y3/CLK_EN3

Y2/CLK_EN2

182

181

180

—

NC1TOE

179

178

ispGDX160V/VA

Top View

MUXsel2

MUXsel1

I/O D 19

I/O D 18

177

176

I/O D 17

175

MUXsel2

MUXsel1

CLK/CLKEN

I/O D 16

I/O D 15

I/O D 14

I/O D 13

174

173

172

171

—

CLK/CLKEN

VCC

I/O D 12

GND

170

169

168

MUXsel2

MUXsel1

I/O D 11

I/O D 10

I/O D 9

167

166

165

MUXsel2

MUXsel1

CLK/CLKEN

I/O D 8

I/O D 7

I/O D 6

I/O D 5

164

163

162

161

100

—

MUXsel2

MUXsel1

CLK/CLKEN

I/O D 4

GND

I/O D 3

I/O D 2

160

159

158

157

101

102

103

104

156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105

Data

VCCIO/VCC I/O D1 I/O D 0 VCC I/O C 39 I/O C 38 I/O C 37 I/O C 36 GND I/O C 35 I/O C 34 I/O C 33 I/O C 32 I/O C 31 I/O C 30 I/O C 29 I/O C 28 GND I/O C 27 VCC I/O C 26 I/O C 25 I/O C 24 I/O C 23 I/O C 22 I/O C 21 I/O C 20 GND I/O C 19 I/O C 18 I/O C 17 I/O C 16 I/O C 15 I/O C 14 I/O C 13 VCC I/O C 12 GND I/O C 11 I/O C 10 I/O C 9 I/O C 8 I/O C 7 I/O C 6 I/O C 5 I/O C 4 GND I/O C 3 I/O C 2 I/O C 1 I/O C 0 VCC

Control

—

CLK/CLKEN

—

MUXsel2 MUXsel1

CLK/CLKEN

—

MUXsel2 MUXsel1

CLK/CLKEN

MUXsel2 MUXsel1

CLK/CLKEN

—

MUXsel2

—

MUXsel1

CLK/CLKEN

MUXsel2 MUXsel1

CLK/CLKEN

—

MUXsel2 MUXsel1

CLK/CLKEN

MUXsel2 MUXsel1

—

CLK/CLKEN

—

MUXsel2 MUXsel1

CLK/CLKEN

MUXsel2 MUXsel1

CLK/CLKEN

—

MUXsel2 MUXsel1

CLK/CLKEN

—

GND

Data

I/O B 3

—

MUXsel2

Control

I/O B 4

I/O B 5

I/O B 6

I/O B 7

MUXsel1

MUXsel2

CLK/CLKEN

I/O B 8

I/O B 9

I/O B 10

I/O B 11

MUXsel1

MUXsel2

CLK/CLKEN

VCC

GND

I/O B 12

—

CLK/CLKEN

I/O B 13

I/O B 14

MUXsel1

I/O B 15

I/O B 16

I/O B 17

MUXsel2

CLK/CLKEN

1NC1

I/O B 18

I/O B 19

CLK_EN0/Y0

CLK_EN1/Y1

—————————

MUXsel1

MUXsel2

GND

TDO

TMS

TCK

TDI

I/O B 20

I/O B 21

I/O B 22

I/O B 23

MUXsel1

MUXsel2

CLK/CLKEN

VCC

I/O B 24

I/O B 25

I/O B 26

MUXsel1—MUXsel2

CLK/CLKEN

I/O B 27

1. No Connect Pins (NC) are not to be connected to any active signal, Vcc or GND.

2. VCCIO on ispGDX160VA. VCC on ispGDX160V.

GND

I/O B 28

I/O B 29

—

CLK/CLKEN

I/O B 30

I/O B 31

I/O B 32

MUXsel1

MUXsel2

CLK/CLKEN

I/O B 33

I/O B 34

MUXsel1

GND

I/O B 35

I/O B 36

—

MUXsel2

CLK/CLKEN

I/O B 37

I/O B 38

MUXsel1

I/O B 39

MUXsel2

Part Number Description

Specifications ispGDX160V/VA

ispGDX XXXXX X XXXX X

Device Family Device Number

160V 160VA

Speed

3 = 3.5ns Tpd 5 = 5ns Tpd 7 = 7ns Tpd

Grade

Blank = Commercial I = Industrial

Package

Q208 = 208-Pin PQFP B208 = 208-Ball fpBGA B272 = 272-Ball BGA

0212/ispGDXVA

9 = 9ns Tpd

Ordering Information

COMMERCIAL

FAMILY ORDERING NUMBER PACKAGEtpd (ns)

208-Pin PQFP3.5 ispGDX160VA-3Q208

208-Ball fpBGA3.5 ispGDX160VA-3B208

272-Ball BGA3.5 ispGDX160VA-3B272

ispGDXVA

ispGDXV*

ispGDX160VA-5Q208

ispGDX160VA-7B208

ispGDX160V-5Q208

ispGDX160V-7B208

INDUSTRIAL

FAMILY ORDERING NUMBER PACKAGEtpd (ns)

ispGDXVA

ispGDXV*

*Use ispGDX160VA for new designs. Note: The ispGDX160VA devices are dual-marked with both Commercial and Industrial grades. The Industrial speed grade is slower, e.g. ispGDX160VA-3B208-5I.

ispGDX160VA-5Q208I

ispGDX160VA-7B208I

ispGDX160VA-9B208I

208-Pin PQFP

208-Ball fpBGA5 ispGDX160VA-5B208

272-Ball BGA5 ispGDX160VA-5B272

208-Pin PQFP7 ispGDX160VA-7Q208

208-Ball fpBGA

272-Ball BGA7 ispGDX160VA-7B272

208-Pin PQFP

208-Ball fpBGA5 ispGDX160V-5B208

272-Ball BGA5 ispGDX160V-5B272

208-Pin PQFP7 ispGDX160V-7Q208

208-Ball fpBGA

272-Ball BGA7 ispGDX160V-7B272

Table 2-0041A/ispGDXV/A

208-Pin PQFP

208-Ball fpBGA5 ispGDX160VA-5B208I

272-Ball BGA5 ispGDX160VA-5B272I

208-Pin PQFP7 ispGDX160VA-7Q208I

208-Ball fpBGA

272-Ball BGA7 ispGDX160VA-7B272I

208-Pin PQFP9 ispGDX160VA-9Q208I

208-Ball fpBGA9

272-Ball BGA9 ispGDX160VA-9B272I

208-Pin PQFP7 ispGDX160V-7Q208I

Table 2-0041C/ispGDXV

Lattice ispGDX 160V, ispGDX 160VA User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual