Lattice ispGDX 160V, ispGDX 160VA User Manual
查询160V供应商
ispGDX
TM
160V/VA
In-System Programmable
3.3V Generic Digital Crosspoint
Functional Block DiagramFeatures
• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL
CROSSPOINT FAMILY
— Advanced Architecture Addresses Programmable
PCB Interconnect, Bus Interface Integration and
Jumper/Switch Replacement
— “Any Input to Any Output” Routing
— Fixed HIGH or LOW Output Option for Jumper/DIP
Switch Emulation
— Space-Saving PQFP and BGA Packaging
— Dedicated IEEE 1149.1-Compliant Boundary Scan
Test
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 3.3V Core Power Supply
— 3.5ns Input-to-Output/3.5ns Clock-to-Output Delay*
— 250MHz Maximum Clock Frequency*
— TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels (Individually Programmable)*
— Low-Power: 16.5mA Quiescent Icc*
— 24mA IOL Drive with Programmable Slew Rate
Control Option
— PCI Compatible Drive Capability*
— Schmitt Trigger Inputs for Noise Immunity
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
• ispGDXV™ OFFERS THE FOLLOWING ADVANTAGES
— 3.3V In-System Programmable Using Boundary Scan
Test Access Port (TAP)
— Change Interconnects in Seconds
• FLEXIBLE ARCHITECTURE
— Combinatorial/Latched/Registered Inputs or Outputs
— Individual I/O Tri-state Control with Polarity Control
— Dedicated Clock/Clock Enable Input Pins (four) or
Programmable Clocks/Clock Enables from I/O Pins
(40)
— Single Level 4:1 Dynamic Path Selection (Tpd = 3.5ns)
— Programmable Wide-MUX Cascade Feature
Supports up to 16:1 MUX
— Programmable Pull-ups, Bus Hold Latch and Open
Drain on I/O Pins
— Outputs Tri-state During Power-up (“Live Insertion”
Friendly)
• DESIGN SUPPORT THROUGH LATTICE’S ispGDX
DEVELOPMENT SOFTWARE
— MS Windows or NT / PC-Based or Sun O/S
— Easy Text-Based Design Entry
— Automatic Signal Routing
— Program up to 100 ISP Devices Concurrently
— Simulator Netlist Generation for Easy Board-Level
Simulation
* “VA” Version Only
Copyright © 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein
are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. July 2000
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
gdx160va_04
1
Boundary
Scan
Control
Description
The ispGDXV/VA architecture provides a family of fast,
flexible programmable devices to address a variety of
system-level digital signal routing and interface requirements including:
• Multi-Port Multiprocessor Interfaces
• Wide Data and Address Bus Multiplexing
(e.g. 16:1 High-Speed Bus MUX)
• Programmable Control Signal Routing
(e.g. Interrupts, DMAREQs, etc.)
• Board-Level PCB Signal Routing for Prototyping or
Programmable Bus Interfaces
The devices feature fast operation, with input-to-output
signal delays (Tpd) of 3.5ns and clock-to-output delays of
3.5ns.
The architecture of the devices consists of a series of
programmable I/O cells interconnected by a Global Routing Pool (GRP). All I/O pin inputs enter the GRP directly
or are registered or latched so they can be routed to the
required I/O outputs. I/O pin inputs are defined as four
sets (A,B,C,D) which have access to the four MUX inputs
I/O
Cells
I/O Pins A
I/O Pins D
Global Routing
Pool
(GRP)
I/O Pins B
I/O
Cells
ISP
Control
I/O Pins C
TM
Description (Continued)
Specifications ispGDX160V/VA
found in each I/O cell. Each output has individual, programmable I/O tri-state control (OE), output latch clock
(CLK), clock enable (CLKEN), and two multiplexer control (MUX0 and MUX1) inputs. Polarity for these signals
is programmable for each I/O cell. The MUX0 and MUX1
inputs control a fast 4:1 MUX, allowing dynamic selection
of up to four signal sources for a given output. A wider
16:1 MUX can be implemented with the MUX expander
feature of each I/O and a propagation delay increase of
2.0ns. OE, CLK, CLKEN, and MUX0 and MUX1 inputs
can be driven directly from selected sets of I/O pins.
Optional dedicated clock input pins give minimum clockto-output delays. CLK and CLKEN share the same set of
I/O pins. CLKEN disables the register clock when
CLKEN = 0.
Through in-system programming, connections between
I/O pins and architectural features (latched or registered
inputs or outputs, output enable control, etc.) can be
defined. In keeping with its data path application focus,
the ispGDXV devices contain no programmable logic
arrays. All input pins include Schmitt trigger buffers for
noise immunity. These connections are programmed
into the device using non-volatile E
2
CMOS technology.
Non-volatile technology means the device configuration
is saved even when the power is removed from the
device.
In addition, there are no pin-to-pin routing constraints for
any
1:1 or 1:n signal routing. That is,
I/O pin configured
as an input can drive one or more I/O pins configured as
outputs.
The device pins also have the ability to set outputs to
fixed HIGH or LOW logic levels (Jumper or DIP Switch
mode). Device outputs are specified for 24mA sink and
12mA source current (at JEDEC LVTTL levels) and can
be tied together in parallel for greater drive. On the
ispGDXVA, each I/O pin is individually programmable for
3.3V or 2.5V output levels as described later. Programmable output slew rate control can be defined
independently for each I/O pin to reduce overall ground
bounce and switching noise.
All I/O pins are equipped with IEEE1149.1-compliant
Boundary Scan Test circuitry for enhanced testability. In
addition, in-system programming is supported through
the Test Access Port via a special set of private commands.
The ispGDXV I/Os are designed to withstand “live insertion” system environments. The I/O buffers are disabled
during power-up and power-down cycles. When designing for “live insertion,” absolute maximum rating conditions
for the Vcc and I/O pins must still be met.
Table 1. ispGDXV Family Members
I/O Pins 160
I/O-OE Inputs* 40
I/O-CLK / CLKEN Inputs* 40
I/O-MUXsel1 Inputs* 40
I/O-MUXsel2 Inputs* 40
Dedicated Clock Pins** 4
EPEN 1
TOE
BSCAN Interface 4
RESET
Pin Count/Package 208-Pin PQFP
* The CLK/CLK_EN, OE, MUX0 and MUX1 terminals on each I/O cell can each be assigned to
25% of the I/Os.
** Global clock pins Y0, Y1, Y2 and Y3 are multiplexed with CLKEN0, CLKEN1, CLKEN2 and
CLKEN3 respectively in all devices.
ispGDXV/VA Device
ispGDX80VA ispGDX240VA
80
20
20
20
20
2
1
1
4
1
100-Pin TQFP
ispGDX160V/VA
1
1
208-Ball fpBGA
272-Ball BGA
240
60
60
60
60
4
1
1
4
1
388-Ball fpBGA
2
Architecture
Specifications ispGDX160V/VA
The ispGDXV/VA architecture is different from traditional
PLD architectures, in keeping with its unique application
focus. The block diagram is shown below. The program-
The various I/O pin sets are also shown in the block
diagram below. The A, B, C, and D I/O pins are grouped
together with one group per side.
mable interconnect consists of a single Global Routing
Pool (GRP). Unlike ispLSI devices, there are no programmable logic arrays on the device. Control signals for
OEs, Clocks/Clock Enables and MUX Controls must
come from designated sets of I/O pins. The polarity of
these signals can be independently programmed in each
I/O cell.
Each I/O cell drives a unique pin. The OE control for each
I/O pin is independent and may be driven via the GRP by
one of the designated I/O pins (I/O-OE set). The I/O-OE
set consists of 25% of the total I/O pins. Boundary Scan
test is supported by dedicated registers at each I/O pin.
In-system programming is accomplished through the
standard Boundary Scan protocol.
I/O Architecture
Each I/O cell contains a 4:1 dynamic MUX controlled by
two select lines as well as a 4x4 crossbar switch con-
trolled by software for increased routing flexiability (Figure
1). The four data inputs to the MUX (called M0, M1, M2,
and M3) come from I/O signals in the GRP and/or
adjacent I/O cells. Each MUX data input can access one
quarter of the total I/Os. For example, in a 160 I/O
ispGDXV, each data input can connect to one of 40 I/O
pins. MUX0 and MUX1 can be driven by designated I/O
pins called MUXsel1 and MUXsel2. Each MUXsel input
covers 25% of the total I/O pins (e.g. 40 out of 160). MUX0
and MUX1 can be driven from either MUXsel1 or MUXsel2.
Figure 1. ispGDXV/VA I/O Cell and GRP Detail (160 I/O Device)
Logic “1”
Logic “0”
I/OCell 0
160 I/O Inputs
I/O Cell 159
I/O Cell 1
•
•
•
•
•
•
I/O Cell 78
I/O Cell 79
80 I/O Cells
160 Input GRP
Inputs Vertical
Outputs Horizontal
E2CMOS
Programmable
Interconnect
I/O Group A
I/O Group B
I/O Group C
I/O Group D
• • • • • •
Y0-Y3
Global
Clocks /
Clock_Enables
From MUX Outputs
of 2 Adjacent I/O Cells
N+2
N+1
N-1
N-2
Global
Reset
4x4
Crossbar
Switch
From MUX Outputs
of 2 Adjacent I/O Cells
80 I/O Cells
ispGDXV/VA architecture enhancements over ispGDX (5V)
4-to-1 MUX
M0
M1
M2
M3
MUX1MUX0
I/O Cell 158
To 2 Adjacent
I/O Cells above
To 2 Adjacent
I/O Cells below
I/O Cell 81
I/O Cell 80
•
•
•
•
•
•
Bypass Option
Register
or Latch
A
D
B
CLK
CLK_EN
Reset
Prog.
Prog.
Bus Hold
Pull-up
Latch
(VCCIO)
C
Q
R
Prog. Open Drain
2.5V/3.3V Output
Prog. Slew Rate
Boundary
Scan Cell
I/O
Pin
I/O Cell N
3
Specifications ispGDX160V/VA
I/O MUX Operation
MUX1 MUX0 Data Input Selected
00 M0
01 M1
11 M2
10 M3
Flexible mapping of MUXselx to MUXx allows the user to
change the MUX select assignment after the ispGDXV/
VA device has been soldered to the board. Figure 1
shows that the I/O cell can accept (by programming the
appropriate fuses) inputs from the MUX outputs of four
adjacent I/O cells, two above and two below. This enables cascading of the MUXes to enable wider (up to
16:1) MUX implementations.
The I/O cell also includes a programmable flow-through
latch or register that can be placed in the input or output
path and bypassed for combinatorial outputs. As shown
in Figure 1, when the input control MUX of the register/
latch selects the “A” path, the register/latch gets its inputs
from the 4:1 MUX and drives the I/O output. When
selecting the “B” path, the register/latch is directly driven
by the I/O input while its output feeds the GRP. The
programmable polarity Clock to the latch or register can
be connected to any I/O in the I/O-CLK/CLKEN set (onequarter of total I/Os) or to one of the dedicated clock input
pins (Yx). The programmable polarity Clock Enable input
to the register can be programmed to connect to any of
the I/O-CLK/CLKEN input pin set or to the global clock
enable inputs (CLKENx). Use of the dedicated clock
inputs gives minimum clock-to-output delays and minimizes delay variation with fanout. Combinatorial output
mode may be implemented by a dedicated architecture
bit and bypass MUX. I/O cell output polarity can be
programmed as active high or active low.
allow adjacent I/O cell outputs to be directly connected
without passing through the global routing pool. The
relationship between the [N+i] adjacent cells and A, B, C
and D inputs will vary depending on where the I/O cell is
located on the physical die. The I/O cells can be grouped
into “normal” and “reflected” I/O cells or I/O “hemi-
spheres.” These are defined as:
Device Normal I/O Cells Reflected I/O Cells
ispGDX80VA
ispGDX160V/VA
ispGDX240VA B29-B0, A59-A0,
B9-B0, A19-A0,
D19-D10
B19-B0, A39-A0,
D39-D20
D59-D30
B10-B19, C0-C19,
D0-D9
B20-B39, C0-C39,
D0-D19
B30-B59, C0-C59,
D0-D29
Table 2 shows the relationship between adjacent I/O
cells as well as their relationship to direct MUX inputs.
Note that the MUX expansion is circular and that I/O cell
B20, for example, draws on I/Os B19 and B18, as well as
B21 and B22, even though they are in different hemi-
spheres of the physical die. Table 2 shows some typical
cases and all boundary cases. All other cells can be
extrapolated from the pattern shown in the table.
Figure 2. I/O Hemisphere Configuration of
ispGDX160V/VA
I/O cell 0 I/O cell 159
A0
D39
D20 D19
D0
C39 C0
MUX Expander Using Adjacent I/O Cells
The ispGDXV/VA allows adjacent I/O cell MUXes to be
cascaded to form wider input MUXes (up to 16 x 1)
without incurring an additional full Tpd penalty. However,
there are certain dependencies on the locality of the
adjacent MUXes when used along with direct MUX
inputs.
Adjacent I/O Cells
Expansion inputs MUXOUT[n-2], MUXOUT[n-1],
MUXOUT[n+1], and MUXOUT[n+2] are fuse-selectable
for each I/O cell MUX. These expansion inputs share the
same path as the standard A, B, C and D MUX inputs, and
I/O cell index increases in this direction
A39
B0
I/O cell 79 I/O cell 80
B19 B20
B39
Direct and Expander Input Routing
Table 2 also illustrates the routing of MUX direct inputs
that are accessible when using adjacent I/O cells as
inputs. Take I/O cell D23 as an example, which is also
shown in Figure 3.
4
I/O cell index increases in this direction
Specifications ispGDX160V/VA
Figure 3. Adjacent I/O Cells vs. Direct Input Path for
ispGDX160V/VA, I/O D23
ispGDX160V/VA I/O Cell
I/O Group A
D21 MUX Out
I/O Group B
D22 MUX Out
I/O Group C
D24 MUX Out
I/O Group D
D25 MUX Out
4 x 4
Crossbar
Switch
.m0
.m1
.m2
.m3
S0S1
D23
It can be seen from Figure 3 that if the D21 adjacent I/O
cell is used, the I/O group “A” input is no longer available
as a direct MUX input.
The ispGDXV/VA can implement MUXes up to 16 bits
wide in a single level of logic, but care must be taken
when combining adjacent I/O cell outputs with direct
MUX inputs. Any particular combination of adjacent I/O
cells as MUX inputs will dictate what I/O groups (A, B, C
or D) can be routed to the remaining inputs. By properly
choosing the adjacent I/O cells, all of the MUX inputs can
be utilized.
Special Features
Slew Rate Control
All output buffers contain a programmable slew rate
control that provides software-selectable slew rate op-
tions.
Open Drain Control
All output buffers provide a programmable Open-Drain
option which allows the user to drive system level reset,
interrupt and enable/disable lines directly without the
need for an off-chip Open-Drain or Open-Collector buffer.
Wire-OR logic functions can be performed at the printed
circuit board level.
Pull-up Resistor
All pins have a programmable active pull-up. A typical
resistor value for the pull-up ranges from 50kΩ to 80kΩ.
Output Latch (Bus Hold)
All pins have a programmable circuit that weakly holds
the previously driven state when all drivers connected to
the pin (including the pin's output driver as well as any
other devices connected to the pin by external bus) are
tristated.
Table 2. Adjacent I/O Cells (Mapping of
ispGDX160V/VA)
Data C/
MUXOUT
Reflected
I/O Cells
Normal
I/O Cells
B20
B21
B22
B23
D16
D17
D18
D19
D20
D21
D22
D23
B16
B17
B18
B19
Data A/
MUXOUT
B22
B23
B24
B25
D18
D19
D20
D21
D18
D19
D20
D21
B14
B15
B16
B17
Data B/
MUXOUT
B21
B22
B23
B24
D17
D18
D19
D20
D19
D20
D21
D22
B15
B16
B17
B18
B19
B20
B21
B22
D15
D16
D17
D18
D21
D22
D23
D24
B17
B18
B19
B20
Data D/
MUXOUT
B18
B19
B20
B21
D14
D15
D16
D17
D22
D23
D24
D25
B18
B19
B20
B21
ispGDX160VA New Features
Unique to the ispGDX160VA are user-programmable
I/Os supporting either 3.3V or 2.5V output voltage level
options. The ispGDX160VA uses a VCCIO pin to provide
the 2.5V reference voltage when used. The ispGDX160VA
VCCIO pin occupies the same location as VCC on the
ispGDX160V, allowing drop-in replacement. The
ispGDX160VA offers improved performance by reducing
fanout delays and has PCI compatible drive capability.
Only the ispGDX160VA is available in the fastest (3.5ns)
Commercial speed grade and in -5,-7, and -9ns Industrial
grades in all packages.
The ispGDX160VA has a device ID different from the
ispGDX160V requiring that the latest Lattice download
software be used for programming and verification. Al-
though the ispGDX160VA and ispGDX160V are
functionally equivalent, they are not 100% JEDEC com-
patible. All design files must be recompiled targeting the
ispGDX160VA.
5
Applications
Specifications ispGDX160V/VA
The ispGDXV/VA Family architecture has been developed to deliver an in-system programmable signal routing
solution with high speed and high flexibility. The devices
are targeted for three similar but distinct classes of endsystem applications:
Programmable, Random Signal
Interconnect (PRSI)
This class includes PCB-level programmable signal routing and may be used to provide arbitrary signal swapping
between chips. It opens up the possibilities of programmable system hardware. It is characterized by the need
to provide a large number of 1:1 pin connections which
are statically configured, i.e., the pin-to-pin paths do not
need to change dynamically in response to control inputs.
Programmable Data Path (PDP)
This application area includes system data path transceiver, MUX and latch functions. With today’s 32- and
64-bit microprocessor buses, but standard data path glue
components still relegated primarily to eight bits, PCBs
are frequently crammed with a dozen or more data path
glue chips that use valuable real estate. Many of these
applications consist of “on-board” bus and memory interfaces that do not require the very high drive of standard
glue functions but can benefit from higher integration.
Therefore, there is a need for a flexible means to integrate these on-board data path functions in an analogous
way to programmable logic’s solution to control logic
integration. Lattice’s CPLDs make an ideal control logic
complement to the ispGDXV/VA in-system programmable data path devices as shown below.
Figure 4. ispGDXV/VA Complements Lattice CPLDs
Address
Inputs
(from P)
Control
Inputs
(from P)
Data Path
Bus #1
Programmable Switch Replacement (PSR)
Includes solid-state replacement and integration of me-
chanical DIP Switch and jumper functions. Through
in-system programming, pins of the ispGDXV/VA de-
vices can be driven to HIGH or LOW logic levels to
emulate the traditional device outputs. PSR functions do
not require any input pin connections.
These applications actually require somewhat different
silicon features. PRSI functions require that the device
support arbitrary signal routing on-chip between any two
pins with no routing restrictions. The routing connections
are static (determined at programming time) and each
input-to-output path operates independently. As a result,
there is little need for dynamic signal controls (OE,
clocks, etc.). Because the ispGDXV/VA device will inter-
face with control logic outputs from other components
(such as ispLSI or ispMACH) on the board (which fre-
quently change late in the design process as control logic
is finalized), there must be no restrictions on pin-to-pin
signal routing for this type of application.
PDP functions, on the other hand, require the ability to
dynamically switch signal routing (MUXing) as well as
latch and tri-state output signals. As a result, the pro-
grammable interconnect is used to define
routes that are then selected dynamically by control
signals from an external MPU or control logic. These
functions are usually formulated early in the conceptual
design of a product. The data path requirements are
driven by the microprocessor, bus and memory architec-
ture defined for the system. This part of the design is the
earliest portion of the system design frozen, and will not
usually change late in the design because the result
would be total system and PCB redesign. As a result, the
ability to accommodate
arbitrary
any pin-to-any pin rerouting is not a strong requirement as long as the designer
has the ability to define his functions with a reasonable
degree of freedom initially.
possible
signal
ispMACH
System
Clock(s)
ispLSI/
Device
Control
Outputs
Buffers / RegistersState Machines
ispGDXV/VA
Device
Buffers / RegistersDecoders
Data Path
Bus #2
ISP/JTAG
Interface
Configuration
(Switch)
Outputs
As a result, the ispGDXV/VA architecture has been
defined to support PSR and PRSI applications (including
bidirectional paths) with no restrictions, while PDP applications (using dynamic MUXing) are supported with a
minimal number of restrictions as described below. In this
way, speed and cost can be optimized and the devices
can still support the system designer’s needs.
The following diagrams illustrate several ispGDXV/VA
applications.
6
Applications (Continued)
Specifications ispGDX160V/VA
Figure 5. Address Demultiplex/Data Buffering
XCVR
Control Bus
MUXed Address Data Bus
I/OA I/OB
OEA OEB
Address
Latch
DQ
CLK
Buffered
Data
To Memory/
Peripherals
Address
Figure 6. Data Bus Byte Swapper
XCVR
I/OA
I/OB
OEA OEB
XCVR
I/OA I/OB
OEA OEB
D0-7
XCVR
I/OA I/OB
OEA OEB
XCVR
I/OA I/OB
OEA OEB
Control Bus
D0-7
Data Bus A
D8-15 D8-15
Data Bus B
Designing with the ispGDXV/VA
As mentioned earlier, this architecture satisfies the PRSI
class of applications without restrictions: any I/O pin as a
single input or bidirectional can drive any other I/O pin as
output.
For the case of PDP applications, the designer does have
to take into consideration the limitations on pins that can
be used as control (MUX0, MUX1, OE, CLK) or data
(MUXA-D) inputs. The restrictions on control inputs are
not likely to cause any major design issues because the
input possibilities span 25% of the total pins.
The MUXA-D input partitioning requires that designers
consciously assign pinouts so that MUX inputs are in the
appropriate, disjoint groups. For example, since the
MUXA group includes I/O0-39 (160 I/O device), it is not
possible to use I/O0 and I/O9 in the same MUX function.
As previously discussed, data path functions will be
assigned early in the design process and these restrictions are reasonable in order to optimize speed and cost.
User Electronic Signature
The ispGDXV/VA Family includes dedicated User Electronic Signature (UES) E2CMOS storage to allow users
to code design-specific information into the devices to
identify particular manufacturing dates, code revisions,
or the like. The UES information is accessible through
the boundary scan programming port via a specific command. This information can be read even when the
security cell is programmed.
Figure 7. Four-Port Memory Interface
4-to-1
16-Bit MUX
Bidirectional
Port #1
OE1
Port #2
OE2
Bus 4
Bus 3
Bus 2
Bus 1
Note: All OE and SEL lines driven by external arbiter logic (not shown).
Port #3
OE3
Port #4
OE4
Memory
Port
OEM
SEL0
SEL1
To
Memory
Security
The ispGDXV/VA Family includes a security feature that
prevents reading the device program once set. Even
when set, it does not inhibit reading the UES or device ID
code. It can be erased only via a device bulk erase.
7
Specifications ispGDX160VA
Absolute Maximum Ratings
1,2
Supply Voltage Vcc................................. -0.5 to +5.4V
Input Voltage Applied............................... -0.5 to +5.6V
Off-State Output Voltage Applied ............ -0.5 to +5.6V
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150 °C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.
DC Recommended Operating Conditions
SYMBOL
VCC
VCCIO
PARAMETER
Supply Voltage
I/O Reference Voltage
Commercial
Industrial
= 0°C to +70°C
T
A
T
= -40°C to +85°C
A
MIN. MAX. UNITS
3.00
3.00 3.60 V
2.3
3.60
3.60
Table 2-0005/gdx160va
V
V
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL
C
1
C
2
I/O Capacitance
Dedicated Clock Capacitance
PARAMETER PACKAGE TYPE
BGA, fpBGA
PQFP
BGA, fpBGA
UNITSTYPICAL TEST CONDITIONS
7PQFP
10 pf
8
10 pf
pf
pf
V = 3.3V, V = 2.0V
CC
V = 3.3V, V = 2.0V
CC Y
I/O
Table 2-0006/gdx160va
Erase/Reprogram Specifications
PARAMETER MINIMUM MAXIMUM UNITS
Erase/Reprogram Cycles 10,000 — Cycles
8
Switching Test Conditions
V
CCIO
R
1
R
2
C
L
*
Device
Output
Test
Point
*C
L
includes Test Fixture and Probe Capacitance.
0213D
Input Pulse Levels
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.5V from steady-state active level.
Output Load Conditions (See Figure 8)
3.3V 2.5V
TEST CONDITION R1
A 35pF
Active High
B
Active Low
Active High to Z
at V -0.5V
C
D 35pF
OH
Active Low to Z
at V +0.5V
OL
Slow Slew
R1 R2
153Ω
∞
153Ω
∞
153Ω
∞
GND to V
< 1.5ns 10% to 90%
V
V
See Figure 8
156Ω
134Ω
134Ω
∞
134Ω
∞
∞
∞
156Ω
∞
156Ω
∞
CCIO(MIN)
CCIO(MIN)
CCIO(MIN)
/2
/2
R2 CL
144Ω
144Ω
35pF
∞
35pF
144Ω
∞
∞
Table 2-0004A/gdx160va
Specifications ispGDX160VA
Figure 8. Test Load
5pF
5pF
DC Electrical Characteristics for 3.3V Range
Over Recommended Operating Conditions
SYMBOL
VCCIO
VIL
VIH
VOL
VOH
I/O Reference Voltage 3.0 –– 3.6 V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
1. I/O voltage configuration must be set to VCC.
PARAMETER
VOH ≤ V
VOH ≤ V
V
CC
V
CC
= V
= V
1
CONDITION MIN. TYP. MAX. UNITS
0.8
or V
OUT
or V
OUT
CC (MIN)
CC (MIN)
≤ V
OUT
OUT
≤ V
OL (MAX)
OL(MAX)
IOL = +100µA
= +24mA
I
OL
I
= -100µA
OH
I
= -12mA
OH
-0.3
2.0
–
––0.55 V
2.8
2.4 ––V
–
5.25
–
0.2
–
–
Table 2-0007/gdx160va
–
V
V
V
V
9
Specifications ispGDX160VA
DC Electrical Characteristics for 2.5V Range
1
Over Recommended Operating Conditions
SYMBOL
VCCIO
VIL
VIH
VOL
VOH
I/O Reference Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
PARAMETER
1. I/O voltage configuration must be set to VCCIO.
V
OH(MIN)
V
OH(MIN)
V
CCIO=MIN
V
CCIO=MIN
V
CCIO=MIN
V
CCIO=MIN
CONDITION MIN. TYP. MAX. UNITS
≤ V
≤ V
, I
, I
, I
, I
OUT
OUT
= 100µA
OL
= 8mA
OL
= -100µA
OH
= -8mA
OH
or V
or V
OUT
OUT
≤ V
≤ V
OL(MAX)
OL(MAX)
2.3
-0.3
1.7
––0.2 V
––0.6 V
2.1 ––V
1.8
––
2.7
–
0.7
–
5.25
–
–
2.5V/gdx160va
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
IIL
IIH
IPU
IBHLS
Input or I/O Low Leakage Current 0V ≤ V
Input or I/O High Leakage Current
I/O Active Pullup Current
Bus Hold Low Sustaining Current
IBHHS Bus Hold High Sustaining Current -40 ––µA
IBHLO Bus Hold Low Overdrive Current ––550 µA
IBHHO Bus Hold High Overdrive Current ––-550 µA
IBHT
IOS
ICCQ
ICC
Bus Hold Trip Points
1
Output Short Circuit Current ––-250 mA
4
Quiescent Power Supply Current – 16.5 – mA
Dynamic Power Supply Current
per Input Switching
PARAMETER
IN
(V
-0.2) ≤ V
CCIO
V
≤ VIN ≤ 5.25V
CCIO
0V
≤ VIN ≤ V
= V
V
IN
IL (MAX)
VIN = V
IH (MIN)
0V ≤ V
IN
0V ≤ V
IN
= 3.3V, V
V
CC
= 0.5V, V
V
IL
One input toggling at 50% duty cycle,
outputs open.
CONDITION MIN. TYP.2MAX. UNITS
≤ V
IL (MAX)
≤ V
IN
IL (MAX)
CCIO
–
–
–
–
–
–
–
–
40 ––µA
≤ V
CCIO
≤ V
CCIO
= 0.5V, TA = 25°C
OUT
= V
IH
CC
V
IL
– V
– See
Note 3
-10
10
50
-200
IH
– mA/
V
V
V
V
µA
µA
µA
µA
V
MHz
Maximum Continuous I/O Pin Sink
5
ICONT
Current Through Any GND Pin
1. One output at a time for a maximum of one second. V
–
= 0.5V was selected to avoid test problems by
OUT
––160 mA
tester ground degradation. Characterized, but not 100% tested.
2. Typical values are at V
= 3.3V and T
CC
= 25°C.
A
3. ICC / MHz = (0.003 x I/O cell fanout) + 0.029.
e.g. An input driving four I/O cells at 40MHz results in a dynamic I
of approximately ((0.003 x 4) + 0.029) x 40 = 1.64mA.
CC
4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bi-directionals.
5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin.
10
DC Char_gdx160va
External Timing Parameters
Over Recommended Operating Conditions
Specifications ispGDX160VA
1
PARAMETER
2
tpd
2
tsel
TEST
COND.
fmax (Tog.)
fmax (Ext.)
tsu1
tsu2
tsu3
tsu4
tsuce1
tsuce2
tsuce3
th1
th2
th3
th4
thce1
thce2
thce3
2
tgco1
2
tgco2
2
tco1
2
tco2
2
ten
2
tdis
2
ttoeen
2
ttoedis
twh
twl
trst
trw
tsl
tsk
1. All timings measured with one output switching, fast output slew rate setting, except tsl.
2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is
used as I/O voltage reference.
#
A
A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
A
A
A
A
B
C
B
C
–
–
–
–
D
A
Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX)
1
Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX)
2
Clock Frequency, Max. Toggle
3
Clock Frequency with External Feedback
4
Input Latch or Register Setup Time Before Y
5
Input Latch or Register Setup Time Before I/O Clock
6
Output Latch or Register Setup Time Before Y
7
Output Latch or Register Setup Time Before I/O Clock
8
Global Clock Enable Setup Time Before Y
9
Global Clock Enable Setup Time Before I/O Clock
10
I/O Clock Enable Setup Time Before Y
11
Input Latch or Reg. Hold Time (Yx)
12
Input Latch or Reg. Hold Time (I/O Clock)
13
Output Latch or Reg. Hold Time (Y
14
Output Latch or Reg. Hold Time (I/O Clock)
15
Global Clock Enable Hold Time (Y
16
Global Clock Enable Hold Time (I/O Clock)
17
I/O Clock Enable Hold Time (Y
18
Output Latch or Reg. Clock (from Y
19
Input Latch or Register Clock (from Y
20
Output Latch or Register Clock (from I/O pin) to Output Delay
21
Input Latch or Register Clock (from I/O pin) to Output Delay
22
Input to Output Enable
23
Input to Output Disable
24
Test OE Output Enable
25
Test OE Output Disable
26
Clock Pulse Duration, High
27
Clock Pulse Duration, Low
28
Register Reset Delay from RESET Low
29
Reset Pulse Width
30
Output Delay Adder for Output Timings Using Slow Slew Rate
31
Output Skew (tgco1 Across Chip)
32
DESCRIPTION
x
)
x
)
x
)
x
) to Output Delay
x
) to Output Delay
x
1
( )
tsu3+tgco1
x
x
x
-3
MIN. MAX.
3.5
–
3.5
–
–
250
3.0
2.5
2.5
2.0
2.5
1.5
3.0
0.0
0.5
0.0
1.0
0.0
1.0
0.0
–
–
–
–
–
–
–
–
2.0
2.0
–
5.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3.5
6.0
4.0
7.0
5.0
5.0
6.0
6.0
–
–
8.0
–
3.5
0.5
166.7
-5
MIN. MAX.
5.0
–
5.0
–
4.0
3.0
4.0
3.0
2.5
1.5
4.5
0.0
1.5
0.0
1.5
0.0
1.5
0.0
–
–
–
–
–
–
–
–
3.5
3.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
5.0
8.5
6.0
9.5
6.0
6.0
6.0
6.0
–
–
14.0
–
5.0
0.5
143
111
10.0
UNITS
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
External Timing Parameters
Over Recommended Operating Conditions
Specifications ispGDX160VA
1
PARAMETER
2
tpd
2
tsel
TEST
COND.
fmax (Tog.)
fmax (Ext.)
tsu1
tsu2
tsu3
tsu4
tsuce1
tsuce2
tsuce3
th1
th2
th3
th4
thce1
thce2
thce3
2
tgco1
2
tgco2
2
tco1
2
tco2
2
ten
2
tdis
2
ttoeen
2
ttoedis
twh
twl
trst
trw
tsl
tsk
1. All timings measured with one output switching, fast output slew rate setting, except tsl.
2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is
used as I/O voltage reference.
#
A
A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
A
A
A
A
B
C
B
C
–
–
–
–
D
A
Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX)
1
Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX)
2
Clock Frequency, Max. Toggle
3
Clock Frequency with External Feedback
4
Input Latch or Register Setup Time Before Y
5
Input Latch or Register Setup Time Before I/O Clock
6
Output Latch or Register Setup Time Before Y
7
Output Latch or Register Setup Time Before I/O Clock
8
Global Clock Enable Setup Time Before Y
9
Global Clock Enable Setup Time Before I/O Clock
10
I/O Clock Enable Setup Time Before Y
11
Input Latch or Reg. Hold Time (Yx)
12
Input Latch or Reg. Hold Time (I/O Clock)
13
Output Latch or Reg. Hold Time (Y
14
Output Latch or Reg. Hold Time (I/O Clock)
15
Global Clock Enable Hold Time (Y
16
Global Clock Enable Hold Time (I/O Clock)
17
I/O Clock Enable Hold Time (Y
18
Output Latch or Reg. Clock (from Y
19
Input Latch or Register Clock (from Y
20
Output Latch or Register Clock (from I/O pin) to Output Delay
21
Input Latch or Register Clock (from I/O pin) to Output Delay
22
Input to Output Enable
23
Input to Output Disable
24
Test OE Output Enable
25
Test OE Output Disable
26
Clock Pulse Duration, High
27
Clock Pulse Duration, Low
28
Register Reset Delay from RESET Low
29
Reset Pulse Width
30
Output Delay Adder for Output Timings Using Slow Slew Rate
31
Output Skew (tgco1 Across Chip)
32
DESCRIPTION
x
)
x
)
x
)
x
) to Output Delay
x
) to Output Delay
x
1
( )
tsu3+tgco1
x
x
x
-7
MIN. MAX.
–
7.0
–
7.0
100
–
80
–
5.5
–
4.5
–
5.5
–
4.5
–
3.5
–
2.5
–
6.5
–
0.0
–
2.5
–
0.0
–
2.5
–
0.0
–
2.5
–
0.0
–
–
7.0
–
11.0
–
9.0
–
13.0
–
8.5
–
8.5
–
8.5
–
8.5
5.0
–
5.0
–
–
18.0
14.0
–
–
7.0
–
0.5
-9
MIN. MAX.
9.0
–
9.0
–
–
83
7.0
6.0
7.0
6.0
4.0
3.0
8.5
0.0
3.0
0.0
3.0
0.0
3.0
0.0
–
–
–
–
–
–
–
–
6.0
6.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
9.0
13.5
11.5
15.7
10.5
10.5
10.5
10.5
–
–
22.0
–
9.0
1.0
62.5
18.0
UNITS
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
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