Lattice ispGAL22V10 User Manual
• IN-SYSTEM PROGRAMMABLE™ (5-V ONL Y)
— 4-Wire Serial Programming Interface
— Minimum 10,000 Program/Erase Cycles
— Built-in Pull-Down on SDI Pin Eliminates Discrete
Resistor on Board (ispGAL22V10C Only)
2
• HIGH PERFORMANCE E
CMOS® TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 11 1 MHz
— 5 ns Maximum from Clock Input to Data Output
— UltraMOS® Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS
• COMPATIBLE WITH STANDARD 22V10 DEVICES
— Fully Function/Fuse-Map/Parametric Compatible
with Bipolar and CMOS 22V10 Devices
2
CELL TECHNOLOGY
•E
— In-System Programmable Logic
— 100% Tested/100% Y ields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Software-Driven Hardware Configuration
• ELECTRONIC SIGNA TURE FOR IDENTIFICATION
DESCRIPTION
The ispGAL22V10, at 7.5ns maximum propagation delay time,
combines a high performance CMOS process with Electrically
Erasable (E
first in-system programmable 22V10 device. E
2
) floating gate technology to provide the industry's
2
technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently .
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The ispGAL22V10 is fully function/fuse map/parametric
compatible with standard bipolar and CMOS 22V10 devices. The
standard PLCC package provides the same functional pinout as
the standard 22V10 PLCC package with No-Connect pins being
used for the ISP interface signals.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 10,000 erase/write
cycles and data retention in excess of 20 years are specified.
Specifications ispGAL22V10
ispGAL22V10
In-System Programmable E2CMOS PLD
Generic Array Logic™
FUNCTIONAL BLOCK DIAGRAMFEATURES
I/CLK
I
I
I
I
I
I
I
I
I
I
I
SDO
MODE
SCLK
SDI
PROGRAMMING
LOGIC
PIN CONFIGURA TION
PLCC
I
I
I/CLK
228
4
I
5
I
7
I
ispGAL22V10
MODE
I
I
I
T op View
9
11
14 16
12 18
I
I
GND
AND-ARRAY
PROGRAMMABLE
Vcc
SCLK
I/O/Q
I/O/Q
26
25
I/O/Q
I/O/Q
23
I/O/Q
SDO
I/O/Q
21
I/O/Q
19
I/O/Q
I
SDI
I/O/Q
I/O/Q
RESET
8
OLMC
10
OLMC
12
OLMC
14
OLMC
16
OLMC
16
SCLK
I/CLK
GND
14
12
10
8
PRESET
I
I
I
I
I
I
I
I
I
I
OLMC
OLMC
OLMC
OLMC
OLMC
1
ispGAL
7
T op View
14
(132X44)
MODE
SSOP
22V10
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
28
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
22
SDO
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
15
SDI
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. July 1997
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
isp22v10_02
1
Specifications ispGAL22V10
ORDERING INFORMATION
Commercial Grade Specifications
)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP
5.75.65041JL7-C01V22LAGpsiCCLPdaeL-82
01V22LAGpsiCL7-K daeL-82POSS
01V22LAGpsiBJL7-CCLPdaeL-82
0177 041JL01-C01V22LAGpsiCCLPdaeL-82
01V22LAGpsiC-01LK daeL-82POSS
01V22LAGpsiBJL01-CCLPdaeL-82
51018 041JL51-C01V22LAGpsiCCLPdaeL-82
01V22LAGpsiC-51LK daeL-82POSS
01V22LAGpsiBJL51-CCLPdaeL-82
Industrial Grade Specifications
)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP
51018 561IJL51-C01V22LAGpsiCCLPdaeL-82
01V22LAGpsiC-51LIKdaeL-82POSS
PART NUMBER DESCRIPTION
ispGAL22V10C
ispGAL22V10B
Device Name
Speed (ns)
PowerL = Low Power
XXXXXXXX XX X X X
_
Grade
Package
Blank = Commercial
I = Industrial
J = PLCC
K = SSOP
2
OUTPUT LOGIC MACROCELL (OLMC)
The ispGAL22V10 has a variable number of product terms per
OLMC. Of the ten available OLMCs, two OLMCs have access to
eight product terms (pins 17 and 27), two have ten product terms
(pins 18 and 26), two have twelve product terms (pins 19 and 25),
two have fourteen product terms (pins 20 and 24), and two
OLMCs have sixteen product terms (pins 21 and 23). In addition
to the product terms available for logic, each OLMC has an additional product-term dedicated to output enable control.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either
active high or active low.
AR
D
Specifications ispGAL22V10
The ispGAL22V10 has a product term for Asynchronous Reset
(AR) and a product term for Synchronous Preset (SP). These two
product terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to zero any time this dedicated
product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after
this product term is asserted.
NOTE: The AR and SP product terms will force the Q output of
the flip-flop into the same state regardless of the polarity of the
output. Therefore, a reset operation, which sets the register output
to a zero, may result in either a high or low at the output pin,
depending on the pin polarity chosen.
Q
QCLK
4 TO 1
MUX
SP
2 TO 1
MUX
ispGAL22V10 OUTPUT LOGIC MACROCELL (OLMC)
OUTPUT LOGIC MACROCELL CONFIGURATIONS
Each of the Macrocells of the ispGAL22V10 has two primary functional modes: registered, and combinatorial I/O. The modes and
the output polarity are set by two bits (SO and S1), which are normally controlled by the logic compiler. Each of these two primary
modes, and the bit settings required to enable them, are described
below and on the following page.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC’s D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an individual product-term for each OLMC, and can therefore be defined by a logic equation. The D flip-flop’s /Q output is fed back
into the AND array, with both the true and complement of the
feedback available as inputs to the AND array.
NOTE: In registered mode, the feedback is from the /Q output of
the register, and not from the pin; therefore, a pin defined as
registered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.
COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the
output buffer drive either true (active high) or inverted (active low).
Output tri-state control is available as an individual product-term
for each output, and may be individually set by the compiler as
either “on” (dedicated output), “off” (dedicated input), or “productterm driven” (dynamic I/O). Feedback into the AND array is from
the pin side of the output enable buffer. Both polarities (true and
inverted) of the pin are fed back into the AND array.
3
REGISTERED MODE
Specifications ispGAL22V10
D
CLK
S0 = 0
S1 = 0
COMBINATORIAL MODE
AR
SP
Q
Q
S0 = 1
S1 = 0
CLK
AR
D
ACTIVE HIGHACTIVE LOW
Q
Q
SP
S0 = 0
S1 = 1
ACTIVE HIGHACTIVE LOW
S0 = 1
S1 = 1
4
Specifications ispGAL22V10
ispGAL22V10 LOGIC DIAGRAM / JEDEC FUSE MAP
PLCC & SSOP Package Pinout
2
3
4
5
6
7
9
10
11
12
13 16
0 4 8 1216202428323640
0000
0044
.
.
.
0396
0440
.
.
.
.
0880
0924
.
.
.
.
.
1452
1496
.
.
.
.
.
.
2112
2156
.
.
.
.
.
.
.
2860
2904
.
.
.
.
.
.
.
3608
3652
.
.
.
.
.
.
4268
4312
.
.
.
.
.
4840
4884
.
.
.
.
5324
5368
.
.
.
5720
5764
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
8
10
12
14
16
16
14
12
10
OLMC
S0
5808
S1
5809
OLMC
S0
5810
S1
5811
OLMC
S0
5812
S1
5813
OLMC
S0
5814
S1
5815
OLMC
S0
5816
S1
5817
OLMC
S0
5818
S1
5819
OLMC
S0
5820
S1
5821
OLMC
S0
5822
S1
5823
OLMC
S0
5824
S1
5825
8
OLMC
S0
5826
S1
5827
SYNCHRONOUS PRESET
(TO ALL REGISTERS)
27
26
25
24
23
21
20
19
18
17
Byte 7 Byte 6 Byte 5 Byte 4 Byte 2 Byte 1 Byte 0Byte 3
Electronic Signature 5828, 5829 ... ... 5890, 5891
M
L
S
S
B
B
5
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