• IN-SYSTEM PROGRAMMABLE™ (5-V ONL Y)
— 4-Wire Serial Programming Interface
— Minimum 10,000 Program/Erase Cycles
— Built-in Pull-Down on SDI Pin Eliminates Discrete
Resistor on Board (ispGAL22V10C Only)
2
• HIGH PERFORMANCE E
CMOS® TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 11 1 MHz
— 5 ns Maximum from Clock Input to Data Output
— UltraMOS® Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS
• COMPATIBLE WITH STANDARD 22V10 DEVICES
— Fully Function/Fuse-Map/Parametric Compatible
with Bipolar and CMOS 22V10 Devices
2
CELL TECHNOLOGY
•E
— In-System Programmable Logic
— 100% Tested/100% Y ields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Software-Driven Hardware Configuration
• ELECTRONIC SIGNA TURE FOR IDENTIFICATION
DESCRIPTION
The ispGAL22V10, at 7.5ns maximum propagation delay time,
combines a high performance CMOS process with Electrically
Erasable (E
first in-system programmable 22V10 device. E
2
) floating gate technology to provide the industry's
2
technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently .
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The ispGAL22V10 is fully function/fuse map/parametric
compatible with standard bipolar and CMOS 22V10 devices. The
standard PLCC package provides the same functional pinout as
the standard 22V10 PLCC package with No-Connect pins being
used for the ISP interface signals.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 10,000 erase/write
cycles and data retention in excess of 20 years are specified.
Specifications ispGAL22V10
ispGAL22V10
In-System Programmable E2CMOS PLD
Generic Array Logic™
FUNCTIONAL BLOCK DIAGRAMFEATURES
I/CLK
I
I
I
I
I
I
I
I
I
I
I
SDO
MODE
SCLK
SDI
PROGRAMMING
LOGIC
PIN CONFIGURA TION
PLCC
I
I
I/CLK
228
4
I
5
I
7
I
ispGAL22V10
MODE
I
I
I
T op View
9
11
14 16
12 18
I
I
GND
AND-ARRAY
PROGRAMMABLE
Vcc
SCLK
I/O/Q
I/O/Q
26
25
I/O/Q
I/O/Q
23
I/O/Q
SDO
I/O/Q
21
I/O/Q
19
I/O/Q
I
SDI
I/O/Q
I/O/Q
RESET
8
OLMC
10
OLMC
12
OLMC
14
OLMC
16
OLMC
16
SCLK
I/CLK
GND
14
12
10
8
PRESET
I
I
I
I
I
I
I
I
I
I
OLMC
OLMC
OLMC
OLMC
OLMC
1
ispGAL
7
T op View
14
(132X44)
MODE
SSOP
22V10
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
28
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
22
SDO
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
15
SDI
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. July 1997
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
isp22v10_02
1
Specifications ispGAL22V10
ORDERING INFORMATION
Commercial Grade Specifications
)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP
5.75.65041JL7-C01V22LAGpsiCCLPdaeL-82
01V22LAGpsiCL7-K daeL-82POSS
01V22LAGpsiBJL7-CCLPdaeL-82
0177 041JL01-C01V22LAGpsiCCLPdaeL-82
01V22LAGpsiC-01LK daeL-82POSS
01V22LAGpsiBJL01-CCLPdaeL-82
51018 041JL51-C01V22LAGpsiCCLPdaeL-82
01V22LAGpsiC-51LK daeL-82POSS
01V22LAGpsiBJL51-CCLPdaeL-82
Industrial Grade Specifications
)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP
51018 561IJL51-C01V22LAGpsiCCLPdaeL-82
01V22LAGpsiC-51LIKdaeL-82POSS
PART NUMBER DESCRIPTION
ispGAL22V10C
ispGAL22V10B
Device Name
Speed (ns)
PowerL = Low Power
XXXXXXXX XX X X X
_
Grade
Package
Blank = Commercial
I = Industrial
J = PLCC
K = SSOP
2
OUTPUT LOGIC MACROCELL (OLMC)
The ispGAL22V10 has a variable number of product terms per
OLMC. Of the ten available OLMCs, two OLMCs have access to
eight product terms (pins 17 and 27), two have ten product terms
(pins 18 and 26), two have twelve product terms (pins 19 and 25),
two have fourteen product terms (pins 20 and 24), and two
OLMCs have sixteen product terms (pins 21 and 23). In addition
to the product terms available for logic, each OLMC has an additional product-term dedicated to output enable control.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either
active high or active low.
AR
D
Specifications ispGAL22V10
The ispGAL22V10 has a product term for Asynchronous Reset
(AR) and a product term for Synchronous Preset (SP). These two
product terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to zero any time this dedicated
product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after
this product term is asserted.
NOTE: The AR and SP product terms will force the Q output of
the flip-flop into the same state regardless of the polarity of the
output. Therefore, a reset operation, which sets the register output
to a zero, may result in either a high or low at the output pin,
depending on the pin polarity chosen.
Q
QCLK
4 TO 1
MUX
SP
2 TO 1
MUX
ispGAL22V10 OUTPUT LOGIC MACROCELL (OLMC)
OUTPUT LOGIC MACROCELL CONFIGURATIONS
Each of the Macrocells of the ispGAL22V10 has two primary functional modes: registered, and combinatorial I/O. The modes and
the output polarity are set by two bits (SO and S1), which are normally controlled by the logic compiler. Each of these two primary
modes, and the bit settings required to enable them, are described
below and on the following page.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC’s D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an individual product-term for each OLMC, and can therefore be defined by a logic equation. The D flip-flop’s /Q output is fed back
into the AND array, with both the true and complement of the
feedback available as inputs to the AND array.
NOTE: In registered mode, the feedback is from the /Q output of
the register, and not from the pin; therefore, a pin defined as
registered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.
COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the
output buffer drive either true (active high) or inverted (active low).
Output tri-state control is available as an individual product-term
for each output, and may be individually set by the compiler as
either “on” (dedicated output), “off” (dedicated input), or “productterm driven” (dynamic I/O). Feedback into the AND array is from
the pin side of the output enable buffer. Both polarities (true and
inverted) of the pin are fed back into the AND array.
3
REGISTERED MODE
Specifications ispGAL22V10
D
CLK
S0 = 0
S1 = 0
COMBINATORIAL MODE
AR
SP
Q
Q
S0 = 1
S1 = 0
CLK
AR
D
ACTIVE HIGHACTIVE LOW
Q
Q
SP
S0 = 0
S1 = 1
ACTIVE HIGHACTIVE LOW
S0 = 1
S1 = 1
4
Specifications ispGAL22V10
ispGAL22V10 LOGIC DIAGRAM / JEDEC FUSE MAP
PLCC & SSOP Package Pinout
2
3
4
5
6
7
9
10
11
12
13 16
0 4 8 1216202428323640
0000
0044
.
.
.
0396
0440
.
.
.
.
0880
0924
.
.
.
.
.
1452
1496
.
.
.
.
.
.
2112
2156
.
.
.
.
.
.
.
2860
2904
.
.
.
.
.
.
.
3608
3652
.
.
.
.
.
.
4268
4312
.
.
.
.
.
4840
4884
.
.
.
.
5324
5368
.
.
.
5720
5764
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
8
10
12
14
16
16
14
12
10
OLMC
S0
5808
S1
5809
OLMC
S0
5810
S1
5811
OLMC
S0
5812
S1
5813
OLMC
S0
5814
S1
5815
OLMC
S0
5816
S1
5817
OLMC
S0
5818
S1
5819
OLMC
S0
5820
S1
5821
OLMC
S0
5822
S1
5823
OLMC
S0
5824
S1
5825
8
OLMC
S0
5826
S1
5827
SYNCHRONOUS PRESET
(TO ALL REGISTERS)
27
26
25
24
23
21
20
19
18
17
Byte 7 Byte 6 Byte 5 Byte 4 Byte 2 Byte 1 Byte 0Byte 3
Electronic Signature 5828, 5829 ... ... 5890, 5891
M
L
S
S
B
B
5
Specifications ispGAL22V10C
Specifications ispGAL22V10
ispGAL22V10B
ABSOLUTE MAXIMUM RA TINGS
Supply voltage VCC....................................... -0.5 to +7V
Input voltage applied ...........................-2.5 to VCC +1.0V
Off-state output voltage applied........... -2.5 to VCC +1.0V
Storage Temperature..................................-65 to 150°C
Ambient T emperature with
Power Applied.........................................-55 to 125°C
1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).
(1)
RECOMMENDED OPERA TING COND.
Commercial Devices:
Ambient T emperature (TA) .............................0 to +75°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.75 to +5.25V
Industrial Devices:
Ambient T emperature (TA) ............................-40 to 85°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.50 to +5.50V
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL P ARAMETER CONDITION MIN. TYP.4MAX. UNITS
VIL Input Low Voltage Vss – 0.5 — 0.8 V
VIH Input High Voltage 2.0 — Vcc+1 V
IIL Input or I/O Low Leakage Current
SDI Low Leakage Current
2
1
0V ≤ VIN ≤ VIL (MAX.) — — –100 µA
0V ≤ VIN ≤ VIL (MAX.) — — 250 µA
IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC ——10µA
SDI High Leakage Current
2
VIN = VOH (MIN.) — — 1 mA
VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V
VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V
IOL Low Level Output Current — — 16 mA
IOH High Level Output Current — — –3.2 mA
3
IOS
Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –30 — –130 mA
COMMERCIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L -7/-10/-15 — 90 140 mA
Supply Current f
toggle = 15MHz Outputs Open
INDUSTRIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L -15 — 90 165 mA
Supply Current f
1) The leakage current is due to the internal pull-up on all pins (except SDI on ispGAL22V10C). See Input Buffer section for
more information.
2) The leakage current is due to the internal pull-down on the SDI pin (ispGAL22V10C only). See Input Buffer section for more
information.
3) One output at a time for a maximum duration of one second. V out = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
4) T ypical values are at Vcc = 5V and TA = 25 °C
toggle = 15MHz Outputs Open
6
Specifications ispGAL22V10C
Specifications ispGAL22V10
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
PARAMETER UNITS
TEST
COND.
DESCRIPTION
1
tpd A Input or I/O to Combinatorial Output — 7.5 — 10 — 15 ns
tco A Clock to Output Delay — 5 — 7 — 8 ns
2
tcf
— Clock to Feedback Delay — 2.5 — 2.5 — 2.5 ns
-7
MIN. MAX.
ispGAL22V10B
COM COM/INDCOM
-10
MIN. MAX.
-15
MIN. MAX.
tsu
tsu
1
2
— Setup Time, Input or Feedback before Clock↑ 6.5 — 7 10 — ns
— Setup Time, SP before Clock↑ 10 — 10 — 10 — ns
th — Hold Time, Input or Feedback after Clock↑ 0—0—0— ns
A Maximum Clock Frequency with 87 — 71.4 — 55.5 — MHz
External Feedback, 1/(tsu + tco)
3
fmax
A Maximum Clock Frequency with 1 11 — 105 — 80 — MHz
Internal Feedback, 1/(tsu + tcf)
A Maximum Clock Frequency with 1 11 — 105 — 83.3 — MHz
No Feedback
twh — Clock Pulse Duration, High 4 — 4 — 6 — ns
twl — Clock Pulse Duration, Low 4 — 4 — 6 — ns
ten B Input or I/O to Output Enabled — 8 — 10 — 15 ns
tdis C Input or I/O to Output Disabled — 8 — 10 — 15 ns
tar A Input or I/O to Asynchronous Reset of Register — 13 — 13 — 20 ns
tarw — Asynchronous Reset Pulse Duration 8 — 8 — 15 — ns
tarr — Asynchronous Reset to Clock Recovery Time 8 — 8 — 10 — ns
tspr — Synchronous Preset to Clock Recovery Time 10 — 10 — 10 — ns
1) Refer to Switching T est Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
CAP ACITANCE (TA = 25°C, f = 1.0 MHz)
SYMBOL P ARAMETER MAXIMUM* UNITS TEST CONDITIONS
C
I
C
I/O
*Characterized but not 100% tested.
Input Capacitance 8 pF VCC = 5.0V , VI = 2.0V
I/O Capacitance 8 pF VCC = 5.0V , V
7
= 2.0V
I/O
SWITCHING W AVEFORMS
INPUT or
I/O FEEDBACK
REGISTERED
OUTPUT
CLK
VALID INPUT
t
su
t
co
t
h
(external fdbk)
1/ fmax
REGISTERED
OUTPUT
CLK
t
arw
t
arr
INPUT or
I/O FEEDBACK
DRIVING AR
t
ar
Specifications ispGAL22V10
INPUT or
I/O FEEDBACK
COMBINATORIAL
OUTPUT
Combinatorial Output
INPUT or
I/O FEEDBACK
t
dis
OUTPUT
Input or I/O to Output Enable/Disable
t
wh
CLK
VALID INPUT
t
pd
t
en
t
wl
CLK
REGISTERED
FEEDBACK
Registered Output
1/ fmax (intern al fdbk )
t
cf
fmax with Feedback
t
su
INPUT or
I/O FEEDBACK
DRIVING SP
CLK
REGISTERED
OUTPUT
1/
f
(w/o fdbk)
Clock Width
t
su
Synchronous Preset
max
t
t
h
spr
t
co
Asynchronous Reset
8
fmax DESCRIPTIONS
Specifications ispGAL22V10
CLK
CLK
LOGIC
ARRAY
t
su
REGISTER
t
co
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
CLK
LOGIC
ARRAY
t
su + th
REGISTER
fmax with No Feedback
Note: fmax with no feedback may be less
than 1/twh + twl. This is to allow for a clock
duty cycle of other than 50%.
LOGIC
ARRAY
REGISTER
t
cf
t
pd
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combinatorial output is equal to tcf + tpd.
SWITCHING TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise and Fall Times 3ns 10% – 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See Figure
3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (see figure)
Test Condition R
A 300Ω 390Ω 50pF
B Active High ∞ 390Ω 50pF
Active Low 300Ω 390Ω 50pF
C Active High ∞ 390Ω 5pF
Active Low 300Ω 390Ω 5pF
1 R2 CL
+5V
R
1
FROM OUTPUT (O/Q)
UNDER TEST
R
2
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
*C
L
C *
L
TEST POINT
9
Specifications ispGAL22V10
ELECTRONIC SIGNATURE
An electronic signature (ES) is provided in every ispGAL22V10
device. It contains 64 bits of reprogrammable memory that can
contain user-defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the
security cell.
The electronic signature is an additional feature not present in
other manufacturers' 22V10 devices. To use the extra feature of
the user-programmable electronic signature it is necessary to
choose a Lattice Semiconductor 22V10 device type when
compiling a set of logic equations. In addition, many device
programmers have two separate selections for the device,
typically an ispGAL22V10 and a ispGAL22V10-UES (UES =
User Electronic Signature) or ispGAL22V10-ES. This allows
users to maintain compatibility with existing 22V10 designs,
while still having the option to use the GAL device's extra
feature.
The JEDEC map for the ispGAL22V10 contains the 64 extra
fuses for the electronic signature, for a total of 5892 fuses.
However, the ispGAL22V10 device can still be programmed
with a standard 22V10 JEDEC map (5828 fuses) with any
qualified device programmer.
SECURITY CELL
A security cell is provided in every ispGAL22V10 device to
prevent unauthorized copying of the array patterns. Once
programmed, this cell prevents further read access to the
functional bits in the device. This cell can only be erased by reprogramming the device, so the original configuration can never
be examined once this cell is programmed. The Electronic
Signature is always available to the user, regardless of the state
of this control cell.
LATCH-UP PROTECTION
ispGAL22V10 devices are designed with an on-board charge
pump to negatively bias the substrate. The negative bias is of
sufficient magnitude to prevent input undershoots from causing
the circuitry to latch. Additionally, outputs are designed with nchannel pullups instead of the traditional p-channel pullups to
eliminate any possibility of SCR induced latching.
DEVICE PROGRAMMING
The ispGAL22V10 device uses a standard 22V10 JEDEC
fusemap file to describe the device programming information.
Any third party logic compiler can produce the JEDEC file for this
device.
IN-SYSTEM PROGRAMMABILITY
The ispGAL22V10 device features In-System Programmable
technology. By integrating all the high voltage programming
circuitry on-chip, programming can be accomplished by simply
shifting data into the device. Once the function is programmed,
the non-volatile E2CMOS cells will not lose the pattern even
when the power is turned off.
All necessary programming is done via four TTL level logic
interface signals. These four signals are fed into the on-chip
programming circuitry where a state machine controls the programming. The interface signals are Serial Data In (SDI), Serial
Data Out (SDO), Serial Clock (SCLK) and Mode (MODE)
control. For details on the operation of the internal state machine
and programming of ispGAL22V10 devices please refer to the
ISP Architecture and Programming section in this Data Book.
OUTPUT REGISTER PRELOAD
When testing state machine designs, all possible states and
state transitions must be verified in the design, not just those
required in the normal machine operations. This is because
certain events may occur during system operation that throw the
logic into an illegal state (power-up, line voltage glitches, brownouts, etc.). To test a design for proper treatment of these
conditions, a way must be provided to break the feedback paths,
and force any desired (i.e., illegal) state into the registers. Then
the machine can be sequenced and the outputs tested for
correct next state conditions.
The ispGAL22V10 device includes circuitry that allows each
registered output to be synchronously set either high or low.
Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of
executing test vectors perform output register preload automatically.
INPUT BUFFERS
ispGAL22V10 devices are designed with TTL level compatible
input buffers. These buffers have a characteristically high
impedance, and present a much lighter load to the driving logic
than bipolar TTL devices.
All input and I/O pins (except SDI on the ispGAL22V10C) also
have built-in active pull-ups. As a result, floating inputs will float
to a TTL high (logic 1). The SDI pin on the ispGAL22V10C has
a built-in pull-down to keep the device out of the programming
state if the pin is not actively driven. However, Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins
be connected to an adjacent active input, Vcc, or ground. Doing
so will tend to improve noise immunity and reduce Icc for the
device. (See equivalent input and I/O schematics on the following page.)
0
-20
-40
Input Current (µA)
-60
0
T ypical Input Current
1.0 2.0 3.0 4.0 5.0
Input Voltage (Volts)
10
POWER-UP RESET
Specifications ispGAL22V10
Vcc
CLK
INTERNAL REGISTER
Q - OUTPUT
ACTIVE LOW
OUTPUT REGISTER
ACTIVE HIGH
OUTPUT REGISTER
Vcc (min.)
Circuitry within the ispGAL22V10 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1µ s MAX). As a result, the
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the
t
su
t
wl
pr
t
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
Device Pin
Reset to Logic "0"
asynchronous nature of system power-up, some conditions must
be met to provide a valid power-up reset of the ispGAL22V10.
First, the Vcc rise must be monotonic. Second, the clock input
must be at static TTL level as shown in the diagram during power
up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and
feedback path setup times have been met. The clock must also
meet the minimum pulse width requirements.
INPUT/OUTPUT EQUIVALENT SCHEMA TICS
PIN
(Vref Typical = 3.2V)
Vcc
Vcc
PIN
Active Pull-up
Circuit (Except SDI
on ispGAL22V10C)
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
Vref
Pull-down Resistor
(SDI on ispGAL22V10C Only)
Input
Data
Output
Feedback
Tri-State
Control
Active Pull-up
Circuit
Vcc
Feedback
(To Input Buffer)
Output
Vref
PIN
(Vref Typical = 3.2V)
PIN
11
Specifications ispGAL22V10
ispGAL22V10C: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
1.2
1.1
1
0.9
Normalized Tpd
0.8
4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Normalized Tpd vs Temp
1.3
1.2
1.1
1
0.9
Normalized Tpd
0.8
0.7
-55 -25 0 2 5 50 75 100 1 25
Temperature (deg. C)
Normalized Tco vs Vcc
1.2
1.1
1
0.9
Normalized Tco
0.8
4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Normalized Tco vs Temp
1.3
1.2
1.1
1
0.9
Normalized Tco
0.8
0.7
-55 -25 0 2 5 50 7 5 100 125
Temperature (deg. C)
Normalized Tsu vs Vcc
1.2
1.1
1
0.9
Normalized Tsu
0.8
4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Normalized Tsu vs Temp
1.4
1.3
1.2
1.1
1
0.9
Normalized Tsu
0.8
0.7
-55 -25 0 25 50 7 5 100 125
Temperature (deg. C)
Delta Tpd vs # of Outputs
Switching
0
-0.25
-0.5
-0.75
Delta Tpd (ns)
-1
12345678910
Number of Outputs Switching
Delta Tpd vs Output Loading
10
8
6
4
2
Delta Tpd(ns)
0
-2
0 50 100 150 200 250 300
RISE
FALL
Ouput Loading (pF)
Delta Tco vs # of Outputs
Switching
0
-0.25
-0.5
-0.75
Delta Tco (ns)
-1
12345678910
Number of Outputs Switching
Delta Tco vs Output Loading
12
10
8
6
4
2
Delta Tco (ns)
0
-2
0 50 100 150 200 250 300
RISE
FALL
Output Loading (pF)
12
Specifications ispGAL22V10
ispGAL22V10C: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
3
2.5
2
1.5
Vol (V)
1
0.5
0
0.00 20.00 40.00 60.00 80.00 100.00
Iol (mA)
Normalized Icc vs Vcc
1.2
1.1
1
0.9
Normalized Icc
0.8
4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Voh vs Ioh
5
4
3
2
Voh (V)
1
0
0.00 10.00 20.00 30.00 40.00 50.00 60.00
Ioh(mA)
Normalized Icc vs Temp
1.3
1.2
1.1
1
0.9
Normalized Icc
0.8
0.7
-55 -25 0 25 50 75 100 125
Temperature (deg. C)
Voh vs Ioh
4.5
4.25
4
Voh (V)
3.75
3.5
0.00 1.00 2.00 3.00 4.00
Ioh(mA)
Normalized Icc vs Freq.
1.20
1.10
1.00
0.90
Normalized Icc
0.80
0 255075100
Frequency (MHz)
Delta Icc vs Vcc
5
4
3
2
Delta Icc (mA)
1
0
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Vin (V)
Input Clamp (Vik)
0
10
20
30
40
50
60
Iik (mA)
70
80
90
100
-2.00 -1.50 -1.00 -0.50 0.00
Vik (V)
13
Specifications ispGAL22V10
Notes
14
Copyright © 1997 Lattice Semiconductor Corporation.
E2CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, Lattice Semiconductor, L (stylized) Lattice
Semiconductor Corp., L (stylized) and Lattice (design) are registered trademarks of Lattice Semiconductor Corporation.
Generic Array Logic, ISP, ispATE, ispCODE, ispDOWNLOAD, ispDS, ispDS+, ispGDS, ispGDX, ispHDL, ispJTAG, ispStarter,
ispSTREAM, ispTEST, ispTURBO, ispVECTOR, ispVerilog, ispVHDL, Latch-Lock, LHDL, pDS+, RFT, Total ISP and Twin
GLB are trademarks of Lattice Semiconductor Corporation. ISP is a service mark of Lattice Semiconductor Corporation. All
brand names or product names mentioned are trademarks or registered trademarks of their respective holders.
Lattice Semiconductor Corporation (LSC) products are made under one or more of the following U.S. and international
patents: 4,761,768 US, 4,766,569 US, 4,833,646 US, 4,852,044 US, 4,855,954 US, 4,879,688 US, 4,887,239 US, 4,896,296
US, 5,130,574 US, 5,138,198 US, 5,162,679 US, 5,191,243 US, 5,204,556 US, 5,231,315 US, 5,231,316 US, 5,237,218 US,
5,245,226 US, 5,251,169 US, 5,272,666 US, 5,281,906 US, 5,295,095 US, 5,329,179 US, 5,331,590 US, 5,336,951 US,
5,353,246 US, 5,357,156 US, 5,359,573 US, 5,394,033 US, 5,394,037 US, 5,404,055 US, 5,418,390 US, 5,493,205 US,
0194091 EP, 0196771B1 EP, 0267271 EP, 0196771 UK, 0194091 GB, 0196771 WG, P3686070.0-08 WG. LSC does not
represent that products described herein are free from patent infringement or from any third-party right.
The specifications and information herein are subject to change without notice. Lattice Semiconductor Corporation (LSC)
reserves the right to discontinue any product or service without notice and assumes no obligation to correct any errors
contained herein or to advise any user of this document of any correction if such be made. LSC recommends its customers
obtain the latest version of the relevant information to establish, before ordering, that the information being relied upon is
current.
LSC warrants performance of its products to current and applicable specifications in accordance with LSC’s standard
warranty. Testing and other quality control procedures are performed to the extent LSC deems necessary. Specific testing of
all parameters of each product is not necessarily performed, unless mandated by government requirements.
LSC assumes no liability for applications assistance, customer’s product design, software performance, or infringements of
patents or services arising from the use of the products and services described herein.
LSC products are not authorized for use in life-support applications, devices or systems. Inclusion of LSC products in such
applications is prohibited.
LATTICE SEMICONDUCTOR CORPORATION
5555 Northeast Moore Court
Hillsboro, Oregon 97124 U.S.A.
Tel.: (503) 681-0118
FAX: (503) 681-3037
http://www.latticesemi.com July 1997
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