Lattice GAL20V8 User Manual
GAL20V8
1
12
13
24
I/CLK
I
I
I
I
I
I
I
I
I
I
GND
Vcc
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/OE
6
18
CLK
I
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I
I
I
I
I
I
I
I
I
I/OE
I/CLK
OE
8
8
8
8
8
8
8
8
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
IMUX
IMUX
PROGRAMMABLE
AND-ARRAY
(64 X 40)
OLMC
High Performance E2CMOS PLD
Generic Array Logic™
Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 5 ns Maximum Propagation Delay
— Fmax = 166 MHz
— 4 ns Maximum from Clock Input to Data Output
— UltraMOS
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
— 75mA Typ Icc on Low Power Device
— 45mA T yp Icc on Quarter Power Device
• ACTIVE PULL-UPS ON ALL PINS
2
CELL TECHNOLOGY
• E
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Y ields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Also Emulates 24-pin PAL
Fuse Map/Parametric Compatibility
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNA TURE FOR IDENTIFICATION
®
Advanced CMOS Technology
®
Devices with Full Function/
Functional Block Diagram
Description
The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Eras-
2
able (E
) floating gate technology to provide the highest speed
performance available in the PLD market. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configurations possible with the GAL20V8 are the P AL
in the table of the macrocell description section. GAL20V8 devices
are capable of emulating any of these PAL architectures with full
function/fuse map/parametric compatibility .
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2000
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
20v8_04
architectures listed
Pin Configuration
PLCC
I/CLK
I
4
5
I
I
I
7
NC
I
9
I
I
11
12 14 16 18
I
1
NC
I
228
GAL20V8
T op View
I
NC
GND
Vcc
I/OE
DIP
I/O/Q
I
26
25
I/O/Q
I/O/Q
23
I/O/Q
NC
21
I/O/Q
I/O/Q
19
I/O/Q
I
I/O/Q
GAL
20V8
GAL20V8 Ordering Information
Commercial Grade Specifications
)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP
534 511JL5-C8V02LAGCCLPdaeL-82
5.775 511
511PL7-B8V02LAGPIDcitsalPniP-42
511JL7-B8V02LAGCCLPdaeL-82
01017 511
511PL01-B8V02LAGPIDcitsalPniP-42
511JL01-B8V02LAGCCLPdaeL-82
51210155PQ51-B8V02LAGPIDcitsalPniP-42
55JQ51-B8V02LAGCCLPdaeL-82
09PL51-B8V02LAGPIDcitsalPniP-42
09JL51-B8V02LAGCCLPdaeL-82
52512155PQ52-B8V02LAGPIDcitsalPniP-42
55JQ52-B8V02LAGCCLPdaeL-82
09PL52-B8V02LAGPIDcitsalPniP-42
09JL52-B8V02LAGCCLPdaeL-82
8V02LAGCJL7-
8V02LAGCJL01-
Specifications GAL20V8
CCLPdaeL-82
CCLPdaeL-82
Industrial Grade Specifications
)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP
01017 031
031IPL01-B8V02LAGPIDcitsalPniP-42
031IJL01-B8V02LAGCCLPdaeL-82
512101031IPL51-B8V02LAGPIDcitsalPniP-42
031IJL51-B8V02LAGCCLPdaeL-82
02311156IPQ02-B8V02LAGPIDcitsalPniP-42
56IJQ02-B8V02LAGCCLPdaeL-82
52512156IPQ52-B8V02LAGPIDcitsalPniP-42
56IJQ52-B8V02LAGCCLPdaeL-82
031IPL52-B8V02LAGPIDcitsalPniP-42
031IJL52-B8V02LAGCCLPdaeL-82
8V02LAGCIJL01-
Part Number Description
_
GAL20V8C
GAL20V8B
XXXXXXXX XX X X X
Device Name
CCLPdaeL-82
Speed (ns)
Q = Quarter Power
Grade
Blank = Commercial
I = Industrial
PowerL = Low Power
Package
P = Plastic DIP
J = PLCC
2
Output Logic Macrocell (OLMC)
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user.
There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
is illustrated in the following pages. T wo global bits, SYN and AC0,
control the mode configuration for all macrocells. The XOR bit of
each macrocell controls the polarity of the output in any of the three
modes, while the AC1 bit of each of the macrocells controls the input/output configuration. These two global and 16 individual architecture bits define all possible configurations in a GAL20V8 . The
information given on these architecture bits is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the user
should not need to directly manipulate these architecture bits.
The following is a list of the PAL architectures that the GAL20V8
can emulate. It also shows the OLMC mode under which the
devices emulate the PAL architecture.
Specifications GAL20V8
PAL Architectures GAL20V8
Emulated by GAL20V8 Global OLMC Mode
20R8 Registered
20R6 Registered
20R4 Registered
20RP8 Registered
20RP6 Registered
20RP4 Registered
20L8 Complex
20H8 Complex
20P8 Complex
14L8 Simple
16L6 Simple
18L4 Simple
20L2 Simple
14H8 Simple
16H6 Simple
18H4 Simple
20H2 Simple
14P8 Simple
16P6 Simple
18P4 Simple
20P2 Simple
Compiler Support for OLMC
Software compilers support the three different global OLMC modes
as different device types. These device types are listed in the table
below. Most compilers have the ability to automatically select the
device type, generally based on the register usage and output
enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with
OE controlled by the product term will force the software to choose
the complex mode. The software will choose the simple mode only
when all outputs are dedicated combinatorial without OE control.
The different device types listed in the table can be used to override
the automatic device selection by the software. For further details,
refer to the compiler software manuals.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 1 and pin 13 (DIP pinout) are permanently
Registered Complex Simple Auto Mode Select
ABEL P20V8R P20V8C P20V8AS P20V8
CUPL G20V8MS G20V8MA G20V8AS G20V8
LOG/iC GAL20V8_R GAL20V8_C7 GAL20V8_C8 GAL20V8
OrCAD-PLD "Registered"
PLDesigner P20V8R
1
2
"Complex"
P20V8C
TANGO-PLD G20V8R G20V8C G20V8AS
configured as clock and output enable, respectively . These pins
cannot be configured as dedicated inputs in the registered mode.
In complex mode pin 1 and pin 13 become dedicated inputs and
use the feedback paths of pin 22 and pin 15 respectively . Because
of this feedback path usage, pin 22 and pin 15 do not have the
feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
18 and 19) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
1
2
"Simple"
P20V8C
1
2
3
GAL20V8A
P20V8A
G20V8
1) Used with Configuration keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.
3
Registered Mode
Specifications GAL20V8
In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.
Architecture configurations available in this mode are similar to the
common 20R8 and 20RP4 devices with various permutations of
polarity , I/O and register placement.
All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/Os are possible in this mode.
CLK
DQ
XOR
OE
Q
Dedicated input or output functions can be implemented as subsets of the I/O function.
Registered outputs have eight product terms per output. I/Os have
seven product terms per output.
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product T erm Disable (PTD) fuses, are shown
on the logic diagram on the following page.
Registered Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 13 controls common OE for the registered outputs.
- Pin 1 & Pin 13 are permanently configured as CLK &
OE for registered output configuration.
Combinatorial Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
- Pin 1 & Pin 13 are permanently configured as CLK &
OE for registered output configuration..
4
Registered Mode Logic Diagram
Specifications GAL20V8
DIP (PLCC) Package Pinouts
1(2)
2(3)
3(4)
4(5)
5(6)
6(7)
7(9)
0000
0280
0320
0600
0640
0920
0960
1240
1280
1560
28
24
201612840
32
2640
36
PTD
23(27)
OLMC
22(26)
XOR-2560
AC1-2632
OLMC
21(25)
XOR-2561
AC1-2633
OLMC
XOR-2562
AC1-2634
OLMC
XOR-2563
AC1-2635
OLMC
XOR-2564
AC1-2636
20(24)
19(23)
18(21)
8(10)
9(11)
10(12)
11(13)
1600
1880
1920
2200
2240
2520
2703
OLMC
XOR-2565
AC1-2637
OLMC
XOR-2566
AC1-2638
OLMC
XOR-2567
AC1-2639
SYN-2704
AC0-2705
OE
17(20)
16(19)
15(18)
14(17)
13(16)
5
Complex Mode
Specifications GAL20V8
In the Complex mode, macrocells are configured as output only or
I/O functions.
Architecture configurations available in this mode are similar to the
common 20L8 and 20P8 devices with programmable polarity in
each macrocell.
Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 15 & 22) do not have input capability . De-
XOR
signs requiring eight I/Os can be implemented in the Registered
mode.
All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1 and
13 are always available as data inputs into the AND array.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
Combinatorial I/O Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 16 through Pin 21 are configured to this function.
Combinatorial Output Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 15 and Pin 22 are configured to this function.
6
Complex Mode Logic Diagram
Specifications GAL20V8
DIP (PLCC) Package Pinouts
1(2)
2(3)
3(4)
4(5)
5(6)
6(7)
7(9)
0000
0280
0320
0600
0640
0920
0960
1240
1280
1560
24
32
201612840
28
2640
36
PTD
23(27)
OLMC
XOR-2560
22(26)
AC1-2632
OLMC
21(25)
XOR-2561
AC1-2633
OLMC
20(24)
XOR-2562
AC1-2634
OLMC
19(23)
XOR-2563
AC1-2635
OLMC
18(21)
XOR-2564
AC1-2636
8(10)
9(11)
10(12)
11(13)
1600
1880
1920
2200
2240
2520
2703
OLMC
XOR-2565
AC1-2637
OLMC
XOR-2566
AC1-2638
OLMC
XOR-2567
AC1-2639
SYN-2704
AC0-2705
17(20)
16(19)
15(18)
14(17)
13(16)
7
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