• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 100 MHz
— 6 ns Maximum from Clock Input to Data Output
— TTL Compatible 12 mA Outputs
— UltraMOS
• 50% REDUCTION IN POWER FROM BIPOLAR
— 75mA Typ Icc
• ACTIVE PULL-UPS ON ALL PINS (GAL16V8D-7 and
GAL16V8D-10)
2
CELL TECHNOLOGY
•E
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Y ields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Also Emulates 20-pin PAL
Fuse Map/Parametric Compatibility
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNA TURE FOR IDENTIFICATION
®
Advanced CMOS Technology
®
Devices with Full Function/
Functional Block Diagram
I/CLK
I
I
I
I
I
(64 X 32)
AND-ARRAY
I
I
I
PROGRAMMABLE
8
8
8
8
8
8
8
8
CLK
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
OE
I/OE
Description
Pin Configuration
The GAL16V8/883 is a high performance E2CMOS programmable logic device processed in full compliance to MIL-STD-883.
This military grade device combines a high performance CMOS
process with Electrically Erasable (E
2
) floating gate technology to
LCC
CERDIP
provide the highest speed/power performance available in the
883 qualified PLD market. The GAL16V8D/883, at 7.5ns maximum propagation delay time, is the world's fastest military qualified CMOS PLD.
4
The generic GAL architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL16V8/883 is capable of emulating all
standard 20-pin PAL
metric compatibility.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. Therefore,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write
cycles and data retention in excess of 20 years are specified.
Supply voltage VCC...................................... –0.5 to +7V
Input voltage applied .......................... –2.5 to V
+1.0V
CC
Off-state output voltage applied .........–2.5 to VCC +1.0V
Recommended Operating Conditions
Case T emperature (TC)..............................–55 to 125°C
Supply voltage (V
with Respect to Ground ..................... +4.50 to +5.50V
CC
)
Storage Temperature ................................–65 to 150°C
Case T emperature with
Power Applied........................................–55 to 125°C
1.Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress only ratings and functional operation of the device at these
or at any other conditions above those indicated in the operational
sections of this specification is not implied (while programming,
follow the programming specifications).
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOLPARAMETERCONDITIONMIN.TYP.
3
MAX.UNITS
VILInput Low Voltage Vss – 0.5—0.8V
VIHInput High Voltage2.0—Vcc+1V
1
IIL
Input or I/O Low Leakage Current0V ≤ VIN≤ VIL (MAX.)——–100µA
IIHInput or I/O High Leakage Current3.5V ≤ VIN≤ VCC——10µA
VOLOutput Low VoltageIOL = MAX. Vin = VIL or VIH——0.5V
VOHOutput High VoltageIOH = MAX. Vin = VIL or VIH2.4——V
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 °C
toggle = 15MHz Outputs Open
2
AC Switching Characteristics
Specifications GAL16V8D-7/10/883
Over Recommended Operating Conditions
PARAMETERUNITS
TEST
COND
DESCRIPTION
1
.
-7
MIN. MAX.
-10
MIN. MAX.
tpdAInput or I/O to Combinational Output17.5210ns
tcoAClock to Output Delay1617ns
2
tcf
—Clock to Feedback Delay—6—7ns
tsu—Setup Time, Input or Feedback before Clock↑7—10—ns
th—Hold Time, Input or Feedback after Clock↑0—0—ns
AMaximum Clock Frequency with76.9—58.8—MHz
External Feedback, 1/(tsu + tco)
3
fmax
AMaximum Clock Frequency with76.9—58.8—MHz
Internal Feedback, 1/(tsu + tcf)
AMaximum Clock Frequency with100—62.5—MHz
No Feedback
twh—Clock Pulse Duration, High5—8—ns
twl—Clock Pulse Duration, Low5—8—ns
tenBInput or I/O to Output Enabled19—10ns
BOE to Output Enabled17—10ns
tdisCInput or I/O to Output Disabled19—10ns
COE to Output Disabled17—10ns
1) Refer to Switching T est Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section.
Capacitance (TA = 25°C, f = 1.0 MHz)
SYMBOLPARAMETERMAXIMUM*UNITSTEST CONDITIONS
C
I
C
I/O
*Characterized but not 100% tested.
Input Capacitance10pFVCC = 5.0V , VI = 2.0V
I/O Capacitance10pFVCC = 5.0V , V
= 2.0V
I/O
3
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