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DisplayPort VIP Input Board
User Manual
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Lattice DisplayPort VIP Input Board User Manual

Evaluation Board User Guide
FPGA-EB-02014-1.0
March 2018
DisplayPort VIP Input Board
Contents
Acronyms in This Document ................................................................................................................................................. 3
1. Introduction .................................................................................................................................................................. 4
1.1. Further Information ................................................................................................................................................ 5
2. Functional Description .................................................................................................................................................. 6
2.1. Switches .................................................................................................................................................................. 6
2.2. DisplayPort Interface .............................................................................................................................................. 6
2.3. LVDS Translator ...................................................................................................................................................... 6
2.4. Clock Interface ........................................................................................................................................................ 6
3. High-Speed Headers ..................................................................................................................................................... 7
4. Power Supply ................................................................................................................................................................ 9
5. User LEDs and Headers ............................................................................................................................................... 10
6. Ordering Information .................................................................................................................................................. 11
References .......................................................................................................................................................................... 12
Technical Support Assistance ............................................................................................................................................. 12
Appendix A. DisplayPort VIP Input Board Schematics ........................................................................................................ 13
Appendix B. DisplayPort VIP Input Board Bill of Materials ................................................................................................. 17
Revision History ................................................................................................................................................................... 20
Figures
Figure 1.1. Top View of DisplayPort VIP Input Board ........................................................................................................... 4
Figure 1.2. Bottom View of DisplayPort VIP Input Board ..................................................................................................... 5
Figure 2.1 Functional Block Diagram .................................................................................................................................... 6
Figure 4.1 Power Supply ....................................................................................................................................................... 9
Figure A.1. Block Diagram ................................................................................................................................................... 13
Figure A.2. DP Redriver and Connector I/F ......................................................................................................................... 14
Figure A.3. Power, Debug LED, Header I/F ......................................................................................................................... 15
Figure A.4. Clock Synthesizer .............................................................................................................................................. 16
Tables
Table 3.1. Connector J1 ........................................................................................................................................................ 7
Table 3.2. Connector J2 ........................................................................................................................................................ 8
Table 5.1 User LEDs............................................................................................................................................................. 10
Table 8.1. Reference Part Number ..................................................................................................................................... 11
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-EB-02014-1.0
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
DisplayPort VIP Input Board
Acronym
Definition
DP
DisplayPort
I2C
Inter-Integrated Circuit
LDO
Low Dropout
LED
Light-emitting Diode
LVDS
Low-Voltage Differential Signaling
mDP
Mini DisplayPort
SPI
Serial Peripheral Interface
VIP
Video Interface Platform
Evaluation Board User Guide
Acronyms in This Document
A list of acronyms used in this document.
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
FPGA-EB-02014-1.0 3
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
User LEDs
Mini DisplayPort
Connector
SN75DP130
SN65MLVD200
3.3 V Power to mDP (Not populated)
SI5342B Clock
Synthesizer
(Not Populated)
User Headers
System Reset
Evaluation Board User Guide
1. Introduction
This document describes the Lattice Semiconductor DisplayPort® VIP Input Board. This board is designed to work with the Lattice Video Interface Platform (VIP) board interconnect system.
This user guide includes descriptions of board components, schematics, and bill of materials.
Key features of the DisplayPort VIP Input Board include:
Integrated Texas Instruments SN75DP130 DisplayPort 1:1 Redriver Mini DisplayPort (mDP) connector Two 60-pin Rugged High-Speed Headers
Figure 1.1 shows the top view of the DisplayPort VIP Input Board and its key components. Figure 1.2 shows the bottom
view of the board.
Figure 1.1. Top View of DisplayPort VIP Input Board
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-EB-02014-1.0
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
DisplayPort VIP Input Board
Upstream Connector (J1)
Upstream Connector (J2)
Evaluation Board User Guide
Figure 1.2. Bottom View of DisplayPort VIP Input Board
1.1. Further Information
The following references provide detailed information on the DisplayPort VIP Input Board:
Appendix A. DisplayPort VIP Input Board Schematics Appendix B. DisplayPort VIP Input Board Bill of Materials For more information on boards and kits available for the VIP (Video Interface Platform) system visit
www.latticesemi.com/boards
For details on the Texas Instruments SN75DP130, visit the Texas Instruments website at www.ti.com
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
FPGA-EB-02014-1.0 5
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SN75DP130
U1
mDP
Connector
CN1
J1
DisplayPort Main Link
(4 lanes)
Aux Channel
HPD/CAD/Control
DisplayPort Main Link
(4 lanes)
Aux Channel
HPD/CAD/Control
Evaluation Board User Guide
2. Functional Description
The DisplayPort VIP Input Board receives up to 4-lanes of DisplayPort video from the Mini DisplayPort Connector. The DisplayPort Main Link, Control and Aux Channel are sent through the TI DisplayPort redriver, which regenerates the DisplayPort high-speed digital link to connector J1.
Figure 2.1 Functional Block Diagram
2.1. Switches
The push button switch, SW1, controls the reset signal RESET. Pressing SW1 provides logic 0 to the SN75DP130 RSTN pin. RESET is connected to GSRN on connecter J1, allowing SW1 to control the reset signal for other connected boards.
2.2. DisplayPort Interface
The mini DisplayPort connector, CN1, connects the DisplayPort VIP Input Board to a DisplayPort sink. If PWR Out is required on Pin 20, the user must populate the 3.3 V Low Dropout (LDO) regulator, U4, and short jumper J4.
2.3. LVDS Translator
The SN65MLV200 LVDS (Low-Voltage Differential Signaling) Driver/Receiver, U2, can be used to translate the LVDS AUX Channel to single ended I/O. This can be used if the downstream processor board is unable to receive LVDS. The single ended I/O are routed to connector J2.
2.4. Clock Interface
The DisplayPort VIP Input Board provides the ability to add advanced clock circuitry, allowing the user to provide a fine tunable reference clock to the downstream board. This is done by populating U17 with a Silicon Labs Si5342B, High Performance Jitter Attenuator Clock Multiplier. The device can be programmed from the downstream connector using an I2C (Inter Integrated Circuit) or SPI (Serial Peripheral Interface) interface.
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-EB-02014-1.0
DisplayPort VIP Input Board
J1 Connector Pin
Signal Name
SN75DP130 pin
Description
1
3.3V — —
2
5V — — 3 3.3V — — 4 5V — — 5 GND — —
6
5V — —
7
LVDS_P
—
LVDS Reference Clock from Si5342
8
GND — — 9 LVDS_N
—
LVDS Reference Clock from Si5342
11
GND — —
13
AUX_P
AUX_SRCp
DisplayPort Auxiliary Data Channel
14
GND — —
15
AUX_N
AUX_SRCn
DisplayPort Auxiliary Data Channel
17
GND — —
20
GND — —
22
2.5V — —
23
GND — —
24
2.5V — —
25
GND — —
26
GND — —
28
RESET
RSTN
Global System Reset
30
HPD_SINK
HPD_SINK
Hot Plug Detect
32
CAD_SINK
CAD_SINK
DP Cable Adapter Detect
34
GND — —
36
RXP0_D1CH0
OUT2p
DisplayPort Main Link Lane 0
38
RXN0_D1CH0
OUT2n
DisplayPort Main Link Lane 0
40
GND — —
41
SCL_CTL
SCL_CTL
I2C Interface to SN75DP130
42
RXP0_D1CH1
OUT3p
DisplayPort Main Link Lane 1
43
SDA_CTL
SDA_CTL
I2C Interface to SN75DP130
44
RXN0_D1CH1
OUT3n
DisplayPort Main Link Lane 1
46
GND — —
48
RXP0_D0CH0
OUT0p
DisplayPort Main Link Lane 0
50
RXN0_D0CH0
OUT0n
DisplayPort Main Link Lane 0
52
GND — —
54
RXP0_D0CH1
OUT1p
DisplayPort Main Link Lane 1
55
GND — —
56
RXN0_D0CH1
OUT1n
DisplayPort Main Link Lane 1
57
GND — —
58
GND — —
59
GND — —
10, 12, 60, 16, 18, 19, 21, 27, 29, 31, 33, 35, 37, 39, 45, 47, 49, 51, 53
Not Connected
—
—
Evaluation Board User Guide
3. High-Speed Headers
The two 60-pin high-speed headers, connectors J1 and J2, are used to connect to a downstream host processor board.
Table 3.1. Connector J1
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
FPGA-EB-02014-1.0 7
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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