Larcan TTS250MV User Manual

GENERAL DESCRIPTION

OVERVIEW

The LARCAN model TTS250M solid-state VHF translator has been designed to
operate conservatively at 250W peak sync visual power, and 25W average aural power.
The translator is completely housed in a 52” high cabinet using standard 19” EIA panels.

The translator is designed for operation from nominal 230V single phase 60Hz
power. Transformer taps are provided to adjust the amplifier power supply for on-site
nominal voltages between 200V and 240V.

AMPLIFIER

The amplifier design is similar to that employed in LARCAN’s high power model
‘M’ series transmitters. The RF amplifier is located in a self-contained slide out drawer.
The power output stage use a pair of dual FET RF power transistors operating Class
‘AB’. Strip line power splitters and combiners are used at the input and output
respectively.

Cooling is provided by a squirrel cage type blower mounted on the rear of the
slide out drawer. Air is drawn through a filter in the rear door of the cabinet, blown
through the amplifier heatsink and exhausted through a grill at the front of the amplifier.
No provision is made for ducting exhaust air.

Metering is provided for voltage, current and RF power. The amplifier is VSWR
protected with an automatic cutback circuit.

The power supply is a conventional linear design, with regulators located in the
amplifier drawer.

All individual assemblies are modular in design, and easy to access for
maintenance and testing. Full interlocking and telemetry facilities are provided.

CIRCUIT DESCRIPTION AND SET UP PROCEDURE
PRE-CORRECTION

The pre-correction circuit used by the amplifier has been set up at the factory and
should not require re-adjustment. Technical personnel should be aware that any
adjustments performed on these circuits should be slight and may have to be repeated
until the desired correction is achieved.

Pre-corrector

The Pre-correction board comprises three separate sections: an input attenuator, a
phase corrector and an output amplifier. The input attenuator is made up of R1 through
R3. The adjustable phase corrector comprises L1, CR1, and R4. U1 is an amplifier IC
and receives power from voltage regulator U2. The amount of correction is controlled by
the adjustment of L1. Typically the adjustment is set to correct for the amount of
differential phase introduced by the PA stages and this should correspond to
approximately unity gain through the Pre-correction board.

Linearity Corrector

The Linearity Corrector board provides a slight amount of linearity correction
needed for intermodulation distortion in the PA stages. R2 and C2 control the amount of
correction by allowing the signal to be shunted to ground by diodes CR1 and CR2. A
higher level signal will cause the diodes to conduc t more, shunting more signal to ground.
R3 acts as a fine control by varying the bias on CR1 and CR2 through emitter follower
Q1.

IPA MODULE
CIRCUIT DESCRIPTION

The amplifier consists of two stages of amplification, a linear hybrid IC and a
transistor power stage. Both stages are biased for Class A operation and each has its own
set of three terminal regulators for voltage or current regulation.

The signal is first applied to a form of variable attenuator consisting of R2, R6
and R12. The first sta ge of amplification is a CA2842 hybrid IC; this amplifier provides
approximately 22dB of gain. A coaxial cable jumper is provided between this stage and
the next to allow for troubleshooting.

The second stage of amplification is a Class A biased MRF325 transistor
amplifier. The input section consists of an attenuator/matching network to transform the
50ohm impedance to values needed for optimum transistor performance. Similarly, a
matching network at the output of the transistor provides the impedance match to the
50ohm output. C6 and C19 are DC blocking capacitors at the input and output of the
amplifier respectively.

DC power to the hybrid stage is provided by a three terminal voltage regulator IC
(VR1). This serves to remove hum from the power supply as well as provide an
interlocking circuit for other applications. This interlocking function is not used in the
250W amplifier application and thus E2 should have a jumper to ground. The DC power
to the output stage is also provided by a three terminal voltage regulator. VR2 is
configured as a 1.5A constant current source. The current is set by the voltage drop

across R11. The zener diode VR3 will conduct at approximately 22V and forward bias
the transistor.

Set up Procedure

• Set up a power sup ply to 30V; current limited to 3.5A.

• Connect the power supply to E1 of the IPA. The current drawn should be

approximately 1.75A.

• Remove the coax jumper.

• Apply a sweep signal to the preamplifier input, being careful not to

overdrive the test equipment. The gain should be at least 18dB to 20dB
and the return loss better than 15dB in the frequency range of interest.

• Connect a 30dB attenuator to the output of the amplifier.

• Apply a low level sweep to the amplifier and measure the gain (be sure to

take into account the 30dB pad). Gain should be about 13dB to 14dB.

POWER AMPLIFIER MODULE

CIRCUIT DESCRIPTION

The PA modules used in the 250W amplifier employ dual FET RF transistor
packages in push-pull configuration. The transistors operate Class AB and are b iased for

0.6A static drain current per transistor.

The input to the PA module is applied at J1 from the power splitter board.
Transformer T1 divides the input into two equal and opposite signals. Capacitors C3, C4
and the associated strip line circuit ry form an impedance matching network to the gates
of the FETs. C1 and C2 are DC isolation (blocking) capacitors. Capacitors C13 and C16
and associated strip line inductors form an output impedance matching network and T2
combines the out of phase signals at the output J2. C14 and C15 also act as blocking
capacitors.

The 50V DC supply is connected to each drain through the 5A fuses and
decoupling inductors L4 and L5. Two resistive divider networks comprising R1 through
R10 apply gate bias voltage to the FETs to set the static drain current. Zener diodes CR1
and CR2 provide a constant voltage source +20V for the bias voltage adjustment. The
FET gate bias required for the recommended 0.6A of quiescent drain current may be
anywhere between 2V and 5V depending on the individual FET. Capacitors C6, C7, C9
through C12, C17 and C18 are RF bypass capacitors.

Set up Procedure

• Set up a 50V power supply; current limited to 1.2A.

• Turn both bias potentiometers for maximum resistance.

• Apply the supply to the one transistor at a time (one-half package) and

adjust the corresponding bias resistor for 0.6A drain current. This setting

is a starting value. It will be re-adjusted during test for minimum
intermods and FM noise.

• Connect a 30dB, 20W attenuator to the o utput of the amplifier.

• Apply B+ to both supply connections of the amplifier module.

• Apply a low level sweep to the module and measure the gain (be sure to

take into account the 30dB pad). Gain should be about 21dB to 24dB.

VOLTAGE REGULATOR BOARD

CIRCUIT DESCRIPTION

The Voltage Regulator board comprises two identical regulator circuits. One is

described below; the description for the second is the same except for the component
numbers.

The voltage regulated is based on a monolithic regulator IC MC1723CP and a
pass transistor for current handling capability. The regulator IC compares a sample of the
output voltage to an on-chip reference. The sample is applied to pin 4 through a resistive
divider consisting of R7, R9 and R11. Varying R7 changes this sample thus changing the
output voltage. The output of the IC (pin 10) drives the PNP transistor U2 through a
Darlington transistor Q3.

Short circuit protection is provided by Q1 and Q4. Q4 shunts the drive away from
the base of U2 when the output current causes the voltage across R6 and R10 to rise high
enough to open transistor Q1. Supply voltage for the IC is via R8 and CR3 from the 30V
supply.

Metering outputs are provided for the supply as well as those for current drawn
from each regulator and the total current from the 30V supply. The voltage metering
outputs have calibration pots whereas the current metering outputs are preset with fixed
resistors.

Set up Procedures

• Set up one power supply for 65V; current limited to 1A and another

supply for approximately 30V, also current limited to 1A.

• Apply the voltages to the appropriate inputs, 65V to E1 and E13; 30V

to E12.

• Adjust R7 for a voltage of 50V at E4. Adjust R24 for 50V at E16.

• Check for 30V output at E11 (the same as that applied to E1 2).

• Reset the 65V supply current limit to approximately 7A, and apply

sufficient load (to draw approximately 5A at 50V) to E4 and to E16
alternately, to check the regulation of the supply. The output at either
one should not drop more than 1V under load.