LAPIS Semiconductor ML610Q421, ML610Q422, ML610421 User Manual
FEUL610Q421-06
ML610Q421/ML610Q422
ML610421
User’s Manual
Issue Date: Feb 9, 2015
Notes
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Preface
This manual describes the operation of the hardware of the 8-bit microcontroller
ML610Q421/ML610Q422/ML610421.
The following manuals are also available. Read them as necessary.
nX-U8/100 Core Instruction Manual
Description on the basic architecture and the each instruction of the nX-U8/100 Core.
MACU8 Assembler Package User’s Manual
Description on the method of operating the relocatable assembler, the linker, the
librarian, and the object converter and also on the specifications of the assembler
language.
CCU8 User’s Manual
Description on the method of operating the compiler.
CCU8 Progr amming Guide
Description on the method of programming.
CCU8 Language Refere nce
Description on the language specifications.
DTU8 Debugger User’s Manual
Description on the method of operating the debugger DTU8.
IDEU8 User’s Manual
Description on the integrated development environment IDEU8.
uEASE User’s Manual
Description on the on-chip debug tool uEASE.
uEASE connection Manual for ML610Q421/ML610Q422
Description about the connection between uEASE and ML610Q421/ML610Q422.
FWuEASE Flash Writer Host Program User’s Manual
Description on the Flash Writer host program.
Notation
MSB
LSB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0 0 1 1 0 1 0 1
Bit name
Register name
Initial value after reset
Invalid bit: This bit reads “0” when read. Write to this bit is ignored.
Classification Notation Description
♦ Numeric val ue xxh, xxH Indicates a hexadecimal number. x: Any value in the range of 0 to F
xxb Indicates a binary number; “b” may be omitted. x: A value 0 or 1
♦ Unit word, W 1 word = 16 bits
byte, B 1 byte = 8 bits
nibble, N 1 nibble = 4 bits
maga-, M 10
kilo-, K 2
kilo-, k 10
milli-, m 10
micro-, µ 10
nano-, n 10
second, s (lower case) second
♦ Terminology “H” level, “1” level Indicates high voltage signal levels V
“L” level, “0” level Indicates low voltage signal levels V
♦ Register description
R/W: Indicates that Read/Wr ite a ttr ibute. “R” indicates that data can be read and “W” indicates that data can be written.
“R/W” indicates that data can be read or written.
6
10
= 1024
3
= 1000
-3
-6
-9
electrical characteristics.
electrical characteristics.
and VOH as specified by the
IH
and VOL as specified by the
IL
FCON0 OUTC1 OUTC0 OSCM1 OSCM0 SYSC1 SYSC0
ML610Q421/ML610Q422/ML610421 User’s Manual
Table of Content s
Chapter 1
1. Overview......................................................................................................................................................... 1-1
1.1 Features ....................................................................................................................................................... 1-1
1.2 Configuration of Functional Blocks ............................................................................................................ 1-5
1.2.1 Block Diagr am of ML610Q421 .......................................................................................................... 1-5
1.2.2 Block Diagr am of ML610Q422 .......................................................................................................... 1-6
1.2.3 Block Diagram of ML610421 ............................................................................................................. 1-7
1.3 Pins ............................................................................................................................................................. 1-8
1.3.1 Pin Layout ........................................................................................................................................... 1-8
1.3.1.1 Pin Layout of ML610Q421 120pin TQFP Package ........................................................................ 1-8
1.3.1.2 Pin Layout of ML610Q422 120pin TQFP Package ........................................................................ 1-9
1.3.1.3 Pin Layout of ML610Q421 Chip ................................................................................................... 1-10
1.3.1.4 Pin Layout of ML610Q422 Chip ................................................................................................... 1-11
1.3.1.5 Pin Layout of ML610421 Chip ...................................................................................................... 1-12
1.3.1.6 Pad Coordinates of ML610Q421 Chip .......................................................................................... 1-13
1.3.1.7 Pad Coordinates of ML610Q422 Chip .......................................................................................... 1-14
1.3.1.8 Pad Coordinates of ML610421 Chip ............................................................................................. 1-15
1.3.2 List of Pi n s ........................................................................................................................................ 1-16
1.3.2.1 List of ML610Q421/ML610Q422 Pins ........................................................................................ 1-16
1.3.2.2 List o f ML610421 Pins ................................................................................................................. 1-20
1.3.3 Description of Pins ............................................................................................................................ 1-24
1.3.4 Termination of Unused Pins ............................................................................................................. 1-28
Chapter 2
Contents
2. CPU and Memory Space ................................................................................................................................. 2-1
2.1 Overview..................................................................................................................................................... 2-1
2.2 Program Memory Space ............................................................................................................................. 2-1
2.3 Data Memory Space .................................................................................................................................... 2-2
2.4 Instruc tio n Le ngth ....................................................................................................................................... 2-2
2.5 Data Type .................................................................................................................................................... 2-2
2.6 Description of Register s .............................................................................................................................. 2-3
2.6.1 List of Register s .................................................................................................................................. 2-3
2.6.2 Data Segment Register (DSR) ............................................................................................................ 2-4
Chapter 3
3. Reset Function ................................................................................................................................................ 3-1
3.1 Overview..................................................................................................................................................... 3-1
3.1.1 Features ............................................................................................................................................... 3-1
3.1.2 Configuration ...................................................................................................................................... 3-1
3.1.3 List of Pi n............................................................................................................................................ 3-1
3.2 Description of Register s .............................................................................................................................. 3-2
3.2.1 List of Register s .................................................................................................................................. 3-2
3.2.2 Reset Status Register (RSTAT) .......................................................................................................... 3-2
3.3 Description of Operatio n............................................................................................................................. 3-3
3.3.1 Operation of System Reset Mode ....................................................................................................... 3-3
Contents – 1
ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 4
4. MCU Control Function ................................................................................................................................... 4-1
4.1 Overview..................................................................................................................................................... 4-1
4.1.1 Features ............................................................................................................................................... 4-1
4.1.2 Configuration ...................................................................................................................................... 4-1
4.2 Description of Register s .............................................................................................................................. 4-2
4.2.1 List of Register s .................................................................................................................................. 4-2
4.2.2 Stop Code Acceptor (STPACP) .......................................................................................................... 4-3
4.2.3 Standby Control Register (SBYCON) ................................................................................................ 4-4
4.2.4 Block Control Register 0 (BLKCON0)............................................................................................... 4-5
4.2.5 Block Control Register 1 (BLKCON1)............................................................................................... 4-6
4.2.6 Block Control Register 2 (BLKCON2)............................................................................................... 4-7
4.2.7 Block Control Register 3 (BLKCON3)............................................................................................... 4-8
4.2.8 Block Control Register 4 (BLKCON4)............................................................................................... 4-9
4.3 Description of Operation........................................................................................................................... 4-11
4.3.1 Program Run Mode ........................................................................................................................... 4-11
4.3.2 HALT Mode ..................................................................................................................................... 4-11
4.3.3 STOP Mode ...................................................................................................................................... 4-12
4.3.3.1 STOP Mode When CPU Operates with Low-Speed Clock ........................................................... 4-12
4.3.3.2 STOP Mode When CPU Operates with High-Speed Clock .......................................................... 4-13
4.3.3.3 Note on Return Operation from STOP/HALT Mode .................................................................... 4-14
4.3.4 Block Control Function ..................................................................................................................... 4-15
Chapter 5
Contents
5. Interrupts (INTs) ............................................................................................................................................. 5-1
5.1 Overview..................................................................................................................................................... 5-1
5.1.1 Features ............................................................................................................................................... 5-1
5.2 Description of Register s .............................................................................................................................. 5-2
5.2.1 List of Register s .................................................................................................................................. 5-2
5.2.2 Interrupt Enable Register 1 (IE1) ........................................................................................................ 5-3
5.2.3 Interrupt Enable Register 2 (IE2) ........................................................................................................ 5-4
5.2.4 Interrupt Enable Register 3 (IE3) ........................................................................................................ 5-5
5.2.5 Interrupt Enable Register 4 (IE4) ........................................................................................................ 5-6
5.2.6 Interrupt Enable Register 5 (IE5) ........................................................................................................ 5-7
5.2.7 Interrupt Enable Register 6 (IE6) ........................................................................................................ 5-8
5.2.8 Interrupt Enable Register 7 (IE7) ........................................................................................................ 5-9
5.2.9 Interrupt Request Register 0 (IRQ0) ................................................................................................. 5-10
5.2.10 Interrupt Request Register 1 (IRQ1) ................................................................................................. 5-11
5.2.11 Interrupt Request Register 2 (IRQ2) ................................................................................................. 5-12
5.2.12 Interrupt Request Register 3 (IRQ3) ................................................................................................. 5-13
5.2.13 Interrupt Request Register 4 (IRQ4) ................................................................................................. 5-14
5.2.14 Interrupt Request Register 5 (IRQ5) ................................................................................................. 5-15
5.2.15 Interrupt Request Register 6 (IRQ6) ................................................................................................. 5-16
5.2.16 Interrupt Request Register 7 (IRQ7) ................................................................................................. 5-17
5.3 Description of Operatio n........................................................................................................................... 5-18
5.3.1 Maskable Interrupt Processing .......................................................................................................... 5-19
5.3.2 Non-Maskable Interrupt Processing .................................................................................................. 5-19
5.3.3 Software Interrupt Processing ........................................................................................................... 5-19
5.3.4 Notes on Inte rrupt Rout ine ................................................................................................................ 5-20
5.3.5 Interrupt Disable State ...................................................................................................................... 5-23
Chapter 6
6. Clock Generation Cir cuit ................................................................................................................................ 6-1
6.1 Overview..................................................................................................................................................... 6-1
6.1.1 Features ............................................................................................................................................... 6-1
6.1.2 Configuration ...................................................................................................................................... 6-1
Contents – 2
ML610Q421/ML610Q422/ML610421 User’s Manual
6.1.3 List of Pi n s .......................................................................................................................................... 6-2
6.2 Description of Registers .............................................................................................................................. 6-2
6.2.1 List of Register s .................................................................................................................................. 6-2
6.2.2 Frequency Control Register 0 (FCON0) ............................................................................................. 6-3
6.2.3 Frequency Control Register 1 (FCON1) ............................................................................................. 6-5
6.3 Description of Operatio n............................................................................................................................. 6-6
6.3.1 Low-Speed Clock................................................................................................................................ 6-6
6.3.1.1 Low-Speed Clock Generation Circuit.............................................................................................. 6-6
6.3.1.2 Operation of Low-Speed Clock Generation Circuit ........................................................................ 6-7
6.3.2 High-Speed Clock ............................................................................................................................... 6-8
6.3.2.1 500 kHz RC Oscillation ................................................................................................................... 6-8
6.3.2.2 Crystal/Ceramic Oscillation Mode .................................................................................................. 6-9
6.3.2.3 Built-in PLL Oscillation Mode ...................................................................................................... 6-10
6.3.2.4 Exter nal Clock Input Mode ........................................................................................................... 6-10
6.3.2.5 Operation of High-Speed Clock Generation Circuit ...................................................................... 6-11
6.3.3 Switching of System Clock ............................................................................................................... 6-13
6.4 Specifying port r e gisters ........................................................................................................................... 6-15
6.4.1 Functioning P21 (OUTCLK) as the high speed clock output ........................................................... 6-15
6.4.2 Functioning P20 (LSCLK) as the low speed clock output ................................................................ 6-16
Chapter 7
Contents
7. Time Base Counter ......................................................................................................................................... 7-1
7.1 Overview..................................................................................................................................................... 7-1
7.1.1 Features ............................................................................................................................................... 7-1
7.1.2 Configuration ...................................................................................................................................... 7-1
7.2 Description of Register s .............................................................................................................................. 7-3
7.2.1 List of Register s .................................................................................................................................. 7-3
7.2.2 Low-Speed Time Base Counter (LTBR) ............................................................................................ 7-4
7.2.3 High-Speed Time Base Counter Divide Register (HTBDR) .............................................................. 7-5
7.2.4 Low-Speed Time Base Counter Frequency Adjustment Registers L and H
(LTBADJL, LTBADJH) ..................................................................................................................... 7-6
7.3 Description of Operatio n............................................................................................................................. 7-7
7.3.1 Low-Speed Time Base Counter .......................................................................................................... 7-7
7.3.2 High-Speed Time Base Counter ......................................................................................................... 7-8
7.3.3 Low-Speed Time Base Counter Frequency Adjustment Function ...................................................... 7-9
7.3.4 A signal generation for 16bit timer 2-3 fre q ue nc y mea sur e m e nt mod e ............................................ 7-10
Chapter 8
8. Capture ............................................................................................................................................................ 8-1
8.1 Overview..................................................................................................................................................... 8-1
8.1.1 Features ............................................................................................................................................... 8-1
8.1.2 Configuration ...................................................................................................................................... 8-1
8.1.3 List of Pins .......................................................................................................................................... 8-1
8.2 Description of Registers .............................................................................................................................. 8-2
8.2.1 List of Registers .................................................................................................................................. 8-2
8.2.2 Capture Control Register (C A PCON) ................................................................................................. 8-3
8.2.3 Capture Status Register (CAPSTAT).................................................................................................. 8-4
8.2.4 Capture Data Register 0 (CAPR0) ...................................................................................................... 8-5
8.2.5 Capture Data Register 1 (CAPR1) ...................................................................................................... 8-6
8.3 Description of Operation............................................................................................................................. 8-7
Chapter 9
9. 1 kHz Timer (1kHzTM) .................................................................................................................................. 9-1
9.1 Overview..................................................................................................................................................... 9-1
9.1.1 Features ............................................................................................................................................... 9-1
9.1.2 Configuration ...................................................................................................................................... 9-1
Contents – 3
ML610Q421/ML610Q422/ML610421 User’s Manual
9.2 Description of Registers .............................................................................................................................. 9-2
9.2.1 List of Registers .................................................................................................................................. 9-2
9.2.2 1 kHz Timer Count Registers (T1KCRL, T1K CRH).......................................................................... 9-3
9.2.3 1 kHz Timer Control Register (T1KCON) ......................................................................................... 9-4
9.3 Description of Operation............................................................................................................................. 9-5
Chapter 10
10. Timers ........................................................................................................................................................... 10-1
10.1 Overview................................................................................................................................................... 10-1
10.1.1 Features ............................................................................................................................................. 10-1
10.1.2 Configuration .................................................................................................................................... 10-1
10.2 Description of Registers ............................................................................................................................ 10-3
10.2.1 List of Register s ................................................................................................................................ 10-3
10.2.2 Timer 0 Data Register (TM0D) ........................................................................................................ 10-4
10.2.3 Timer 1 Data Register (TM1D) ........................................................................................................ 10-5
10.2.4 Timer 2 Data Register (TM2D) ........................................................................................................ 10-6
10.2.5 Timer 3 Data Register (TM3D) ........................................................................................................ 10-7
10.2.6 Timer 0 Counter Register (TM0C) ................................................................................................... 10-8
10.2.7 Timer 1 Counter Register (TM1C) ................................................................................................... 10-9
10.2.8 Timer 2 Counter Register (TM2C) ................................................................................................. 10-10
10.2.9 Timer 3 Counter Register (TM3C) ................................................................................................. 10-11
10.2.10 Timer 0 Control Register 0 (TM0CON0) ....................................................................................... 10-12
10.2.11 Timer 1 Control Register 0 (TM1CON0) ....................................................................................... 10-13
10.2.12 Timer 2 Control Register 0 (TM2CON0) ....................................................................................... 10-14
10.2.13 Timer 3 Control Re gister 0 (TM3CON0) ....................................................................................... 10-15
10.2.14 Timer 0 Control Register 1 (TM0CON1) ....................................................................................... 10-16
10.2.15 Timer 1 Control Register 1 (TM1CON1) ....................................................................................... 10-17
10.2.16 Timer 2 Control Register 1 (TM2CON1) ....................................................................................... 10-18
10.2.17 Timer 3 Control Register 1 (TM3CON1) ....................................................................................... 10-19
10.3 Description of Operation......................................................................................................................... 10-20
10.3.1 Timer mode operation ..................................................................................................................... 10-20
10.3.2 16-bit timer frequenc y measure ment mode operation ................................................................... 10-21
10.3.3 16-bit timer fr equency measurement mode application for setting uart baud-rate .......................... 10-23
Chapter 11
Contents
11. PWM ............................................................................................................................................................. 11-1
11.1 Overview................................................................................................................................................... 11-1
11.1.1 Features ............................................................................................................................................. 11-1
11.1.2 Configuration .................................................................................................................................... 11-1
11.1.3 List of Pi n s ........................................................................................................................................ 11-2
11.2 Description of Registers ............................................................................................................................ 11-2
11.2.1 List of Register s ................................................................................................................................ 11-2
11.2.2 PWM0 Period Registers (PW0PL, PW0PH) .................................................................................... 11-3
11.2.3 PWM0 Duty Registers (PW0DL, PW0DH) ...................................................................................... 11-4
11.2.4 PWM0 Count er Registers (PW0CH, PW0CL) ................................................................................. 11-5
11.2.5 PWM0 Control Register 0 (PW0CON0) ........................................................................................... 11-6
11.2.6 PWM0 Control Register 1 (PW0CON1) ........................................................................................... 11-7
11.3 Description of Ope ration........................................................................................................................... 11-8
11.4 Specifying port registers ......................................................................................................................... 11-10
11.4.1 Functioning P43 (PWM0) as the PWM output ............................................................................... 11-10
11.4.2 Functioning P34 (PWM0) as the PWM output ............................................................................... 11-11
Chapter 12
12. Watchdog Timer ........................................................................................................................................... 12-1
12.1 Overview................................................................................................................................................... 12-1
12.1.1 Features ............................................................................................................................................. 12-1
Contents – 4
ML610Q421/ML610Q422/ML610421 User’s Manual
12.1.2 Configuration .................................................................................................................................... 12-1
12.2 Description of Registers ............................................................................................................................ 12-2
12.2.1 List of Register s ................................................................................................................................ 12-2
12.2.2 Watchdog Timer Control Register (W DTCON) ............................................................................... 12-3
12.2.3 Watchdog Timer Mode Register (WDTMOD) ................................................................................. 12-4
12.3 Description of Ope ration........................................................................................................................... 12-5
12.3.1 Handli ng example when you do not want to use the watch dog timer .............................................. 12-7
Chapter 13
13. Synchronous Serial Port ................................................................................................................................ 13-1
13.1 Overview................................................................................................................................................... 13-1
13.1.1 Features ............................................................................................................................................. 13-1
13.1.2 Configuration .................................................................................................................................... 13-1
13.1.3 List of Pi n s ........................................................................................................................................ 13-2
13.2 Description of Registers ............................................................................................................................ 13-3
13.2.1 List of Register s ................................................................................................................................ 13-3
13.2.2 Serial Port Transmit/Receive Buffers (SIO0BUFL, SIO0BUFH) .................................................... 13-4
13.2.3 Serial Port Control Register (SI O0CON) .......................................................................................... 13-5
13.2.4 Serial Port Mode Register 0 (SIO0MOD0) ....................................................................................... 13-6
13.2.5 Serial Port Mode Register 1 (SIO0MOD1) ....................................................................................... 13-7
13.3 Description of Ope ration........................................................................................................................... 13-8
13.3.1 Transmit Operation ........................................................................................................................... 13-8
13.3.2 Receive Operation ............................................................................................................................. 13-9
13.3.3 Transmit/Receive Operation ........................................................................................................... 13-10
13.4 Specifying port registers ......................................................................................................................... 13-11
13.4.1 Functioning P42 (SOUT0), P41 (SCK0) and P40 (SIN0) as the SSIO/ “Master mode” ................ 13-11
13.4.2 Functioning P42 (SOUT0), P41 (SCK0) and P40 (SIN0) as the SSIO/ ”Slave mode” ................... 13-12
13.4.3 Functioning P46 (SOUT0), P45 (SCK0) and P44 (SIN0) as the SSIO/ ”Master mode” ................ 13-13
13.4.4 Functioning P46 (SOUT0), P45 (SCK0) and P44 (SIN0) as the SSIO/ ”Slave mode” ................... 13-14
Chapter 14
Contents
14. UART ........................................................................................................................................................... 14-1
14.1 Overview................................................................................................................................................... 14-1
14.1.1 Features ............................................................................................................................................. 14-1
14.1.2 Configuration .................................................................................................................................... 14-1
14.1.3 List of Pins ........................................................................................................................................ 14-1
14.2 Description of Registers ............................................................................................................................ 14-2
14.2.1 List of Register s ................................................................................................................................ 14-2
14.2.2 UART0 Transmit/Receive Buffer (UA0BUF) .................................................................................. 14-3
14.2.3 UART0 Contro l Register (UA0CON) .............................................................................................. 14-4
14.2.4 UART0 Mode Register 0 (UA0MOD0) ........................................................................................... 14-5
14.2.5 UART0 Mode Register 1 (UA0MOD1) ........................................................................................... 14-6
14.2.6 UART0 Baud Rate Registers L, H (UA0BRTL, UA0BRTH) .......................................................... 14-8
14.2.7 UART0 Status Re gister (UA0STAT) ............................................................................................... 14-9
14.3 Description of Ope ration......................................................................................................................... 14-11
14.3.1 Transfer Data Format ...................................................................................................................... 14-11
14.3.2 Baud Rate ........................................................................................................................................ 14-12
14.3.3 Transmit Data Direction ................................................................................................................. 14-13
14.3.4 Transmit Operation ......................................................................................................................... 14-14
14.3.5 Receive Operation ........................................................................................................................... 14-16
14.4 Specifying port registers ......................................................................................................................... 14-18
14.4.1 Functioning P43(TXD0) and P42(RXD0) as the UART ................................................................ 14-18
14.4.2 Functioning P43(TXD0) and P02(RXD0) as the UART ................................................................ 14-19
Contents – 5
ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 15
15. I2C Bus Interface ........................................................................................................................................... 15-1
15.1 Overview................................................................................................................................................... 15-1
15.1.1 Features ............................................................................................................................................. 15-1
15.1.2 Configuration .................................................................................................................................... 15-1
15.1.3 List of Pi n s ........................................................................................................................................ 15-1
15.2 Description of Registers ............................................................................................................................ 15-2
15.2.1 List of Registers ................................................................................................................................ 15-2
15.2.2 I
15.2.3 I
15.2.4 I
15.2.5 I
15.2.6 I
15.2.7 I
2
C Bus 0 Receive Register (I2C0RD) .............................................................................................. 15-3
2
C Bus 0 Slave Addr ess Register (I2C0SA) .................................................................................... 15-4
2
C Bus 0 Transmit Dat a Register (I2C0TD) .................................................................................... 15-5
2
C Bus 0 Control Register (I2C0CON) ............................................................................................ 15-6
2
C Bus 0 Mode Register (I2C0MOD) .............................................................................................. 15-7
2
C Bus 0 Status Register (I2C0STAT) ............................................................................................ 15-8
15.3 Description of Ope ration........................................................................................................................... 15-9
15.3.1 Communication Operating Mode ...................................................................................................... 15-9
15.3.1.1 Start Condition ............................................................................................................................... 15-9
15.3.1.2 Repeated Start Condition ............................................................................................................... 15-9
15.3.1.3 Slave Address Transmit Mode ....................................................................................................... 15-9
15.3.1.4 Data Transmit Mode ...................................................................................................................... 15-9
15.3.1.5 Data Receive Mode ....................................................................................................................... 15-9
15.3.1.6 Control Register Se tting Wait State ............................................................................................... 15-9
15.3.1.7 Stop Condition ............................................................................................................................. 15-10
15.3.2 Communication Operation Timing ................................................................................................. 15-11
15.3.3 Operation Waveforms ..................................................................................................................... 15-13
15.4 Specifying port registers ......................................................................................................................... 15-14
15.4.1 Functioning P41(SCL) and P40(SDA) as the I2C .......................................................................... 15-14
Chapter 16
Contents
16. NMI Pin ........................................................................................................................................................ 16-1
16.1 Overview................................................................................................................................................... 16-1
16.1.1 Features ............................................................................................................................................. 16-1
16.1.2 Configuration .................................................................................................................................... 16-1
16.1.3 List of Pi n s ........................................................................................................................................ 16-1
16.2 Description of Registers ............................................................................................................................ 16-2
16.2.1 List of Register s ................................................................................................................................ 16-2
16.2.2 NMI Data Register (NMID) .............................................................................................................. 16-3
16.2.3 NMI Control Register (NMICON).................................................................................................... 16-4
16.3 Description of Operation........................................................................................................................... 16-5
16.3.1 Interrupt Request ............................................................................................................................... 16-5
Chapter 17
17. Port 0 ............................................................................................................................................................. 17-1
17.1 Overview................................................................................................................................................... 17-1
17.1.1 Features ............................................................................................................................................. 17-1
17.1.2 Configuration .................................................................................................................................... 17-1
17.1.3 List of Pi n s ........................................................................................................................................ 17-1
17.2 Description of Registers ............................................................................................................................ 17-2
17.2.1 List of Register s ................................................................................................................................ 17-2
17.2.2 Port 0 Data Register (P0D) ............................................................................................................... 17-3
17.2.3 Port 0 Control Registers 0, 1 (P0CON0, P0CON1) .......................................................................... 17-4
17.2.4 External Interrupt Control Registers 0, 1 (EXICON0, EXICON1)................................................... 17-5
17.2.5 External Interrupt Control Register 2 (EXICON2) ........................................................................... 17-6
17.3 Description of Oper a tion........................................................................................................................... 17-7
17.3.1 External Interrupt/Capture Function ................................................................................................. 17-7
17.3.2 Interrupt Request ............................................................................................................................... 17-7
Contents – 6
ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 18
18. Port 1 ............................................................................................................................................................. 18-1
18.1 Overview................................................................................................................................................... 18-1
18.1.1 Features ............................................................................................................................................. 18-1
18.1.2 Configuration .................................................................................................................................... 18-1
18.1.3 List of Pi n s ........................................................................................................................................ 18-1
18.2 Description of Registers ............................................................................................................................ 18-2
18.2.1 List of Registers ................................................................................................................................ 18-2
18.2.2 Port 1 Data Register (P1D) ............................................................................................................... 18-3
18.2.3 Port 1 Control Registers 0, 1 (P1CON0, P1CON1) .......................................................................... 18-4
18.3 Description of Oper a tion........................................................................................................................... 18-5
18.3.1 Input Port Function ........................................................................................................................... 18-5
18.3.2 Secondary Function .......................................................................................................................... 18-5
Chapter 19
19. Port 2 ............................................................................................................................................................. 19-1
19.1 Overview................................................................................................................................................... 19-1
19.1.1 Features ............................................................................................................................................. 19-1
19.1.2 Configuration .................................................................................................................................... 19-1
19.1.3 List of Pi n s ........................................................................................................................................ 19-1
19.2 Description of Registers ............................................................................................................................ 19-2
19.2.1 List of Register s ................................................................................................................................ 19-2
19.2.2 Port 2 Data Register (P2D) ............................................................................................................... 19-3
19.2.3 Port 2 control registers 0, 1 (P2CON0, P2CON1) ............................................................................ 19-4
19.2.4 Port 2 Mode Register (P2MOD) ....................................................................................................... 19-5
19.3 Description of Oper a tion........................................................................................................................... 19-6
19.3.1 Output Port Function ......................................................................................................................... 19-6
19.3.2 Secondary Function .......................................................................................................................... 19-6
Chapter 20
Contents
20. Port 3 ............................................................................................................................................................. 20-1
20.1 Overview................................................................................................................................................... 20-1
20.1.1 Features ............................................................................................................................................. 20-1
20.1.2 Configuration .................................................................................................................................... 20-1
20.1.3 List of Pi n s ........................................................................................................................................ 20-2
20.2 Description of Registers ............................................................................................................................ 20-3
20.2.1 List of Register s ................................................................................................................................ 20-3
20.2.2 Port 3 data register (P3D).................................................................................................................. 20-4
20.2.3 Port 3 Direction Register (P3DIR) .................................................................................................... 20-5
20.2.4 Port 3 control registers 0, 1 (P3CON0, P3CON1) ............................................................................ 20-6
20.2.5 Port 3 mode registers 0, 1 (P3MOD0, P3MOD1) ............................................................................. 20-8
20.3 Description of Oper a tion......................................................................................................................... 20-10
20.3.1 Input/Output Port Functions............................................................................................................ 20-10
20.3.2 Secondary and Tertiary Functions .................................................................................................. 20-10
Chapter 21
21. Port 4 ............................................................................................................................................................. 21-1
21.1 Overview................................................................................................................................................... 21-1
21.1.1 Features ............................................................................................................................................. 21-1
21.1.2 Configuration .................................................................................................................................... 21-1
21.1.3 List of Pins ........................................................................................................................................ 21-2
21.2 Description of Registers ............................................................................................................................ 21-3
21.2.1 List of Register s ................................................................................................................................ 21-3
21.2.2 Port 4 Data Register (P4D) ............................................................................................................... 21-4
Contents – 7
ML610Q421/ML610Q422/ML610421 User’s Manual
21.2.3 Port 4 Direction Register (P4DIR) .................................................................................................... 21-5
21.2.4 Port 4 Control Registers 0, 1 (P4CON0, P4CON1) .......................................................................... 21-6
21.2.5 Port 4 Mode Registers 0, 1 (P4MOD0, P4MOD1) ........................................................................... 21-8
21.3 Description of Oper a tion......................................................................................................................... 21-11
21.3.1 Input/Output Port Functions............................................................................................................ 21-11
21.3.2 Secondary and Tertiary Functions .................................................................................................. 21-11
Chapter 22
22. Port A ............................................................................................................................................................ 22-1
22.1 Overview................................................................................................................................................... 22-1
22.1.1 Features ............................................................................................................................................. 22-1
22.1.2 Configuration .................................................................................................................................... 22-1
22.1.3 List of Pi n s ........................................................................................................................................ 22-1
22.2 Description of Registers ............................................................................................................................ 22-2
22.2.1 List of Register s ................................................................................................................................ 22-2
22.2.2 Port A Data Register (PAD).............................................................................................................. 22-3
22.2.3 Port A Direction Register (PADIR) .................................................................................................. 22-4
22.2.4 Port A Control Registers 0, 1 (PACON0, PACON1) ....................................................................... 22-5
22.3 Description of Operation........................................................................................................................... 22-7
22.3.1 Input/Output Port Functions.............................................................................................................. 22-7
Chapter 23
Contents
23. Melody Driver .............................................................................................................................................. 23-1
23.1 Overview................................................................................................................................................... 23-1
23.1.1 Features ............................................................................................................................................. 23-1
23.1.2 Configuration .................................................................................................................................... 23-1
23.1.3 List of Pi n s ........................................................................................................................................ 23-1
23.2 Description of Registers ............................................................................................................................ 23-2
23.2.1 List of Register s ................................................................................................................................ 23-2
23.2.2 Melody 0 Control Register (MD0CON) ........................................................................................... 23-3
23.2.3 Melody 0 Tempo Code Register (MD0TMP) ................................................................................... 23-4
23.2.4 Melody 0 Scale Code Register (MD0TON) ...................................................................................... 23-5
23.2.5 Melody 0 Tone Length Code Register (MD0LEN) .......................................................................... 23-6
23.3 Description of Ope ration........................................................................................................................... 23-7
23.3.1 Operation of Melody Output ............................................................................................................. 23-7
23.3.2 Tempo Codes .................................................................................................................................... 23-8
23.3.3 Tone Length Codes ........................................................................................................................... 23-9
23.3.4 Scale Codes ..................................................................................................................................... 23-10
23.3.5 Example of Using Melo dy Circuit .................................................................................................. 23-11
23.3.6 Operations of Buzzer Output .......................................................................................................... 23-12
23.4 Specifying port registers ......................................................................................................................... 23-13
23.4.1 Functioning P22 (MD0) as the Melody or Buzzer output ............................................................... 23-13
Chapter 24
24. RC Oscillation Type A/D Con ver te r ............................................................................................................. 24-1
24.1 Overview................................................................................................................................................... 24-1
24.1.1 Features ............................................................................................................................................. 24-1
24.1.2 Configuration .................................................................................................................................... 24-1
24.1.3 List of Pi n s ........................................................................................................................................ 24-2
24.2 Description of Registers ............................................................................................................................ 24-3
24.2.1 List of Registers ................................................................................................................................ 24-3
24.2.2 RC-ADC Counter A Registers (RADCA0–2) .................................................................................. 24-4
24.2.3 RC-ADC Counter B Registers (RADCB0–2) ................................................................................... 24-5
24.2.4 RC-ADC Mode Register (RADMOD) .............................................................................................. 24-6
24.2.5 RC-ADC Control Register (RADCO N) ............................................................................................ 24-7
24.3 Description of Oper a tion........................................................................................................................... 24-8
Contents – 8
ML610Q421/ML610Q422/ML610421 User’s Manual
24.3.1 RC Oscillator Circuits ....................................................................................................................... 24-8
24.3.2 Counter A/Counter B Reference Modes ......................................................................................... 24-11
24.3.3 Example of Use of RC Oscillation Type A/D Converter ................................................................ 24-15
24.3.4 Monitoring RC Oscillation.............................................................................................................. 24-20
24.4 Specifying port registers ......................................................................................................................... 24-21
24.4.1 Functioning P35(RCM), P34(RCT0), P33(RT0), P32(RS0), P31(CS0) and P30(IN0) as the
RC-ADC(Ch0) ................................................................................................................................ 24-21
24.4.2 Functioning P47(RT1), P46(RS1), P45(CS1) and P44(IN1) as the RC-ADC(Ch1) ....................... 24-22
Chapter 25
25. Successive Approximation Type A/D Converter .......................................................................................... 25-1
25.1 Overview................................................................................................................................................... 25-1
25.1.1 Features ............................................................................................................................................. 25-1
25.1.2 Configuration .................................................................................................................................... 25-1
25.1.3 List of Pi n s ........................................................................................................................................ 25-2
25.2 Description of Registers ............................................................................................................................ 25-3
25.2.1 List of Register s ................................................................................................................................ 25-3
25.2.2 SA-ADC Result Registe r 0L (SADR0L) .......................................................................................... 25-4
25.2.3 SA-ADC Result Registe r 0H (SADR0H) ......................................................................................... 25-4
25.2.4 SA-ADC Result Registe r 1L (SADR1L) .......................................................................................... 25-5
25.2.5 SA-ADC Result Registe r 1H (SADR1H) ......................................................................................... 25-5
25.2.6 SA-ADC Control Regis t er 0 (SADCON0) ....................................................................................... 25-6
25.2.7 SA-ADC Control Regis t er 1 (SADCON1) ....................................................................................... 25-7
25.2.8 SA-ADC Mode Register 0 (SADMOD0) ......................................................................................... 25-8
25.3 Description of Oper a tion........................................................................................................................... 25-9
25.3.1 Settings of A/D Convers i on Channel s ................................................................................................ 25-9
25.3.2 Operation of the Successive Approximation A/D Converter .......................................................... 25-10
Chapter 26
Contents
26. LCD Drivers ................................................................................................................................................. 26-1
26.1 Overview................................................................................................................................................... 26-1
26.1.1 Features ............................................................................................................................................. 26-3
26.1.2 Configurati on of the L CD Drivers .................................................................................................... 26-4
26.1.3 Configurati on of the Bias Generation Circuit ................................................................................... 26-5
26.1.4 List of Pi n s ........................................................................................................................................ 26-6
26.2 Description of Registers ............................................................................................................................ 26-9
26.2.1 List of Register s ................................................................................................................................ 26-9
26.2.2 Bias Circuit Control Register 0 (BIASCON) .................................................................................. 26-10
26.2.3 Display Control Register (DSP CNT) .............................................................................................. 26-11
26.2.4 Display Mode Register 0 (DSPMOD0) .......................................................................................... 26-12
26.2.5 Display Mode Register 1 (DSPMOD1) .......................................................................................... 26-14
26.2.6 Display Control Register (DSPCON) ............................................................................................. 26-15
26.2.7 Display Allocation Register A (DS0C0A to DS49C7A) ................................................................ 26-16
26.2.8 Display Allocation Register B (DS0C0B to DS49C7B) ................................................................. 26-18
26.2.9 Display Registers (DSPR00 to DSPR71) ........................................................................................ 26-20
26.3 Description of Oper a tion......................................................................................................................... 26-25
26.3.1 Operation of LCD Drivers and Bias Generation Circuit ................................................................. 26-25
26.3.2 Segment Mapping When the Programmable Display Allocation Function is Not Used ................ 26-26
26.3.3 Segment Mapping Whe n the Programmable Display Allocation Function is Used ....................... 26-27
26.3.4 Common Output Waveforms .......................................................................................................... 26-29
26.3.5 Segment Output Waveforms ........................................................................................................... 26-31
Chapter 27
27. Battery Level Detector .................................................................................................................................. 27-1
27.1 Overview................................................................................................................................................... 27-1
27.1.1 Features ............................................................................................................................................. 27-1
Contents – 9
ML610Q421/ML610Q422/ML610421 User’s Manual
27.1.2 Configuration .................................................................................................................................... 27-1
27.2 Description of Registe r s ............................................................................................................................ 27-2
27.2.1 List of Register s ................................................................................................................................ 27-2
27.2.2 Battery Level Detector Control Register 0 (BLDCON0) .................................................................. 27-3
27.2.3 Battery Level Detector Control Register 1 (BLDCON1) .................................................................. 27-4
27.3 Description of Oper a tion........................................................................................................................... 27-5
27.3.1 Threshold Voltage ............................................................................................................................. 27-5
27.3.2 Operation of Battery Level Detector ................................................................................................. 27-6
Chapter 28
28. Power Supply Circuit .................................................................................................................................... 28-1
28.1 Overview................................................................................................................................................... 28-1
28.1.1 Features ............................................................................................................................................. 28-1
28.1.2 Configuration .................................................................................................................................... 28-1
28.1.3 List of Pi n s ........................................................................................................................................ 28-1
28.2 Description of Oper a tion........................................................................................................................... 28-2
Chapter 29
29. On-Chip Debug Function .............................................................................................................................. 29-1
29.1 Overview................................................................................................................................................... 29-1
29.2 Method of Connecting to On-Chip Debug Emulator ................................................................................ 29-1
29.3 Flash Memor y Rewrite Function .............................................................................................................. 29-2
Appendixes
Contents
Appendix A Registers ......................................................................................................................................... A-1
Appendix B Package Dimensions ........................................................................................................................B-1
Appendix C Electrical Characteristics .................................................................................................................C-1
Appendix D Application Circuit Example .......................................................................................................... D-1
Appendix E Check List ........................................................................................................................................ E-1
Revision History
Revision History .....................................................................................................................................................R-1
Contents – 10
Chapter 1
Overview
1. Overview
1.1 Features
ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 1 Overview
This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous
serial port, UART, I
converter, 12-bit successive approximation type A/D converter, and LCD d river, are incorporated around 8-bit CPU
nX-U8/100.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line
architecture parallel procesing.
The Flash ROM that is installed as program memory to ML610Q421/ML610Q422 achieves low-voltage low-power
consumption operation (read operation) equivalent to mask ROM and is most suitable for battery-driven applications.
The on-chip debug function that is installed enables program debugging and programming.
• CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system: 16-bit instructions
− Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
− On-Chip debug function（ML610Q421/ML610Q422 only）
− Minimum instruction execution time
30.5 µs (@32.768 kHz system clock)
0.24 4µs (@4.096 MHz system clock)
• Internal memory
− ML610Q421/ML610Q422:Internal 32KByte Flash ROM (16K×16 bits) (including unus able 1KByte TEST ar ea)
− ML610421:Internal 32KByte Mask ROM (16K×16 bits) (including unusable 1KByte TEST area)
− Internal 1KByte Data RAM (1024×8 bits), 1KByte Display Allocation RAM (1024 x 8bit)
− Internal 100-byte RAM for display
• Interrupt controller
− 2 non-maskable interrupt sources (Internal source: 1, External source: 1)
− 20 maskable interrupt sources (Internal sources: 16, External sources: 4)
• Time base counter
− Low-speed time base counter ×1 channel
Frequency compensation (Compensation range: Approx. −488ppm to +488ppm. Compensation accuracy: Approx.
0.48ppm)
− High-speed time base counter ×1 channel
• Watchdog timer
− Non-maskable interrupt and reset
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
• Timers
− 8 bits × 4 channels (Timer0-3: 16-bit x 2 configura tion available by using Timer0-1 or Timer2-3)
Clock frequency measurement mode (in one channel of 16-bit configurat i on using Timer2-3)
−
• 1 kHz timer
− 10 Hz/1 Hz interrup t function
2
C bus interface (master), melody driver, battery level detect circuit, RC oscillation type A/D
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations,
arithmetic shift, and so on
1 – 1
ML610Q421/ML610Q422/ML610421 User’s Manual
• Capture
− Time base capture × 2 channels (4096 Hz to 32 Hz)
• PWM
− Resolution 16 bits × 1 channel
• Synchronous ser i al port
− Master/slave selectable
− LSB first/MSB first selectable
− 8-bit length/16-bit length selectable
• UART
− Half-Duplex Communication
− TXD/RXD × 1 channel
− Bit length, parity/no parity, odd pa rity/even parity, 1 stop bit/2 stop bits
− Positive logic/negative logic selectable
− Built-in baud rate generator
2
C bus interface
• I
− Maste r function only
− Fast mode (400 kbps@４MHｚ), standard mode (100 kbps@1MHｚ, 50kbps@500kHz)
• Melody driver
− Scale: 29 types (Melody sound frequency: 508 Hz to 32.768 kHz)
− To ne length: 63 types
− Tempo: 15 types
− Buzzer output mode (4 output modes, 8 frequencies, 16 duty levels)
• RC oscillation type A/D converter
− 24-bit counter
− Time division × 2 channels
• Successive approximation type A/D converter
− 12-bit A/D converter
− Input × 2 channels
• General-purpose ports
− Non-maskable interrupt input port × 1 channel
− Input-only port × 6 channels (includ i ng s econdary functions)
− Output-only port × 3 channels (includ ing secondary functi ons)
− Input/output port
ML610Q421/ML610421: 22 channels (including second ary functions)
ML610Q422: 14 channels (including sec ondary functions)
Chapter 1 Overview
1 – 2
ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 1 Overview
• LCD driver
− Dot matrix can be supported.
ML610Q421/ML610421: 400 dots max. (50 seg × 8 com), 1/1 to 1/8 duty
ML610Q422: 800 dots max. (50 seg × 16 com), 1/1 to 1/16 duty
− 1/3 or 1/4 bias (built-in bias generation circuit)
− Frame frequency selecable (approx. 64 Hz, 73 Hz, 85 Hz, and 102 Hz)
− Bias voltage multiplying clock selectable (8 types)
− Contrast adjustment (1/3 bias: 32 steps, 1/4 bias: 20 steps)
− LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable
− Programmable display allocation function (available o nly when 1/1~1/8 duty is selected)
• Reset
− Reset through the RESET_N pin
− Power-on reset generation when powered on
− Reset when oscillation stop of the low-speed clock is detected
− Reset by the watchdog timer (WDT) overflow
• Power supply voltage detect function
− Judgment voltages: One of 16 levels
− Judgment accuracy: ±2% (Typ.)
• Clock
− Low-speed clock: (This LSI can not guarantee the operation withoug low-speed clock)
Crystal oscillation (32.768 kHz)
− High-speed clock:
Built-in RC oscillation (500 kHz)
Built-in PLL oscillation (8.192 MHz ±2.5%), crystal/ceramic oscillation (4.096 MHz), external clock
− Selection of high-speed clock mode by software:
Built-in RC oscillation, built-in PLL oscillation, cr ystal/ceramic oscillation, external clock
• Power management
− HALT mode: Instruction exec ution by CPU is suspend e d (peripheral circuits are in operating states).
− STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits
are stopped.)
− Clock gear: The frequenc y of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the
oscillation clock)
− Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals.
• Guaranteed operating range
− Operating temperature: −20°C to 70°C (P version: −40°C to +85°C)
− Operating voltage: V
= 1.1V to 3.6V, AVDD = 2.2V to 3.6V
DD
1 – 3
ML610Q421/ML610Q422/ML610421 User’s Manual
ML610Q421-xxxWA
Flash ROM
-20°C to +70°C
Yes
ML610422-xxxWA
Mask ROM
-20°C to +70°C
-
ML610Q421-xxxTB
Flash ROM
-20°C to +70°C
Yes
ML610Q422P-xxxTB
Flash ROM
-40°C to +85°C
Yes
• Product name – Supported Function
The line-up of the ML610Q421 ,the ML610Q422 and the ML610421 is below.
Chapter 1 Overview
- Chip (Die) - ROM type
ML610Q422-xxxWA Flash ROM -20°C to +70°C Yes
ML610Q421P-xxxWA Flash ROM -40°C to +85°C Yes
ML610Q422P-xxxWA Flash ROM -40°C to +85°C Yes
ML610421-xxxWA Mask ROM -20°C to +70°C Yes
ML610421P-xxxWA Mask ROM -40°C to +85°C ML610422P-xxxWA Mask ROM -40°C to +85°C -
Operating
temperature
Product availability
-120-pin plastic
TQFP -
ML610Q422-xxxTB Flash ROM -20°C to +70°C Yes
ML610Q421P-xxxTB Flash ROM -40°C to +85°C Yes
ML610421-xxxTB Mask ROM -20°C to +70°C ML610422-xxxTB Mask ROM -20°C to +70°C ML610421P-xxxTB Mask ROM -40°C to +85°C ML610422P-xxxTB Mask ROM -40°C to +85°C -
ROM type
Operating
temperature
Product availability
xxx: ROM code numbe r (xxx of the blank product is NNN)
Q: Flash ROM version
P: Wide range temperature version (P version)
WA: Chip (Die),
TB: TQFP
1 – 4
1.2 Configuration of Functional Blocks
Program
SSIO
SCK0*
SIN0*
SOUT0*
UART
RXD0*
TXD0*
I2C
SDA*
SCL*
INT
1
RAM
Interrupt
CPU (nX-U8/100)
Timing
EA
SP
On-Chip
Instruction
BUS
Instruction
TBC
INT 4 INT 1 INT 1 INT
1
WDT
INT
4
8bit Timer
Capture
INT
1
PWM
P00 to P03
P10 to P11
P20 to P22
INT 5 NMI
P30 to P35
P40 to P47
PA0 to PA7
Data-bus
PWM0*
Melody
INT 1 MD0*
TEST
RESET_N
XT0
XT1
OSC0*
OSC1*
LSCLK*
OUTCLK*
BLD
Power
AVDD
AVSS
V
LCD
COM0 to COM7
SEG0 to SEG49
LCD
VL1, VL2, VL3, VL4
C1, C2, C3, C4
12bit-ADC
AIN0, AIN1
V
REF
CS0*
IN0*
RS0*
RT0*
CRT0*
RCM*
CS1*
IN1*
RS1*
RT1*
RESET &
ALU
EPSW1～3
PSW
ELR1～3
LR
ECSR1～3
DSR/CSR
PC
GREG
VPP
VDD
VSS
V
DDX
1kHzTC
INT 1 INT 1 INT
1
Display RAM
100Byte
Display Allocation
RAM 1024Byte
1.2.1 Block Diagram of ML610Q421
Controller
ICE
TEST
OSC
DDL
RC-ADC
×2
* Secondary function or Tertiary function
0～15
Decoder
Register
1024byte
Controller
ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 1 Overview
Controller
×2
×4
Memory
(Flash)
32Kbyte
GPIO
Driver
BIAS
Figure 1-1 Block Diagram of ML610Q421
1 – 5
1.2.2 Block Diagram of ML610Q422
Program
SSIO
SCK0*
SIN0*
SOUT0*
UART
RXD0*
TXD0*
I2C
SDA*
SCL*
INT
1
RAM
Interrupt
CPU (nX-U8/100)
Timing
EA
SP
On-Chip
Instruction
BUS
Instruction
TBC
INT 4 INT 1 INT 1 INT
1
WDT
INT
4
8bit Timer
Capture
2
INT
1
PWM
P00 to P03
P10 to P11
P20 to P22
INT 5 NMI
P30 to P35
P40 to P47
Data-bus
PWM0*
Melody
INT 1 MD0*
TEST
RESET_N
XT0
XT1
OSC0*
OSC1*
LSCLK*
OUTCLK*
BLD
Power
AVDD
AVSS
V
DDL
LCD
COM0 to COM15
SEG0 to SEG49
LCD
VL1, VL2, VL3, VL4
C1, C2, C3, C4
12bit-ADC
AIN0, AIN1
V
REF
CS0*
IN0*
RS0*
RT0*
CRT0*
RCM*
CS1*
IN1*
RS1*
RT1*
RESET &
ALU
EPSW1～3
PSW
ELR1～3
LR
ECSR1～3
DSR/CSR
PC
GREG
VPP
VDD
VSS
V
DDX
1kHzTC
INT 1 INT 1 INT
1
Display RAM
192Byte
Display Allocation
RAM 1KByte
0～15
Controller
ICE
Decoder
TEST
OSC
RC-ADC
×2
*
Secondary function or Tert iary function
Register
1024byte
Controller
×
×4
ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 1 Overview
Controller
Memory
(Flash)
32Kbyte
GPIO
Driver
BIAS
Figure 1-2 Block Diagram of ML610Q422
1 – 6
1.2.3 Block Diagram of ML610421
Program
SCK0*
SIN0*
SOUT0*
UART
RXD0*
TXD0*
I2C
SDA*
SCL*
INT
1
Interrupt
CPU (nX-U8/100)
Timing
EA
SP
On-Chip
Instruction
BUS
Instruction
TBC
INT 4 INT 1 INT 1 INT
1
WDT
INT
4
8bit Timer
Capture
INT
1
PWM
P00 to P03
P10 to P11
P20 to P22
INT 5 NMI
P30 to P35
P40 to P47
PA0 to PA7
Data-bus
PWM0*
Melody
INT 1 MD0*
TEST
RESET_N
XT0
XT1
OSC0*
OSC1*
LSCLK*
OUTCLK*
BLD
Power
AVDD
AVSS
V
DDL
LCD
COM0 to COM7
SEG0 to SEG49
LCD
VL1, VL2, VL3, VL4
C1, C2, C3, C4
12bit-ADC
AIN0, AIN1
V
REF
CS0*
IN0*
RS0*
RT0*
CRT0*
RCM*
CS1*
IN1*
RS1*
RT1*
ALU
EPSW1～3
PSW
ELR1～3
LR
ECSR1～3
DSR/CSR
PC
GREG
VDD
VSS
V
DDX
1kHzTC
INT
1
INT
1
INT
1
Display RAM
100Byte
Display Allocation
RESET &
RAM
SSIO
0～15
Controller
ICE
Decoder
TEST
OSC
RC-ADC
×2
* Secondary function or Tertiary function
Register
1024byte
Controller
×2
×4
RAM 1024Byte
ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 1 Overview
Controller
Memory
(MaskROM)
32Kbyte
GPIO
Driver
BIAS
Figure 1-3 Block Diagram of ML610421
1 – 7
1.3 Pins
1pin
120pin
30pin
31pin
60pin
61pin
91pin
90pin
PA7
P20
P21
P22
P40
P41
VSS
PA5
PA4
PA3
PA2
PA1
PA0
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
SEG49
(NC)
AVSS
(NC)
VREF
AIN0
AIN1
AVDD
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
VDD
P11
(NC)
P10
VSS
P03
P02
P01
P00
C4
C3
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG18
SEG17
SEG16
SEG15
SEG14
RESET_N
P42
P43
P44
P45
P46
P30
P31
P34
P32
P33
P35
TEST
VDD
VDDL
VSS
VDDX
XT0
VL1
VL3
VL2
NMI
VSS
XT1
VL4
C1
C2
P47
VPP＊
１
(NC)
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG19
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
96
97
98
99
100
101
102
91
92
93
94
95
44
43
42
41
40
39
38
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
37
36
35
34 3332
31
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
1 2 3 4 5 6 7
30
89
88
87
86
85
84
82
81
80
79
78
77
76
75
74
73
72
71
66
64
65
67 68
69
63
62
61
83
90
70
1.3.1 Pin Layout
1.3.1.1 Pin Layout of ML610Q421 TQFP Package
ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 1 Overview
(NC): No Connection
Note:
The assignment of the pads P30 to P35 are not in order.
1
：A VPP terminal exists only ML610Q421.
*
Figure 1-4 Pin Layout of ML610Q421 Package
1 – 8
1.3.1.2 Pin Layout of ML610Q422 TQFP Package
1pin
120pin
30pin
31pin
60pin
61pin
91pin
90pin
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
VDD
P11
(NC)
P10
VSS
P03
P02
P01
P00
C4
C3
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG18
SEG17
SEG16
SEG15
SEG14
RESET_N
P42
P43
P44
P45
P46
P30
P31
P34
P32
P33
P35
TEST
VDD
VDDL
VSS
VDDX
XT0
VL1
VL3
VL2
NMI
VSS
XT1
VL4
C1
C2
P47
VPP*
1
(NC)
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG19
COM15
P20
P21
P22
P40
P41
VSS
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
SEG49
(NC)
AVSS
(NC)
VREF
AIN0
AIN1
AVDD
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
96
97
98
99
100
101
102
91
92
93
94
95
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
1 2 3 4 5 6 7
30
44
43
42
41
40
39
38
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60 3736 3534
33
32
31
89
88
87
86
85
84
82
81
80
79
78
77
76
75
74
73
72
71
66
64
65
67 68
69
63
62 61
83
90
70
ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 1 Overview
(NC): No Connection
Note:
The assignment of the pads P30 to P35 are not in order.
1
：A VPP terminal exists only ML610Q422..
*
Figure 1-5 Pin Layout of ML610Q422 Package
1 – 9
1.3.1.3 Pin Layout of ML610Q421 Chip
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
8887868584838281807978777675747372717069686766656463626160
59
SEG49 89 58 SEG18
COM0
90 57 SEG17
COM1 91 56 SEG16
COM2 92 55 SEG15
COM3 93 54 SEG14
COM4 94 53 SEG13
COM5 95 52 SEG12
COM6 96 51 SEG11
COM7 97 50 SEG10
PA0 98 49
SEG9
PA1 99 48 SEG8
PA2 100 47 SEG7
PA3 101 46 SEG6
PA4 102 45 SEG5
PA5 103 44 SEG4
PA6 104 43 SEG3
PA7 105 42 SEG2
P20/LED0 106
P21/LED1 107
P22/LED2 108
P40/SDA 109
P41/SCL 110
Vss 111
AVSS 112
VREF 113
AIN0 114
AIN1 115
AVDD 116
123456789
10111213141516171819202122232425262728
29
VPP
RESET_N
P42
P43
P44/IN1
P45/CS1
P46/RS1
P47/RT1
P30/IN0
P31/CS0
P34/RCT0
P32/RS0
P33/RT0
P35/RCM
TEST
VDD
VDDL
Vss
VDDX
XT0
XT1
Vss
NMI
VL1
VL2
VL3
VL4
C1
C2
41
40
39
38
37
363534
33
32
30
31
SEG1
SEG0
VDD
P11
P10
Vss
P03
P02
P01
P00
C3
C4
2.98mm
3.02mm
ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 1 Overview
Note:
The assignment of the pads P30 to P35 are not in order.
Chip size: 2.98 mm × 3.02mm
PAD count: 116 pins
Minimum PAD pitch: 80 µm
PAD aperture: 70 µm ×70 µm
Chip thickness: 350 µm
Voltage of the rear side of chip: V
level
SS
Figure 1-6 Dimensions of ML610Q421 Chip
1 – 10
1.3.1.4 Pin Layout of ML610Q422 Chip
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
8887868584838281807978777675747372717069686766656463626160
59
SEG49 89 58 SEG18
COM0 90 57 SEG17
COM1 91 56 SEG16
COM2 92 55 SEG15
COM3 93 54 SEG14
COM4 94 53 SEG13
COM5 95 52 SEG12
COM6 96 51 SEG11
COM7 97 50 SEG10
COM8 98 49 SEG9
COM9 99 48 SEG8
COM10 100 47 SEG7
COM11 101 46 SEG6
COM12 102 45 SEG5
COM13 103 44 SEG4
COM14 104 43 SEG3
COM15 105 42 SEG2
P20/LED0 106
P21/LED1 107
P22/LED2 108
P40/SDA 109
P41/SCL 110
Vss 111
AVSS 112
VREF 113
AIN0 114
AIN1 115
AVDD 116
123456789
10111213141516171819202122232425262728
29
VPP
RESET_N
P42
P43
P44/IN1
P45/CS1
P46/RS1
P47/RT1
P30/IN0
P31/CS0
P34/RCT0
P32/RS0
P33/RT0
P35/RCM
TEST
VDD
VDDL
Vss
VDDX
XT0
XT1
Vss
NMI
VL1
VL2
VL3
VL4
C1
C2
414039
38
37
363534
33
32
30
31
SEG1
SEG0
VDD
P11
P10
Vss
P03
P02
P01
P00
C3
C4
2.98mm
3.02mm
ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 1 Overview
Note:
The assignment of the pads P30 to P35 are not in order.
Chip size: 2.98 mm × 3.02 mm
PAD count: 116 pins
Minimum PAD pitch: 80 µm
PAD aperture: 70 µm × 70 µm
Chip thickness: 350 µm
Voltage of the rear side of chip: V
level
SS
Figure 1-7 Dimensions of ML610Q422 Chip
1 – 11
1.3.1.5 Pin Layout of ML610421 Chip
ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 1 Overview
Note:
The assignment of the pads P30 to P35 are not in order.
Chip size: 2.80 mm × 2.86mm
PAD count: 115 pins
Minimum PAD pitch: 80 µm
PAD aperture: 70 µm ×70 µm
Chip thickness: 350 µm
Voltage of the rear side of chip: V
Figure 1-8 Dimensions of ML610421 Chip
1 – 12
level
SS
1.3.1.6 Pad Coordinates of ML610Q421 Chip
Chip Center: X=0,Y=0
1
VPP
-1240
-1404 51
SEG11
1384
640 101
PA3
-1384
240 2 RESET_N
-1160
-1404 52
SEG12
1384
720 102
PA4
-1384
160 3 P42
-1080
-1404 53
SEG13
1384
800 103
PA5
-1384
80 4 P43
-1000
-1404 54
SEG14
1384
880 104
PA6
-1384 0 5
P44
-920
-1404 55
SEG15
1384
960 105
PA7
-1384
-80 6 P45
-840
-1404 56
SEG16
1384
1040 106
P20
-1384
-200 7 P46
-760
-1404 57
SEG17
1384
1120 107
P21
-1384
-280 8 P47
-680
-1404 58
SEG18
1384
1200 108
P22
-1384
-360 9 P30
-600
-1404 59
SEG19
1160
1404 109
P40
-1384
-440
10
P31
-520
-1404 60
SEG20
1080
1404 110
P41
-1384
-520
11
P34
-440
-1404 61
SEG21
1000
1404 111
Vss
-1384
-600
12
P32
-360
-1404 62
SEG22
920
1404 112
AVss
-1384
-680
13
P33
-280
-1404 63
SEG23
840
1404 113
VREF
-1384
-840
14
P35
-200
-1404 64
SEG24
760
1404 114
AIN0
-1384
-920
15
TEST
-120
-1404 65
SEG25
680
1404 115
AIN1
-1384
-1092
16
VDD
-40
-1404 66
SEG26
600
1404 116
AVDD
-1384
-1172
17
VDDL
40
-1404 67
SEG27
520
1404 18
Vss
120
-1404 68
SEG28
440
1404 19
VDDX
200
-1404 69
SEG29
360
1404 20
XT0
360
-1404 70
SEG30
280
1404 21
XT1
520
-1404 71
SEG31
200
1404 22
Vss
600
-1404 72
SEG32
120
1404 23
NMI
680
-1404 73
SEG33
40
1404 24
VL1
840
-1404 74
SEG34
-40
1404 25
VL2
920
-1404 75
SEG35
-120
1404 26
VL3
1000
-1404 76
SEG36
-200
1404 27
VL4
1080
-1404 77
SEG37
-280
1404 28
C1
1160
-1404 78
SEG38
-360
1404 29
C2
1240
-1404 79
SEG39
-440
1404 30
C3
1384
-1240 80
SEG40
-520
1404 31
C4
1384
-1160 81
SEG41
-600
1404 32
P00
1384
-1040 82
SEG42
-680
1404 33
P01
1384
-960 83
SEG43
-760
1404 34
P02
1384
-880 84
SEG44
-840
1404 35
P03
1384
-800 85
SEG45
-920
1404 36
Vss
1384
-660 86
SEG46
-1000
1404 37
P10
1384
-580 87
SEG47
-1080
1404 38
P11
1384
-420 88
SEG48
-1160
1404 39
VDD
1384
-340 89
SEG49
-1384
1200 40
SEG0
1384
-240 90
COM0
-1384
1120 41
SEG1
1384
-160 91
COM1
-1384
1040 42
SEG2
1384
-80 92
COM2
-1384
960 43
SEG3
1384
0 93
COM3
-1384
880 44
SEG4
1384
80 94
COM4
-1384
800 45
SEG5
1384
160 95
COM5
-1384
720 46
SEG6
1384
240 96
COM6
-1384
640 47
SEG7
1384
320 97
COM7
-1384
560 48
SEG8
1384
400 98
PA0
-1384
480 49
SEG9
1384
480 99
PA1
-1384
400 50
SEG10
1384
560 100
PA2
-1384
320
Table 1-1 Pad Coordinates of ML610Q421
ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 1 Overview
PAD
No.
Pad
Name X (μm) Y (μm)
PAD
No.
Pad
Name X (μm) Y (μm)
PAD
No.
Pad
Name X (μm) Y (μm)
1 – 13
1.3.1.7 Pad Coordinates of ML610Q422 Chip
Chip Center: X=0,Y=0
1
VPP
-1240
-1404 51
SEG11
1384
640 101
COM11
-1384
240 2 RESET_N
-1160
-1404 52
SEG12
1384
720 102
COM12
-1384
160 3 P42
-1080
-1404 53
SEG13
1384
800 103
COM13
-1384
80 4 P43
-1000
-1404 54
SEG14
1384
880 104
COM14
-1384 0 5
P44
-920
-1404 55
SEG15
1384
960 105
COM15
-1384
-80 6 P45
-840
-1404 56
SEG16
1384
1040 106
P20
-1384
-200 7 P46
-760
-1404 57
SEG17
1384
1120 107
P21
-1384
-280 8 P47
-680
-1404 58
SEG18
1384
1200 108
P22
-1384
-360 9 P30
-600
-1404 59
SEG19
1160
1404 109
P40
-1384
-440
10
P31
-520
-1404 60
SEG20
1080
1404 110
P41
-1384
-520
11
P34
-440
-1404 61
SEG21
1000
1404 111
Vss
-1384
-600
12
P32
-360
-1404 62
SEG22
920
1404 112
AVss
-1384
-680
13
P33
-280
-1404 63
SEG23
840
1404 113
VREF
-1384
-840
14
P35
-200
-1404 64
SEG24
760
1404 114
AIN0
-1384
-920
15
TEST
-120
-1404 65
SEG25
680
1404 115
AIN1
-1384
-1092
16
VDD
-40
-1404 66
SEG26
600
1404 116
AVDD
-1384
-1172
17
VDDL
40
-1404 67
SEG27
520
1404 18
Vss
120
-1404 68
SEG28
440
1404 19
VDDX
200
-1404 69
SEG29
360
1404 20
XT0
360
-1404 70
SEG30
280
1404 21
XT1
520
-1404 71
SEG31
200
1404 22
Vss
600
-1404 72
SEG32
120
1404 23
NMI
680
-1404 73
SEG33
40
1404 24
VL1
840
-1404 74
SEG34
-40
1404 25
VL2
920
-1404 75
SEG35
-120
1404 26
VL3
1000
-1404 76
SEG36
-200
1404 27
VL4
1080
-1404 77
SEG37
-280
1404 28
C1
1160
-1404 78
SEG38
-360
1404 29
C2
1240
-1404 79
SEG39
-440
1404 30
C3
1384
-1240 80
SEG40
-520
1404 31
C4
1384
-1160 81
SEG41
-600
1404 32
P00
1384
-1040 82
SEG42
-680
1404 33
P01
1384
-960 83
SEG43
-760
1404 34
P02
1384
-880 84
SEG44
-840
1404 35
P03
1384
-800 85
SEG45
-920
1404 36
Vss
1384
-660 86
SEG46
-1000
1404 37
P10
1384
-580 87
SEG47
-1080
1404 38
P11
1384
-420 88
SEG48
-1160
1404 39
VDD
1384
-340 89
SEG49
-1384
1200 40
SEG0
1384
-240 90
COM0
-1384
1120 41
SEG1
1384
-160 91
COM1
-1384
1040 42
SEG2
1384
-80 92
COM2
-1384
960 43
SEG3
1384
0 93
COM3
-1384
880 44
SEG4
1384
80 94
COM4
-1384
800 45
SEG5
1384
160 95
COM5
-1384
720 46
SEG6
1384
240 96
COM6
-1384
640 47
SEG7
1384
320 97
COM7
-1384
560 48
SEG8
1384
400 98
COM8
-1384
480 49
SEG9
1384
480 99
COM9
-1384
400 50
SEG10
1384
560 100
COM10
-1384
320
Table 1-2 Pad Coordinates of ML610Q422
ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 1 Overview
PAD
No.
Pad
Name X (μm) Y (μm)
PAD
No.
Pad
Name X (μm) Y (μm)
PAD
No.
Pad
Name X (μm) Y (μm)
1 – 14
1.3.1.8 Pad Coordinates of ML610421 Chip
Chip Center: X=0,Y=0
1
RESET_N
-1090
-1324 51
SEG12
1294
630 101
PA4
-1294
60 2 P42
-1010
-1324 52
SEG13
1294
710 102
PA5
-1294
-20 3 P43
-930
-1324 53
SEG14
1294
790 103
PA6
-1294
-100 4 P44
-850
-1324 54
SEG15
1294
870 104
PA7
-1294
-180 5 P45
-770
-1324 55
SEG16
1294
950 105
P20
-1294
-270 6 P46
-690
-1324 56
SEG17
1294
1030 106
P21
-1294
-350 7 P47
-610
-1324 57
SEG18
1294
1110 107
P22
-1294
-430 8 P30
-530
-1324 58
SEG19
1160
1324 108
P40
-1294
-510 9 P31
-450
-1324 59
SEG20
1080
1324 109
P41
-1294
-590
10
P34
-370
-1324 60
SEG21
1000
1324 110
Vss
-1294
-670
11
P32
-290
-1324 61
SEG22
920
1324 111
AVss
-1294
-750
12
P33
-210
-1324 62
SEG23
840
1324 112
VREF
-1294
-830
13
P35
-130
-1324 63
SEG24
760
1324 113
AIN0
-1294
-910
14
TEST
-50
-1324 64
SEG25
680
1324 114
AIN1
-1294
-1082
15
VDD
30
-1324 65
SEG26
600
1324 115
AVDD
-1294
-1162
16
VDDL
110
-1324 66
SEG27
520
1324 17
Vss
190
-1324 67
SEG28
440
1324 18
VDDX
270
-1324 68
SEG29
360
1324 19
XT0
350
-1324 69
SEG30
280
1324 20
XT1
510
-1324 70
SEG31
200
1324 21
Vss
590
-1324 71
SEG32
120
1324 22
NMI
670
-1324 72
SEG33
40
1324 23
VL1
750
-1324 73
SEG34
-40
1324 24
VL2
830
-1324 74
SEG35
-120
1324 25
VL3
910
-1324 75
SEG36
-200
1324 26
VL4
990
-1324 76
SEG37
-280
1324 27
C1
1070
-1324 77
SEG38
-360
1324 28
C2
1150
-1324 78
SEG39
-440
1324 29
C3
1294
-1220 79
SEG40
-520
1324 30
C4
1294
-1140 80
SEG41
-600
1324 31
P00
1294
-1050 81
SEG42
-680
1324 32
P01
1294
-970 82
SEG43
-760
1324 33
P02
1294
-890 83
SEG44
-840
1324 34
P03
1294
-810 84
SEG45
-920
1324 35
Vss
1294
-730 85
SEG46
-1000
1324 36
P10
1294
-650 86
SEG47
-1080
1324 37
P11
1294
-490 87
SEG48
-1160
1324 38
VDD
1294
-410 88
SEG49
-1294
1110 39
SEG0
1294
-330 89
COM0
-1294
1030 40
SEG1
1294
-250 90
COM1
-1294
950 41
SEG2
1294
-170 91
COM2
-1294
870 42
SEG3
1294
-90 92
COM3
-1294
790 43
SEG4
1294
-10 93
COM4
-1294
710 44
SEG5
1294
70 94
COM5
-1294
630 45
SEG6
1294
150 95
COM6
-1294
550 46
SEG7
1294
230 96
COM7
-1294
470 47
SEG8
1294
310 97
PA0
-1294
380 48
SEG9
1294
390 98
PA1
-1294
300 49
SEG10
1294
470 99
PA2
-1294
220 50
SEG11
1294
550 100
PA3
-1294
140
Table 1-3 Pad Coordinates of ML610421
ML610Q421/ML610Q422/ML610421 User’s Manual
Chapter 1 Overview
PAD
No.
Pad
Name X (μm) Y (μm)
PAD
No.
Pad
Name X (μm) Y (μm)
PAD
No.
Pad
Name X (μm) Y (μm)
1 – 15
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