FEUL610Q111-05
ML610Q111/ML610Q112
User’s Manual
Issue Date: Nov. 16, 2016
ML610Q111/ML610Q112 User’s Manual
NOTES
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Copyright 2013-2016 LAPIS Semiconductor Co., Ltd.
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http://www.lapis-semi.com/en/
FEUL610Q111 1
ML610Q111/ML610Q112 User’s Manual
Preface
This manual describes the operation of the hardware of the 8-bit microcontroller ML610Q111 /
ML610Q112.
The following manuals are also available. Read them as necessary.
nX-U8/100 Core Instruction Manual
Description on the basic architecture and the each instruction of the nX-U8/100 Core.
MACU8 Assembler Package User’s Manual
Description on the method of operating the relocatable assembler, the linker, the librarian,
and the object converter and also on the specifications of the assembler language.
CCU8 User’s Manual
Description on the method of operating the compiler.
CCU8 Progr amming Guide
Description on the method of programming.
CCU8 Language Reference
Description on the language specifications.
DTU8 Debugger User’s Manual
Description on the method of operating the debugger DTU8.
IDEU8 User’s Manual
Description on the integrated development environment IDEU8.
uEASE User’s Manual
Description on the on-chip debug tool uEASE.
uEASE conne ction Manual for ML610QXXX
Description about the connection between uEASE and ML610Q111 and ML610Q112.
FWuEASE Flash Writer Host Program User’s Manual
Description on the Flash Writer host program.
FEUL610Q111 2
ML610Q111/ML610Q112 User’s Manual
MSB
LSB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0 0 1 1 0 1 0 1
Notation
Classification Notation Description
♦ Numeric value xxh, xxH Indicates a hexadecimal number. x: Any value in the range of 0 to F
xxb Indicates a binary number; “b” may be omitted. x: A value 0 or 1
♦ Unit word, W 1 word = 16 bits
byte, B 1 byte = 8 bits
nibble, N 1 nibble = 4 bits
maga-, M 10
kilo-, K 2
kilo-, k 10
milli-, m 10
micro-, µ 10
nano-, n 10
second, s (lower case) second
♦ Terminology “H” level, “1” level Indicates hi gh voltage si gnal levels V
“L” level, “0” level Indicates low voltage signal levels V
♦ Register description
R/W: Indicates that Read/Wr ite a ttribute. “R” indicates that data can be read and “W” indicates that data can be written. “R/W”
indicates that data can be read or written.
Register name
6
10
= 1024
3
= 1000
-3
-6
-9
and VOH as specified by the electrical
IH
characteristics.
and VOL as specified by the electrical
IL
characteristics.
Invalid bit: This bit reads “0” when read. Write to this bit is ignored.
Bit name
FCON0 OUTC1 OUTC0 OSCM1 OSCM0 SYSC1 SYSC0
Initial value after reset
FEUL610Q111 3
ML610Q111/ML610Q112 User’s Manual
Contents
Chapter 1
1 Overview ..................................................................................................................................................... 1-1
1.1 Features .................................................................................................................................................. 1-1
1.2 Configuration of Functional Blocks ....................................................................................................... 1-4
1.2.1 Block Diagram ............................................................................................................................. 1-4
1.3 Pins ......................................................................................................................................................... 1-5
1.3.1 Pin Layout .................................................................................................................................... 1-5
1.3.2 List of Pins.................................................................................................................................... 1-6
1.3.3 Description of Pins ....................................................................................................................... 1-8
1.3.4 Termination of Unused Pins ....................................................................................................... 1-11
Chapter 2
2 CPU and Memory Space ............................................................................................................................. 2-1
2.1 Overview ................................................................................................................................................ 2-1
2.2 Program Memory Space ......................................................................................................................... 2-1
2.3 Data Memory Space ............................................................................................................................... 2-3
2.4 Instruction Length .................................................................................................................................. 2-5
2.5 Data Ty pe ............................................................................................................................................... 2-5
2.6 Description of Registers ......................................................................................................................... 2-6
2.6.1 List of Registers ............................................................................................................................ 2-6
2.6.2 Data Segment Register (DSR) ...................................................................................................... 2-7
Chapter 3
Contents
3 Reset Function ............................................................................................................................................. 3-1
3.1 Overview ................................................................................................................................................ 3-1
3.1.1 Features ........................................................................................................................................ 3-1
3.1.2 Configuration ................................................................................................................................ 3-1
3.1.3 List of Pin ..................................................................................................................................... 3-1
3.2 Description of Registers ......................................................................................................................... 3-2
3.2.1 List of Registers ............................................................................................................................ 3-2
3.2.2 Reset Status Register (RSTAT) ..................................................................................................... 3-2
3.3 Description of Operation ........................................................................................................................ 3-3
3.3.1 Operation of System Reset Mode ................................................................................................. 3-3
Chapter 4
4 MCU Control Function ................................................................................................................................ 4-1
4.1 Overview .................................................................................................................................................. 4-1
4.1.1 Features ........................................................................................................................................ 4-1
4.1.2 Configuration ................................................................................................................................ 4-1
4.2 Description of Registers ........................................................................................................................... 4-2
4.2.1 List of Registers ............................................................................................................................ 4-2
4.2.2 Stop Code Acceptor (STPACP) .................................................................................................... 4-3
4.2.3 Standby Control Register (SBYCON) .......................................................................................... 4-4
4.2.4 Block Control Register 2 (BLKCON2) ........................................................................................ 4-5
4.2.5 Block Control Register 4 (BLKCON4) ........................................................................................ 4-6
4.2.6 Block Control Register 6 (BLKCON6) ........................................................................................ 4-7
4.2.7 Block Control Register 7 (BLKCON7) ........................................................................................ 4-9
4.3 Descr ipt ion of Operation ....................................................................................................................... 4-10
4.3.1 Program Run Mode .................................................................................................................... 4-10
4.3.2 HALT Mode ............................................................................................................................... 4-10
4.3.3 STOP Mode ................................................................................................................................ 4-11
4.3.3.1 STOP Mode When CPU Operates with Low-Speed Clock ............................................................4-11
4.3.3.2 STOP Mode When CPU Operates with High-Speed Clock........................................................... 4-12
4.3.3.3 Note on Return Operation from STOP/HALT Mode ..................................................................... 4-13
4.3.4 Block Control Function .............................................................................................................. 4-14
FEUL610Q111 Contents - 1
ML610Q111/ML610Q112 User’s Manual
Chapter 5
5 Interrupts (INTs) .......................................................................................................................................... 5-1
5.1 Overview ................................................................................................................................................ 5-1
5.1.1 Features ........................................................................................................................................ 5-1
5.2 Description of Registers ......................................................................................................................... 5-2
5.2.1 List of Registers ............................................................................................................................ 5-2
5.2.2 Interrupt Enable Register 0 (IE0) ................................................................................................. 5-3
5.2.3 Interrupt Enable Register 1 (IE1) ................................................................................................. 5-4
5.2.4 Interrupt Enable Register 2 (IE2) ................................................................................................. 5-6
5.2.5 Interrupt Enable Register 3 (IE3) ................................................................................................. 5-7
5.2.6 Interrupt Enable Register 4 (IE4) ................................................................................................. 5-8
5.2.7 Interrupt Enable Register 5 (IE5) ................................................................................................. 5-9
5.2.8 Interrupt Enable Register 6 (IE6) ............................................................................................... 5-10
5.2.9 Interrupt Enable Register 7 (IE7) ............................................................................................... 5-11
5.2.10 Interrupt Request Register 0 (IRQ0) .......................................................................................... 5-12
5.2.11 Interrupt Request Register 1 (IRQ1) .......................................................................................... 5-13
5.2.12 Interrupt Request Register 2 (IRQ2) .......................................................................................... 5-15
5.2.13 Interrupt Request Register 3 (IRQ3) .......................................................................................... 5-16
5.2.14 Interrupt Request Register 4 (IRQ4) .......................................................................................... 5-17
5.2.15 Interrupt Request Register 5 (IRQ5) .......................................................................................... 5-18
5.2.16 Interrupt Request Register 6 (IRQ6) .......................................................................................... 5-19
5.2.17 Interrupt Request Register 7 (IRQ7) .......................................................................................... 5-21
5.3 Description of Operation ...................................................................................................................... 5-22
5.3.1 Maskable Interrupt Processing ................................................................................................... 5-23
5.3.2 Non-Maskable Interrupt Processing ........................................................................................... 5-23
5.3.3 Software Interrupt Processing .................................................................................................... 5-23
5.3.4 Notes on Interrupt Routine ......................................................................................................... 5-24
5.3.5 Interrupt Disable State ................................................................................................................ 5-27
Chapter 6
Contents
6 Clock Generation Circuit ............................................................................................................................. 6-1
6.1 Overview ................................................................................................................................................ 6-1
6.1.1 Features ........................................................................................................................................ 6-1
6.1.2 Configuration ................................................................................................................................ 6-1
6.1.3 List of Pins.................................................................................................................................... 6-2
6.2 Description of Registers ......................................................................................................................... 6-2
6.2.1 List of Registers ............................................................................................................................ 6-2
6.2.2 Frequency Control Register 0 (FCON0) ...................................................................................... 6-3
6.2.3 Frequency Control Register 1 (FCON1) ...................................................................................... 6-4
6.3 Description of Operation ........................................................................................................................ 6-5
6.3.1 Low-Speed Clock ......................................................................................................................... 6-5
6.3.1.1 Low-Speed Clock Generation Circuit (built-in RC oscillating circuit) ........................................... 6-5
6.3.1.2 Operation of Low-Speed Clock Generatio n Circuit ........................................................................ 6-6
6.3.2 High-Speed Clock ........................................................................................................................ 6-7
6.3.2.1 Built-in PLL Oscillation Mode ........................................................................................................ 6-7
6.3.2.2 High-Speed External Clock Input Mode ......................................................................................... 6-8
6.3.2.3 Operation of High-Speed Cloc k Gener a tion Circuit ........................................................................ 6-9
6.3.3 Switching of System Clock ........................................................................................................ 6-10
6.4 Specifying port registers ...................................................................................................................... 6-11
6.4.1 Functioning PB7 (LSCLK) as the low speed clock output ......................................................... 6-11
6.4.2 Functioning PB0 (OUTCLK) as the High speed clock output ................................................... 6-12
6.4.3 Functioning PA2 (CLKIN) as the External clock input .............................................................. 6-13
Chapter 7
7 Time Base Counter ...................................................................................................................................... 7-1
7.1 Overview ................................................................................................................................................ 7-1
7.1.1 Features ........................................................................................................................................ 7-1
7.1.2 Configuration ................................................................................................................................ 7-1
7.2 Description of Registers ......................................................................................................................... 7-3
FEUL610Q111 Contents - 2
ML610Q111/ML610Q112 User’s Manual
7.2.1 List of Registers ............................................................................................................................ 7-3
7.2.2 Low-Speed Time Base Counter (LTBR) ...................................................................................... 7-4
7.2.3 High-Speed Time Base Counter Divide Register (HTBDR) ........................................................ 7-5
7.3 Description of Operation ........................................................................................................................ 7-6
7.3.1 Low-Speed Time Base Counter .................................................................................................... 7-6
7.3.2 High-Speed Time Base Counter ................................................................................................... 7-7
Chapter 8
8 Timers .......................................................................................................................................................... 8-1
8.1 Overview ................................................................................................................................................ 8-1
8.1.1 Features ........................................................................................................................................ 8-1
8.1.2 Configuration ................................................................................................................................ 8-2
8.1.3 List of Pins.................................................................................................................................... 8-4
8.2 Description of Registers ......................................................................................................................... 8-5
8.2.1 List of Registers ............................................................................................................................ 8-5
8.2.2 Timer 8 Data Register (TM8D) .................................................................................................... 8-6
8.2.3 Timer 9 Data Register (TM9D) .................................................................................................... 8-7
8.2.4 Timer A Data Register (TMAD) ................................................................................................... 8-8
8.2.5 Timer B Data Register (TMBD) ................................................................................................... 8-9
8.2.6 Timer E Data Register (TMED) ................................................................................................. 8-10
8.2.7 Timer F Data Register (TMFD) .................................................................................................. 8-11
8.2.8 Timer 8 Counter Register (TM8C) ............................................................................................. 8-12
8.2.9 Timer 9 Counter Register (TM9C) ............................................................................................. 8-13
8.2.10 Timer A Counter Register (TMAC) ............................................................................................ 8-14
8.2.11 Timer B Counter Register (TMBC) ............................................................................................ 8-15
8.2.12 Timer E Counter Register (TMEC) ............................................................................................ 8-16
8.2.13 Timer F Counter Register (TMFC) ............................................................................................. 8-17
8.2.14 Timer 8 Control Register 0 (TM8CON0) ................................................................................... 8-18
8.2.15 Timer 9 Control Register 0 (TM9CON0) ................................................................................... 8-19
8.2.16 Timer A Control Register 0 (TMACON0) .................................................................................. 8-20
8.2.17 Timer B Control Register 0 (TMBCON0) .................................................................................. 8-21
8.2.18 Timer E Control Register 0 (TMECON0) .................................................................................. 8-22
8.2.19 Timer F Control Register 0 (TMFCON0) .................................................................................. 8-23
8.2.20 Timer 8 Control Register 1 (TM8CON1) ................................................................................... 8-24
8.2.21 Timer 9 Control Register 1 (TM9CON1) ................................................................................... 8-25
8.2.22 Timer A Control Register 1 (TMACON1) .................................................................................. 8-26
8.2.23 Timer B Control Register 1 (TMBCON1) .................................................................................. 8-27
8.2.24 Timer E Control Register 1 (TMECON1) .................................................................................. 8-28
8.2.25 Timer F Control Register 1 (TMFCON1) .................................................................................. 8-29
8.2.26 Timer E Control Register 2 (TMECON2) .................................................................................. 8
8.2.27 Timer F Control Register 2 (TMFCON2) .................................................................................. 8-31
8.2.28 Timer E Control Register 3 (TMECON3) .................................................................................. 8-33
8.2.29 Timer F Control Register 3 (TMFCON3) .................................................................................. 8-34
8.3 Description of Operation ...................................................................................................................... 8-35
8.3.1 Timer basic operation ................................................................................................................. 8-35
8.3.2 The external timer start/stop operation ....................................................................................... 8-37
8.3.3 The external timer operation ...................................................................................................... 8-37
8.4 Restriction of timer .............................................................................................................................. 8-39
8.4.1 Restriction 1 ............................................................................................................................... 8-39
8.4.1 Restriction 2 ............................................................................................................................... 8-39
8.4.1 Restriction 3 ............................................................................................................................... 8-39
8.5 Specifying port registers ...................................................................................................................... 8-40
8.5.1 Functioning PA0 (TM9OUT) as the timer output ...................................................................... 8-40
8.5.2 Functioning PC3 (TMFOUT) as the timer output ...................................................................... 8-41
Chapter 9
Contents
-30
9 W at chdog T imer .......................................................................................................................................... 9-1
9.1 Overview ................................................................................................................................................ 9-1
9.1.1 Features ........................................................................................................................................ 9-1
FEUL610Q111 Contents - 3
ML610Q111/ML610Q112 User’s Manual
9.1.2 Configuration ................................................................................................................................ 9-1
9.2 Description of Registers ......................................................................................................................... 9-2
9.2.1 List of Registers ............................................................................................................................ 9-2
9.2.2 Watchdog Timer Control Register (WDTCON) ........................................................................... 9-3
9.2.3 Watchdog Timer Mode Register (WDTMOD) ............................................................................. 9-4
9.3 Description of Operation ........................................................................................................................ 9-5
9.3.1 Handling example when you do not want to use the watchdog timer .......................................... 9-7
Chapter 10
10 PWM.......................................................................................................................................................... 10-1
10.1 Overview .............................................................................................................................................. 10-1
10.1.1 Features ...................................................................................................................................... 10-1
10.1.2 Configuration .............................................................................................................................. 10-2
10.1.3 List of Pins.................................................................................................................................. 10-3
10.2 Description of Registers ....................................................................................................................... 10-4
10.2.1 List of Registers .......................................................................................................................... 10-4
10.2.2 PWM C Period Registers (PWC PL, PWC PH) ............................................................................ 10-5
10.2.3 PWM C Duty Registers (PWCDL, PWCDH) ............................................................................. 10-6
10.2.4 PWM C Counter Registers (PWCCH, PWC CL ) ......................................................................... 10-7
10.2.5 PWMC Control Register 0 (PWCCON0) ................................................................................... 10-8
10.2.6 PWMC Control Register 1 (PWCCON1) ................................................................................... 10-9
10.2.7 PWMC Control Register 2 (PWCCON2) ................................................................................. 10-10
10.2.8 PWMC Control Register 3 (PWCCON3) ................................................................................. 10-11
10.2.9 PWM D Period Registers (PWCPL, PWCPH) .......................................................................... 10-12
10.2.10 PWMD Duty Registers (PWDDL, PWDDH) .......................................................................... 10-13
10.2.11 PWMD Counter Registers (PWDCH, PWDCL) ...................................................................... 10-14
10.2.12 PWMD Control Register 0 (PWDCON0) ................................................................................ 10-15
10.2.13 PWMD Control Register 1 (PWDCON1) ................................................................................ 10-16
10.2.14 PWMD Control Register 2 (PWDCON2) ................................................................................ 10-17
10.2.15 PWMD Control Register 3 (PWDCON3) ................................................................................ 10-18
10.2.16 PWME Period Registers (PWEPL, PWEPH) ........................................................................... 10-19
10.2.17 PWME Duty Registers (PWEDL, PWEDH) ............................................................................ 10-20
10.2.18 PWME Counter Registers (PWECH, PWECL) ....................................................................... 10-21
10.2.19 PWME Control Register 0 (PWECON0) ................................................................................. 10-22
10.2.20 PWME Control Register 1 (PWECON1) ................................................................................. 10-23
10.2.21 PWME Control Register 2 (PWECON2) ................................................................................. 10-24
10.2.22 PWME Control Register 3 (PWECON3) ................................................................................. 10-25
10.2.23 PWMF Period Registers (PWFPL, PWFPH) ........................................................................... 10-26
10.2.24 PWMF0 Duty Registers (PWF0DL, PWF0DH) ...................................................................... 10-27
10.2.25 PWMF1 Duty Registers (PWF1DL, PWF1DH) ...................................................................... 10-28
10.2.26 PWMF2 Duty Registers (PWF2DL, PWF2DH) ...................................................................... 10-29
10.2.27
10.2.28 PWMF Control Register 0 (PWFCON0) .................................................................................. 10-31
10.2.29 PWMF Control Register 1 (PWFCON1) .................................................................................. 10-32
10.2.30 PWMF Control Register 2 (PWFCON2) .................................................................................. 10-33
10.2.31 PWMF Control Register 3 (PWFCON3) .................................................................................. 10-34
10.2.32 PWMF Control Register 4 (PWFCON4) .................................................................................. 10-35
10.2.33 PWMF Control Register 5 (PWFCON5) .................................................................................. 10-36
10.3 Description of Operation .................................................................................................................... 10-37
10.3.1 Start, Stop, and Clear Operations of PWM by External Input Control ..................................... 10-39
10.3.2 Emergency Stop Operation ....................................................................................................... 10-39
10.3.3 PWMF Operation ..................................................................................................................... 10-40
10.3.4 Interrupt of PWM ..................................................................................................................... 10-42
10.4 Specifying port registers .................................................................................................................... 10-43
10.4.1 Functioning PA0 (PWMC) as the PWM output ....................................................................... 10-43
10.4.2 Functioning PB0 (PWMC) as the PWM output ....................................................................... 10-44
10.4.3 Functioning PB7 (PWMC) as the PWM output ....................................................................... 10-45
PWMF Counter Registers (PWFCH, PWFCL) ........................................................................ 10-30
Contents
FEUL610Q111 Contents - 4
ML610Q111/ML610Q112 User’s Manual
Chapter 11
11 Synchronous Serial Port ............................................................................................................................ 11-1
11.1 Overview .............................................................................................................................................. 11-1
11.1.1 Features ...................................................................................................................................... 11-1
11.1.2 Configuration .............................................................................................................................. 11-1
11.1.3 List of Pins.................................................................................................................................. 11-2
11.2 Description of Registers ....................................................................................................................... 11-3
11.2.1 List of Registers .......................................................................................................................... 11-3
11.2.2 Serial Port Transmit/Receive Buffers (SIO0BUFL, SIO0BUFH) .............................................. 11-4
11.2.3 Serial Port Control Register (SIO0CON) ................................................................................... 11-5
11.2.4 Serial Port Mode Register 0 (SIO0MOD0) ................................................................................ 11-6
11.2.5 Serial Port Mode Register 1 (SIO0MOD1) ................................................................................ 11-7
11.3 Description of Operation ...................................................................................................................... 11-8
11.3.1 Transmit Operation ..................................................................................................................... 11-8
11.3.2 Receive Operation ...................................................................................................................... 11-9
11.3.3 Transmit/Receive Operation ..................................................................................................... 11-10
11.4 Specifying port registers .................................................................................................................... 11-11
11.4.1 Functioning as the SSIO master mode ..................................................................................... 11-11
11.4.2 Functioning as the SSIO slave mode ........................................................................................ 11-12
Chapter 12
Contents
12 UART ........................................................................................................................................................ 12-1
12.1 Overview ............................................................................................................................................ 12-1
12.1.1 Features ...................................................................................................................................... 12-1
12.1.2 Configuration .............................................................................................................................. 12-1
12.1.3 List of Pins.................................................................................................................................. 12-2
12.2 Description of Registers ..................................................................................................................... 12-2
12.2.1 List of Registers .......................................................................................................................... 12-2
12.2.2 UART0 Transmit/Receive Buffer (UA0BUF) ............................................................................ 12-3
12.2.3 UART1 Transmit/Receive Buffer (UA1BUF) ............................................................................ 12-3
12.2.4 UART0 Control Register (UA0CON) ........................................................................................ 12-4
12.2.5 UART1 Control Register (UA1CON) ........................................................................................ 12-4
12.2.6 U ART0 Mode Register 0 (UA0MOD0) ..................................................................................... 12-5
12.2.7 U ART1 Mode Register 0 (UA1MOD0) ..................................................................................... 12-6
12.2.8 U ART0 Mode Register 1 (UA0MOD1) ..................................................................................... 12-7
12.2.9 U ART1 Mode Register 1 (UA1MOD1) ..................................................................................... 12-8
12.2.10 UART0 Baud Rate Registers L, H (UA0BRTL, UA0BRTH) .................................................... 12-9
12.2.11 UART1 Baud Rate Registers L, H (UA1BRTL, UA1BRTH) .................................................. 12-10
12.2.12 UART0 Status Register (UA0STAT) ........................................................................................ 12-11
12.2.13 UART1 Status Register (UA1STAT) ........................................................................................ 12-12
12.3 Description of Operation .................................................................................................................. 12-13
12.3.1 Transfer Data Format ................................................................................................................ 12-13
12.3.2 Baud rate................................................................................................................................... 12-14
12.3.3 Transmitted Data Direction ...................................................................................................... 12-15
12.3.4 Transmit Operation ................................................................................................................... 12-16
12.3.5 Receive Operation .................................................................................................................... 12-17
12.3.5.1 Detection of Start Bit ................................................................................................................... 12-18
12.3.5.2 Sampling Timing ......................................................................................................................... 12-18
12.3.5.3 Reception Margin ........................................................................................................................ 12-19
12.4 Specifying port registers ................................................................................................................... 12-20
12.4.1 Functioning PB1(TXD0) and PB0(RXD0) as the UART ......................................................... 12-20
12.4.2 Functioning PB4(TXD0) and PB5(RXD0) as the UART ......................................................... 12-21
12.4.3 Functioning PB1(TXD1) and PB2(RXD1) as the UART ......................................................... 12-22
12.4.4 Functioning PB3(TXD1) and PB2(RXD1) as the UART ................................
12.4.5 Functioning PB4(TXD1) and PB2(RXD1) as the UART ......................................................... 12-24
12.4.6 Functioning PB1(TXD1) and PB7(RXD1) as the UART ......................................................... 12-25
12.4.7 Functioning PB3(TXD1) and PB7(R XD1) as the UART ......................................................... 12-26
12.4.8 Functioning PB4(TXD1) and PB7(RXD1) as the UART ......................................................... 12-27
......................... 12-23
FEUL610Q111 Contents - 5
ML610Q111/ML610Q112 User’s Manual
Chapter 13
13 I2C Bus Interface Master ........................................................................................................................... 13-1
13.1 Overview .............................................................................................................................................. 13-1
13.1.1 Features ...................................................................................................................................... 13-1
13.1.2 Configuration .............................................................................................................................. 13-1
13.1.3 List of Pins.................................................................................................................................. 13-1
13.2 OverviewDescription of Registers ....................................................................................................... 13-2
13.2.1 List of Registers .......................................................................................................................... 13-2
13.2.2 I2C Bus 0 Receive Register (I2C0RD) ....................................................................................... 13-3
13.2.3 I2C Bus 0 Slave Address Register (I2C0SA) ............................................................................. 13-4
13.2.4 I2C Bus 0 Transmit Data Register (I2C0TD) ............................................................................. 13-5
13.2.5 I2C Bus 0 Control Register (I2C0CON) .................................................................................... 13-6
13.2.6 I2C Bus 0 Mode Register (I2C0MOD) ...................................................................................... 13-7
13.2.7 I2C Bus 0 Status Register (I2C0STAT) ...................................................................................... 13-8
13.3 Description of Operation ...................................................................................................................... 13-9
13.3.1 Communication Operating Mode ............................................................................................... 13-9
13.3.1.1 Start Condition ............................................................................................................................... 13-9
13.3.1.2 Repeated Start Condition ............................................................................................................... 13-9
13.3.1.3 Slave Address Transmit Mode ....................................................................................................... 13-9
13.3.1.4 Data Transmit Mode ...................................................................................................................... 13-9
13.3.1.5 Data Receive Mode ....................................................................................................................... 13-9
13.3.1.6 Control Register Setting Wait State ............................................................................................... 13-9
13.3.1.7 Stop Condition ............................................................................................................................... 13-9
13.3.2 Com m unication Operation Timing ........................................................................................... 13-10
13.3.3 Operati on Waveforms ............................................................................................................... 13-12
13.4 Specifying port registers .................................................................................................................... 13-13
13.4.1 Functioning PB5(SCL) and PB6(SDA) as the I2C................................................................... 13-13
Chapter 14
Contents
14 I2C Bus Interface Slave ............................................................................................................................. 14-1
14.1 Overview .............................................................................................................................................. 14-1
14.1.1 Features ...................................................................................................................................... 14-1
14.1.2 Configuration .............................................................................................................................. 14-1
14.1.3 List of Pins.................................................................................................................................. 14-2
14.2 Description of Registers ....................................................................................................................... 14-3
14.2.1 List of Registers .......................................................................................................................... 14-3
14.2.2 I2C Bus 1 Receive Register (I2C1RD) ....................................................................................... 14-4
14.2.3 I2C Bus 1 Slave Address Register (I2C1SA) ............................................................................. 14-5
14.2.4 I2C Bus 1 Transmit Data Register (I2C1TD) ............................................................................. 14-6
14.2.5 I2C Bus 1 Control Register (I2C1CON) .................................................................................... 14-7
14.2.6 I2C Bus 1 Mode Register (I2C1MOD) ...................................................................................... 14-8
14.2.7 I2C Bus 1 Status Register (I2C1STAT) ...................................................................................... 14-9
14.3 Description of Operation .................................................................................................................... 14-11
14.3.1 Communication Operating Mode ............................................................................................. 14-11
14.3.1.1 Start Condition .............................................................................................................................. 14-11
14.3.1.2 Slave Address Receive Mode ....................................................................................................... 14-11
14.3.1.3 Communication Wait State ........................................................................................................... 14-11
14.3.1.4 Data Transmit Mode ..................................................................................................................... 14-11
14.3.1.5 Data Receive Mode ...................................................................................................................... 14-11
14.3.1.6 Stop Condition .............................................................................................................................. 14-11
14.3.2 Com m unication Operation Timing ........................................................................................... 14-12
14.3.3 Operati on Waveforms ............................................................................................................... 14-13
14.4 Specifying port registers .................................................................................................................... 14-14
14.4.1 Functioning PB5(SCL) and PB6(SDA) as the I2C................................................................... 14-14
Chapter 15
15 Port A ......................................................................................................................................................... 15-1
15.1 Overview .............................................................................................................................................. 15-1
15.1.1 Features ...................................................................................................................................... 15-1
FEUL610Q111 Contents - 6
ML610Q111/ML610Q112 User’s Manual
15.1.2 Configuration .............................................................................................................................. 15-2
15.1.3 List of Pins.................................................................................................................................. 15-3
15.2 Description of Registers ....................................................................................................................... 15-4
15.2.1 List of Registers .......................................................................................................................... 15-4
15.2.2 Port A Data Register (PAD) ........................................................................................................ 15-5
15.2.3 Port A Direction Register (PADIR) ............................................................................................ 15-6
15.2.4 Port A Control Registers 0, 1 (PACON0, PACON1) .................................................................. 15-7
15.2.5 Port A Mode Registers 0 (PAMOD0, PAMOD1)) ...................................................................... 15-8
15.3 Description of Operation ...................................................................................................................... 15-9
15.3.1 Input/Output Port Functions ....................................................................................................... 15-9
15.3.2 Primary Function except for Input/Output Port .......................................................................... 15-9
15.3.3 Secondary tertiary and fourthly functions .................................................................................. 15-9
Chapter 16
16 Port B ......................................................................................................................................................... 16-1
16.1 Overview .............................................................................................................................................. 16-1
16.1.1 Features ...................................................................................................................................... 16-1
16.1.2 Configuration .............................................................................................................................. 16-2
16.1.3 List of Pins.................................................................................................................................. 16-3
16.2 Description of Registers ....................................................................................................................... 16-4
16.2.1 List of Registers .......................................................................................................................... 16-4
16.2.2 Port B Data Register (PBD) ....................................................................................................... 16-5
16.2.3 Port B Direction Register (PBDIR) ............................................................................................ 16-6
16.2.4 Port B Control Registers 0, 1 (PBCON0, PBCON1) .................................................................. 16-7
16.2.5 Port B Mode Registers 0 (PBMOD0, PBMOD1) ....................................................................... 16-9
16.3 Description of Operation .................................................................................................................... 16-11
16.3.1 Input/Output Port Functions ..................................................................................................... 16-11
16.3.2 Primary Function except for Input/Output Port ........................................................................ 16-11
16.3.3 Secondary tertiary and fourthly functions ................................................................................ 16-11
Chapter 17
Contents
17 Port C ......................................................................................................................................................... 17-1
17.1 Overview .............................................................................................................................................. 17-1
17.1.1 Features ...................................................................................................................................... 17-1
17.1.2 Configuration .............................................................................................................................. 17-2
17.1.3 List of Pins.................................................................................................................................. 17-3
17.2 Description of Registers ....................................................................................................................... 17-4
17.2.1 List of Registers .......................................................................................................................... 17-4
17.2.2 Port C Data Register (PCD) ....................................................................................................... 17-5
17.2.3 Port C Direction Register (PCDIR) ............................................................................................ 17-6
17.2.4 Port C Control Registers 0, 1 (PCCON0, PCCON1) .................................................................. 17-7
17.2.5 Port C Mode Registers 0 (PCMOD0, PCMOD1) ....................................................................... 17-9
17.3 Description of Operation .................................................................................................................... 17-11
17.3.1 Input/Output Port Functions ..................................................................................................... 17-11
17.3.2 Primary Function except for Input/Output Port ........................................................................ 17-11
17.3.3 Secondary tertiary and fourthly functions ................................................................................ 17-11
Chapter 18
18 Port D......................................................................................................................................................... 18-1
18.1 Overview .............................................................................................................................................. 18-1
18.1.1 Features ...................................................................................................................................... 18-1
18.1.2 Configuration .............................................................................................................................. 18-1
18.1.3 List of Pins.................................................................................................................................. 18-2
18.2 Description of Registers ....................................................................................................................... 18-3
18.2.1 List of Registers .......................................................................................................................... 18-3
18.2.2 Port D Data Register (PDD) ....................................................................................................... 18-4
18.2.3 Port D Direction Register (PDDIR)............................................................................................ 18-5
18.2.4 Port D Control Registers 0, 1 (PDCON0, PDCON1) ................................................................. 18-6
FEUL610Q111 Contents - 7
ML610Q111/ML610Q112 User’s Manual
18.3 Description of Operation ...................................................................................................................... 18-8
18.3.1 Input/Output Port Functions ....................................................................................................... 18-8
Chapter 19
19 Port AB Interrupts ...................................................................................................................................... 19-1
19.1 Overview .............................................................................................................................................. 19-1
19.1.1 Features ...................................................................................................................................... 19-1
19.1.2 Configuration .............................................................................................................................. 19-1
19.2 Description of Registers ....................................................................................................................... 19-1
19.2.1 List of Registers .......................................................................................................................... 19-1
19.2.2 Port AB Interrupt Control Registers 0, 1 (PABICON0, PABICON1) ........................................ 19-2
19.2.3 Port AB Interrupt Control Register 2 (PABICON2) ................................................................... 19-3
19.3 Description of Operation ...................................................................................................................... 19-4
19.3.1 Interrupt Request ........................................................................................................................ 19-4
Chapter 20
20 Successive Approximation Type A/D Converter ....................................................................................... 20-1
20.1 Overview .............................................................................................................................................. 20-1
20.1.1 Features ...................................................................................................................................... 20-1
20.1.2 Configuration .............................................................................................................................. 20-1
20.1.3 List of Pins.................................................................................................................................. 20-2
20.2 Description of Registers ....................................................................................................................... 20-3
20.2.1 List of Registers .......................................................................................................................... 20-3
20.2.2 SA-ADC Result Register 0L (SADR0L) .................................................................................... 20-4
20.2.3 SA-ADC Result Register 0H (SADR0H) ................................................................................... 20-4
20.2.4 SA-ADC Result Register 1L (SADR1L) .................................................................................... 20-5
20.2.5 SA-ADC Result Register 1H (SADR1H) ................................................................................... 20-5
20.2.6 SA-ADC Result Register 2L (SADR2L) .................................................................................... 20-6
20.2.7 SA-ADC Result Register 2H (SADR2H) ................................................................................... 20-6
20.2.8 SA-ADC Result Register 3L (SADR3L) .................................................................................... 20-7
20.2.9 SA-ADC Result Register 3H (SADR3H) ................................................................................... 20-7
20.2.10 SA-ADC Result Register 4L (SADR4L) .................................................................................... 20-8
20.2.11 SA-ADC Result Register 4H (SADR4H) ................................................................................... 20-8
20.2.12 SA-ADC Result Register 5L (SADR5L) .................................................................................... 20-9
20.2.13 SA-ADC Result Register 5H (SADR5H) ................................................................................... 20-9
20.2.14 SA-ADC Result Register 6L (SADR6L) .................................................................................. 20-10
20.2.15 SA-ADC Result Register 6H (SADR6H) ................................................................................. 20-10
20.2.16 SA-ADC Result Register 7L (SADR7L) .................................................................................. 20-11
20.2.17 SA-ADC Result Register 7H (SADR7H) ................................................................................. 20-11
20.2.18 SA-ADC Control Register 0 (SADCON0) ............................................................................... 20-12
20.2.19 SA-ADC Control Register 1 (SADCON1) ............................................................................... 20-13
20.2.20 SA-ADC Mode Register 0 (SADMOD0) ................................................................................. 20-14
20.3 Description of Operation .................................................................................................................... 20-16
20.3.1 Settings of A/D Conversion Channels ...................................................................................... 20-16
20.3.2 Operation of the Successive Approximation A/D Converter .................................................... 20-17
Chapter 21
Contents
21 Voltage Level Supervisor ........................................................................................................................... 21-1
21.1 Overview .............................................................................................................................................. 21-1
21.1.1 Features ...................................................................................................................................... 21-1
21.1.2 Configuration .............................................................................................................................. 21-1
21.2 Description of Registers ....................................................................................................................... 21-2
21.2.1 List of Registers .......................................................................................................................... 21-2
21.2.2 Voltage Level Supervisor Control Register 0 (VLSCON0) ........................................................ 21-3
21.2.3 Voltage Level Supervisor Control Register 1 (VLSCON1) ........................................................ 21-4
21.2.4 Voltage Level Supervisor Mode Register (VLSMOD) ............................................................... 21-5
21.3 Description of Operation ...................................................................................................................... 21-6
21.3.1 Operation of Voltage Level Supervisor ...................................................................................... 21-6
FEUL610Q111 Contents - 8
ML610Q111/ML610Q112 User’s Manual
Chapter 22
22 Analog Comparator ................................................................................................................................... 22-1
22.1 Overview .............................................................................................................................................. 22-1
22.1.1 Features ...................................................................................................................................... 22-1
22.1.2 Configuration .............................................................................................................................. 22-1
22.1.3 List of Pins.................................................................................................................................. 22-2
22.2 Description of Registers ....................................................................................................................... 22-2
22.2.1 List of Registers .......................................................................................................................... 22-2
22.2.2 Comparator 0 control register 0 (CMP0CON0) ......................................................................... 22-3
22.2.3 Comparator 0 control register 1 (CMP0CON1) ......................................................................... 22-4
22.2.4 Comparator 0 control register 2 (CMP0CON2) ......................................................................... 22-5
22.2.5 Comparator 1 control register 0 (CMP1CON0) ......................................................................... 22-6
22.2.6 Comparator 1 control register 1 (CMP1CON1) ......................................................................... 22-7
22.2.7 Comparator 1 control register 2 (CMP1CON2) ......................................................................... 22-8
22.3 Description of Operation ...................................................................................................................... 22-9
22.3.1 Comparator Functions ................................................................................................................ 22-9
22.3.2 Interrupt Request ...................................................................................................................... 22-10
Chapter 23
Contents
23 Data Flash Memory ................................................................................................................................... 23-1
23.1 Overview .............................................................................................................................................. 23-1
23.1.1 Features ...................................................................................................................................... 23-1
23.2 Description of Registers ....................................................................................................................... 23-2
23.2.1 List of Registers .......................................................................................................................... 23-2
23.2.2 Flash Address Register (FLASHAL,H) ...................................................................................... 23-3
23.2.3 Flash Data Register (FLASHDL,H) ........................................................................................... 23-4
23.2.4 Flash Control Register (FLASHCON) ....................................................................................... 23-5
23.2.5 F lash Accepter (FLASHACP) .................................................................................................... 23-6
23.2.6 Flash Segment Register (FLASHSEG) ...................................................................................... 23-7
23.2.7 Flash Self Register (FLASHSLF)............................................................................................... 23-7
23.2.8 Flash Protection Register (FLASHPRT) .................................................................................... 23-8
23.2.9 Flash Erase Abort Source Select Register (FLASHEAS) ......................................................... 23-10
23.2.10 Flash Erase Status Register (FLASHEST) ............................................................................... 23-11
23.3 Description of Operation .................................................................................................................... 23-12
23.3.1 Sector Erase Function ............................................................................................................... 23-13
23.3.2 Block Erase F unct ion ............................................................................................................... 23-15
23.3.3 1-W ord Write Function ............................................................................................................. 23-17
23.3.4 Notes in Use ............................................................................................................................. 23-19
Chapter 24
24 On-Chip Debug Function .......................................................................................................................... 24-1
24.1 Overview .............................................................................................................................................. 24-1
24.2 Method of Connecting to On-Chip Debug Emulator ........................................................................... 24-1
Appendix
Appendix A Registers ....................................................................................................................................... A-1
Appendix B Package ........................................................................................................................................ B-1
Appendix C Electrical ...................................................................................................................................... C-1
Appendix D Application Circuit Example ........................................................................................................ D-1
Appendix E Check List ..................................................................................................................................... E-1
Revision History
Revision History ............................................................................................................................................... R-1
FEUL610Q111 Contents - 9
Chapter 1
Overview
1 Overview
1.1 Features
ML610Q111/ML610Q112 User’s Manual
Chapter 1 Overview
This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circ uits, such as timers, PWM ,
UART, I
successive approximation type A/D converter, are incorporated around 8-bit CPU nX-U8/100.
The CPU nX-U8/1 00 is capable of efficient instruction execution in 1-intruction 1-clock mode by pipe line architecture
parallel processing. It has a data-flash memory that can be written by software.
The on-chip debug function that is ins t alled enables program debugging and programming.
2
C bus interface (master/slave), synchronous seria l port, voltage level supervisor (VLS) functi on, and 10-bit
• CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system : 16-bit instructions
− Instruction set :
Transfer, arithmetic operations, comparison, logic oper ations, multiplication/division, bit manipulations, bit logic
operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
− On-Chip debug function
− Minimum instruction execution time
30.5µs (@32.768kHz system clock)
0.122µs (@8.192MHz system clock)
• Internal memory
− ML610Q111 :
Flash memory (Program memory) : 24Kbyte (12K×16 bits) * including unusable 32 byte test data area.
Data flash memory : 4Kbyte (2 K ×16 bits)
RAM : 2Kbyte (2K×8 bits)
− ML610Q112 :
Flash memory (Program memroy) : 32Kbyte (16K×16 bits) * including unusable 32 byte test data area.
Data flash memory : 4Kbyte (2 K ×16 bits)
RAM : 4Kbyte (4K×8 bits)
• Interrupt controller
− 1 non-maskable interrupt source (Internal source: 1)
− 30 maskable interrupt sources (Internal sources: 23, External sources: 7)
• Time base counter (TBC)
− Low-speed time base counter × 1 channel
− High-speed time base counter × 1 channel
(This time base counter is divided by 1-16, then it can be used as a clock of the Timer and PWM.)
• Watchdog timer (WDT)
− Non-maskable interrupt and reset
(Non-maskable interrupt is generated by the first overflow, and reset is generated by the second overflow)
− Free running
− Overflow period: 7 types selectable by software (23.4ms, 31.25ms, 62.5ms, 125ms, 500ms, 2s, and 8s)
FEUL610Q111 1-1
• Timer
− 8 bits × 6 channels (16-bit configuration available )
− Supports continuous mode/one shot mode
− Timer start/stop function by software or external trigger i nput
(Timer function with external trigger input supports for only 2ch. Selectable external pins/analog comparator
output as an exe ternal trigger.)
− The effective minimum pulse width of the external trigger input: Timer clock 3φ (about 183 ns @ 16.384 MHz)
− Allows measurement of pulse width etc. using a n external trigger i nput.
• PWM
− Resolution 16 bits × 4 channels
− Allows an output of the PWM signal in a cycle of about 122ns (@PLLCLK = 16.384MHz) to 2s (@LSCLK =
32.768kHz)
− Supports continuous mode/one shot mode
− PWM start/stop function by software or external trigger i nput
(Selectable external pins, analog comparator output or timer interrupt a s exter nal tr igger. )
− The effective minimum pulse width of the external trigger input: Timer clock 3φ (about 183 ns @ 16.384MHz)
• UART
− TXD/RXD × 2 channels
− Half-duplex
− Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop b its
− Positive logic/negative logic selectable
− Built-in baud rate generator
2
C Bus Interface
• I
− Master function: Standard mode (100 kbits/s @ 8 MHz), First mode (400 kbits/s @ 8 MHz)
− Slave function: Standard mode (100 kbits/s)
• Synchronous Serial Port (SSIO)
− Master/slave selectable
− LSB first/MSB first selectable
− 8-bit length/16-bit length selectable
− Support SPI mode 0/3
• Successive approximation type A/D converter (SA-ADC)
− Resolution 10-bit
− ML610Q111: Analog Input : 6channels
− ML610Q112: Analog Input : 8channels
− Conversion time : Approx 12.45μs/ch＠8.192MHz
− Single conversion/continuous conversion selectable
• Analog Comparator
− 2ch
ch0: Allows comparison of the voltage level of the two external pins or comparison of one external pin and
internal reference voltage level.
ch1: Allows comparison of one external pin and internal reference voltage level.
− Common mode input voltage range : V
− Internal reference voltage : 0.1-0.8V (Selectable in 50mV increments)
− Hysteresis (Comparator0 only): 20mV(Typ.)
− Allows selection of with/without interrup t s ampling and interrup t edge.
• General-purpose ports (GPIO)
− ML610Q111 : Input/output port × 15 channels
− ML610Q112 : Input/output port × 25 channels
= 0.1V to VDD - 1.5V
DD
ML610Q111/ML610Q112 User’s Manual
Chapter 1 Overview
FEUL610Q111 1-2
• Reset
− Reset by the RESET_N pin
− Reset by power-on
− Reset by the watchdog timer (WDT) 2nd overflow
− Reset by voltage level supervisor (VLS) function: Selectab le by software
• Voltage level supervisor (VLS)
− 2ch
− Judgment accuracy: ±3.0% (Typ.)
− The threshold voltages of VLS 0 : (V
− The threshol d voltages of VLS1 (V
− The VLS0 can be used as the low voltage level detector reset.
• Clock
− Low-speed clock:
Built-in RC oscillation (32.768 kHz)
− High-speed clock:
Built-in PLL oscillation (16.384 MHz), external clock(max. 8.192MHz)
* The clock of the CPU is 8.192MHz(max.)
− Selection of high-speed clock mode by software:
Built-in PLL oscillation, external clock
• Power management
− HALT mode : Instruction execution by CPU is suspended (peripheral circuits are in operating states).
− STOP mode : Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits
are stopped.)
− Clock gear : The fr equency of high-speed system clock can be changed by software (1/1, 1/2, 1/4 or 1/8 of the
oscillation clock)
− Block Control Function : Power down (reset registers and stop clock supply) the circuits of unused peripherals.
• Shipment
− ML610Q111 :
20-pin TSSOP
ML610Q111-xxxTD (Blank product: ML610Q111-NNNTD)
− ML610Q112 :
32-pin LQFP
ML610Q112-xxxTC (Blank prod uct: ML610Q112-NNNTC)
• Guaranteed operating range
− Operating ambient temperature: −40°C to 105°C ( When the flash memory writing/erasi ng : −20°C to 85°C)
− Operating voltage: V
= 2.7V to 5.5V
DD
ML610Q111/ML610Q112 User’s Manual
fall) : 2.85V (Typ. ) (VDD rise) : 2.92V (Typ. )
DD
fall) : 4 types selectable 3.3V/ 3.6V/ 3.9V/ 4.2V (Typ.)
DD
Chapter 1 Overview
FEUL610Q111 1-3
Program
RXD0
TXD0*
CPU (nX-U8/100)
EA
SP
Instruction
BUS
Instruction
INT
PA0 to PA2
PB0 to PB7
Data-bus
RESET &
ALU
PSW
LR
DSR/CSR
PC
VDD
AIN0
SDA*
SCK*
SOUT*
SIN*
(PC4 to PC7)
*2
CMP0P
CMP0M
CMP1OUT*
CMP1P
RESET_N
INT 1 RXD1
TXD1*
RESET_N
INT
1
CMP0OUT*
INT
2
10bit-ADC
Analog
Clock
VLS
1
INT
4
INT 6 INT 2 INT
2
RAM
8bit Timer
SCL*
INT 1 PWMC*
PWMD*
PWME*
PWMF0*
PWMF1*
PWMF2*
INT 4 INT
7
GPIO
I2C
SSIO
PC0 to PC3
(PD0 to PD5)
*2
1.2 Configuration of Functional Blocks
1.2.1 Block Diagram
Figure 1-1 show the bl ock diagram of the LSI.
"*" indicates secondary function, tertiary function o r quaternary function of each port.
*2
" indicates the specification of ML610Q112.
" ( )
TEST
V
SS
TEST
to
AIN5(AIN7)
*2
EPSW1-3
Timing
Controller
On-Chip
ICE
Power
TEST
Generator
Comparator
x 2
GREG
0 - 15
Decoder
ELR1-3
Register
Data
Memory
(Flash)
4Kbyte
2Kbyte
(4Kbyte)
Interrupt
Controller
WDT
TBC
x 6
*2
ECSR1-3
Controller
ML610Q111/ML610Q112 User’s Manual
Chapter 1 Overview
Memory
(Flash)
24Kbyte
UART
PWM
*2
(32Kbyte)
Master/Slave
Figure 1-1 ML610Q111/ML610Q112 Block Diagram
FEUL610Q111 1-4
1.3 Pins
PA0 / EXI0 / AIN0 / PWMC
RESET_N
PC1 / PWMF1
PC5 / SDA
PC4 / SCL
PC0 / PWMF0 / TM9OUT
PD5
PWMF2 / PC2
PD4
PD3
TMFOUT / PC3
PD2
CMP1P / AIN1 / EXI1 / PA1
PWMD /
PB3 / EXI7 / SIN / TXD1
PB2 / EXI6 / RXD1 / PWME
PB1 / EXI5 / AIN3 / PWMD / TXD0 / TXD1
N.C.
PB0 / EXI4 / AIN2 / RXD0 / PWMC / OUTCLK / CMP1OUT
PD1
TEST
3
4
6
7
PA2 / EXI2 / PWME / CLKIN / CMP0OUT
PWMF1 / SDA / CLKIN / AIN4 / PB6
N.C.
V
SS
V
DD
AIN7 / PC7
23
21
20
19
18
17
TXD1 / TXD0 / SOUT / CMP0P / PB4
PWMF2 / SCL / SCK / RXD0 / CMP0M / PB5
PWMC / PWMF0 / LSCLK / RXD1 / AIN5 / PB7
CMP0OUT / CLKIN / PWME / EXI2 / PA2
2 3 4 5 6
7
8
9
10
RESET_N
TEST
TXD1 / TXD0 / PWMD / AIN3 / EXI5 / PB1
PWME / RXD1 / EXI6 / PB2
TXD1 / SIN / EXI7 / PB3
TESTF
TMFOUT / PC3
CMP1OUT / OUTCLK / PWMC / RXD0 / AIN2 / EXI4 / PB0
TM9OUT / PWMF0 / PC0
20
PC1 / PWMF1
PA0 / EXI0 / AIN0 / PWMC / OUTCLK / TM9OUT
PB7 / AIN5 / RXD1 / LSCLK / PWMF0 / PWMC
VDD
VSS
PB6 / AIN4 / CLKIN / SDA / PWMF1
PB5 / CMP0M / RXD0 / SCK / SCL / PWMF2
PB4 / CMP0P / SOUT / TXD0 / TXD1
PA1 / EXI1 / AIN1 / CMP1P / PWMD / LSCLK / TMFOUT
PC2 / PWMF2
1.3.1 Pin Layout
Figure 1-2 show the TSSOP20 pin layout of the ML610Q111.
ML610Q111/ML610Q112 User’s Manual
Chapter 1 Overview
1
* PIN No.4-8, 12-15, 18, 19 can be used as external trigger of the Timer E-F and PWMC-F.
Figure 1-2 Pin Layout of ML610Q111 TSSOP20 Package
Figure 1-3 show the LQFP32 pin layout of the ML610Q112.
TMFOUT / LSCLK /
19
18
17
16
15
14
13
12
11
TESTF
FEUL610Q111 1-5
* PIN No.3, 5-8, 16-19, 24, 25 can be used as external trigger of the Timer E- F and PWMC-F.
Figure 1-3 Pin Layout of ML610Q112 LQFP32 Package
22
24
15 14 13 12 11 10 9
16
27 28 29 30 31 32 25
26
/ OUTCLK / TM9OUT
PC6 / AIN6
8
5
2
1
PD0
ML610Q111/ML610Q112 User’s Manual
PIN No.
Primary function
Secondary function
Tertiary function
quaternary function
Pin
name
Pin
name
Descrip
tion
Pin
name
Descrip
tion
Pin
name
Descrip
tion
Negative power
supply pin
Positive power
supply pin
Test for Flash
memory
32 2 RESE T_N
I
Reset input pin
Input/output pin for
High-
output
Input/output port /
1 non-inverted input
External t ri gger
Input/output port /
External trigger
Input/output port /
External trigger
Input/output port /
External trigger
SSIO
input
UART1
output
External trigger
Input/output port /
External trigger
Input/output port /
External trigger
PWMF
output
Input/output port /
External trigger
Chapter 1 Overview
1.3.2 List of Pins
Table 1-1 shows list of pins.
In the I/O column, “—” denotes a power supply pin, “I” an input pin, “O” an output pin, and “I/O” an input/output pin.
Table 1-1 List of pins
32
LQFP
20
TSSOP
I/O Description
I/O
I/O
I/O
21 16 VSS
22 17 VDD
9 9 TESTF
1 3 TEST I/O
25 19
16 12
8 8
3 4
5 5
6 6
PA0/
EXI0/
AIN0
PA1/
EXI1/
AIN1/
CMP1P
PA2/
EXI2
PB0/
EXI4/
AIN2/
RXD0
PB1/
EXI5/
AIN3
PB2/
EXI6/
RXD1
testing
Input/output port /
I/O
External interrupt /
ADC input
External interrupt /
ADC input /
I/O
Analog comparator
Input/output port /
I/O
External interrupt /
Input/output port /
External interrupt /
ADC input /
I/O
UART0 data input /
External trigger
External interrupt /
I/O
ADC input /
External interrupt /
I/O
UART1 data input /
PWM
C
PWM
D
PWM
E
PWM
C
PWM
D
PWM
E
O
O
O
O
O
O
PWMC
output
PWMD
output
PWME
output
PWMC
output
PWMD
output
PWME
output
OUTCL
K
LSCLK O
CLKIN I
OUTCL
K
TXD0 O
O
O
speed
clock
Low-
speed
clock
output
clock
input
High-
speed
clock
output
UART0
data
output
TM9O
UT
TMFO
UT
CMP0
OUT
CMP1
OUT
TXD1 O
O
O
O
O
timer 9
output
timer F
output
CMP0
output
CMP1
output
UART1
data
output
7 7
13
17
18 14
19 15
24 18
FEUL610Q111 1-6
PB3/
EXI7
PB4/
CMP0P
PB5/
RXD0/
CMP0M
PB6/
AIN4
PB7/
AIN5/
RXD1
I/O
External interrupt /
Input/output port /
Analog comparator
0 non-inverted input
I/O
/
UART0 data input /
Analog comparator
I/O
0 inverted input /
I/O
ADC input /
Analog comparator
0 inverted input /
I/O
UART data input /
SIN I
SOUT O
SCK I/O
CLKI
N
LSCL
O
K
I
data
SSIO
data
output
SSIO
clock
input/ou
tput
clock
input
Low-
speed
clock
output
TXD1 O
TXD0 O
SCL I/O
SDA I/O
PWMF
0
O
data
UART0
data
output
I2C
clock
I2C
data
PWMF
0 output
TXD1 O
PWM
F2
PWM
F1
PWM
O
O
O
C
UART1
data
output
PWMF
2
output
1
PWMC
output
PIN No.
Primary function
Secondary function
Tertiary function
quaternary function
Pin
name
Pin
name
Descrip
tion
Pin
name
Descrip
tion
Pin
name
Descript
ion
PWMF
0
PWMF
0output
TM9O
UT
timer 9
output
PWMF
1
PWMF
1output
PWMF
2
PWMF
2output
TMFO
UT
timer F
output
I2C
clock
PC6/
AIN6
Input/output port /
ADC input
PC7/
AIN7
Input/output port /
ADC input
31 PD0
I/O
Input/output port
Input/output port
10
PD2
I/O
12 PD3
I/O
Input/output port
I/O
Input/output port
15
PD5
32
LQFP
20
TSSOP
I/O Description
I/O
ML610Q111/ML610Q112 User’s Manual
Chapter 1 Overview
I/O
I/O
30 1 PC0 I/O Input/out put port
27 20 PC1 I/O Input/output port
14 11 PC2 I/O Input/output port
11 10 PC3 I/O Input/output port
29
28
26
23
2
13
PC4 I/O Input/output port SCL I/O
PC5 I/O Input/output port SDA I/O
I/O
I/O
PD1 I/O
Input/output port
PD4
I/O Input/output port
I2C
data
O
O
O
O
O
*: The External trigger is indicated the Timer E, F or the PWMC-F external trigger input (TETG,TFTG, PCTG, PDTG, PETG,
PFTG).
FEUL610Q111 1-7
1.3.3 Description of Pins
Primary/
System
internally connected.
Tertiary
the PA0 or PB0 pin.
General-purpose input/output port
External interrupt
terrupt input pins. Interrupt enable and edge selection
can be performed for each bit by software. These pins are used as the
primary functions of the PA0 – PA2 and PB0 – PB3 pins.
Synchronous Serial Port (SSIO)
This pin is used as the secondary
function of the PB3 pin.
This pin is used as the secondary
function of the PB5 pin.
This pin is used as the secondary
function of the
I2C Bus Interface
2
or the
secondary function of the PC4 pin.
Tertiary
2
or the
secondary function of the PC5 pin.
Tertiary
Table 1-2 shows description of pins.
ML610Q111/ML610Q112 User’s Manual
Table 1-2 (1/3) Description of pins
Chapter 1 Overview
Pin name I/O Description
Reset input pin. When this pin is set to a “L” level, system reset mode is
RESET_N I
CLKIN I
LSCLK O
OUTCLK O
PA0 to PA2
PB0 to PB7
PC0 to PC7
PD0 to PD5
EXI0 to 2,
EXI4 to 7
set and the internal section is initialized. When this pin is set to a “H”
level subsequently, program execution starts. A pull-up resistor is
High-speed clock output pin. This pin is used as the tertiary function of
the PA2 or the secondary function of PB6 pin.
Low-speed clock output pin. This pin is used as the tertiary function of the
PA1 or the secondary function of the PB7 pin.
High-speed clock output pin. This pin is used as the tertiary function of
General-purpose input/output port.
Since these pins have secondary functions and tertiary functions and
quaternary functions, the pins cannot be used as a port when the
I/O
secondary functions and tertiary functions and quaternary functions are
used.
External maskable in
I
Secondary/
Tertiary/
Quaternary
— Negative
Secondary/
Tertiary
Secondary/
Tertiary —
Primary Positive
Primary
Logic
Positive/
Negative
—
—
UART
SIN
SCK
SOUT
TXD0
RXD0
TXD1
RXD1
SCL
SDA
I Synchronous serial data input pin.
I/O Synchronous clock input/output pin.
O Synchronous serial data output pin.
function of the PB4 pin.
UART0 data output pin. This pin is used as the tertiary function of the PB1
O
or PB4 pin.
UART0 data input pin. This pin is used as the primary function of the PB0
I
or PB5 pin.
UART1 data output pin. This pin is used as the quaternary
O
PB0 or PB1 or the tertiary function of the PB3 pin.
UART1 data input pin. This pin is used as the primary function of the PB2
I
or PB7 pin.
I/O
I
C clock pin. This pin is used as the tertiary function of the PB5
I/O
I
C data pin. This pin is used as the tertiary function of the PB6
Secondary Positive
Secondary —
Secondary Positive
Tertiary Positive
Primary Positive
Tertiary/
Quaternary
Primary Positive
Secondary/
Secondary/
Positive
Positive
Positive
FEUL610Q111 1-8
Table 1-2 (2/3) Description of pins
Timer
Timer 9 output pin. This pin is used as the quaternary function of the PA0
Timer F output pin. This pin is used as the quaternary function of the PA1
PWM
PFTG
PC0 pin.
negative
Quaternary
Quaternary
Successive approximation type A/D converter
This pin is used as the primary function of the PA0 pin.
This pin is used as the primary function of the PB0 pin.
Channel 3 analog input for successive approximation type A/D converter.
Channel 4 analog input for successive approximation type A/D converter.
Channel 5 analog input for successive approximation type A/D converter.
Channel 6 analog input for successive approximation type A/D converter.
This pin is used as the primary function of the PC6 pin.
This pin is used as the primary function of the PC7 pin.
Comparator
function of the PB4 pin.
of the PB5 pin.
the PA2 pin.
function of the PA1 pin.
the PB0 pin.
Pin name I/O Description
ML610Q111/ML610Q112 User’s Manual
Chapter 1 Overview
Primary/
Secondary/
Tertiary/
Quaternary
Logic
TETG,
TFTG
TM9OUT O
TMFOUT O
PCTG,
PDTG,
PETG,
PWMC O
PWMD O
PWME O
PWMF0 O
PWMF1 O
PWMF2 O
AIN0 I
AIN1 I
AIN2 I
I
External clock input pin used for both Timer E and Timer F. These pins
I
are used as the primary function of the PA0-PA2, PB0-PB7 pins.
or PC0 pin.
or PC3 pin.
External trigger input pins of PWMC to PWMF. These pins are used as
the primary function of the PA0-PA2, PB0-PB7 pins.
PWMC output pin. This pin is used as the secondary function of the PB0
or PA0 or the quaternary function of the PB7 pin.
PWMC output pin. This pin is used as the secondary function of the PB1
or PA1 pin.
PWME output pin. This pin is used as the secondary function of the PB2
or PA2 pin.
PWMF0 output pin. This pin is used as the tertiary function of the PB7 or
PWMF1 output pin. This pin is used as the quaternary function of the
PB6 or the tertiary function of the PC1 pin.
PWMF2 output pin. This pin is used as the quaternary function of the
PB5 or the tertiary function of the PC2 pin.
Channel 0 analog input for successive approximation type A/D converter.
Channel 1 analog input for successive approximation type A/D converter.
This pin is used as the primary function of the PA1 pin.
Channel 2 analog input for successive approximation type A/D converter.
Primary —
Quaternary Positive
Quaternary Positive
Primary
Secondary/
Quaternary
Secondary
Secondary
Tertiary
Tertiary/
Tertiary/
Primary —
Primary —
Primary —
—
Positive/
negative
Positive/
negative
Positive/
negative
Positive/
Positive/
negative
Positive/
negative
AIN3 I
AIN4 I
AIN5 I
AIN6 I
AIN7 I
CMP0P I
CMP0M I
CMP0OUT O
CMP1P I
CMP1OUT O
This pin is used as the primary function of the PB1 pin.
This pin is used as the primary function of the PB6 pin.
This pin is used as the primary function of the PB7 pin.
Channel 7 analog input for successive approximation type A/D converter.
Non-inverting input for comparator0. This pin is used as the primary
Inverting input for comparator0. This pin is used as the primary function
Output for comparator0. This pin is used as the quaternary function of
Non-inverting input for comparator1. This pin is used as the primary
Output for comparator1. This pin is used as the quaternary function of
Primary —
Primary —
Primary —
Primary —
Primary —
Primary —
Primary —
Quaternary —
Primary —
Quaternary —
FEUL610Q111 1-9
Quaternary
For testing
TEST
I/O
—
Positive
TESTF
—
—
—
Power supply
VSS
—
— — VDD
—
—
—
Table 1-2 (3/3) Description of pins
Pin name I/O Description
Input/output pin for testing. A pull-down resistor is internally connected.
Test pin for flash memory. A pull-down resistor is internally connected.
Negative power supply pin.
Positive power supply pin.
ML610Q111/ML610Q112 User’s Manual
Chapter 1 Overview
Primary/
Secondary/
Tertiary/
Logic
FEUL610Q111 1-10
Pin
Recommended pin termination
Open
Open
PA0 to PA2
Open
PC0 to PC7
Open
N.C.
Open
1.3.4 Termination of Unused Pins
Table 1-3 shows methods of terminating the unused pins.
Table 1-3 Termination of Unused Pins
RESET_N
TEST
TESTF
ML610Q111/ML610Q112 User’s Manual
Chapter 1 Overview
Open
PB0 to PB7
PD0 to PD5
Open
Open
Note:
It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up
resistors or the output mode since the supply current may become excessively large if the pins are left open in the high
impedance input setting.
FEUL610Q111 1-11
Chapter 2
CPU and Memory Space
ML610Q111/ML610Q112 User’s Manual
CSR:PC
Segment 0
ROM Window Area
0:00FFH
0:5FDFH
Chapter 2 CPU and Memory Space
2 CPU and Memory Space
2.1 Overview
This LSI includes 8-bit CPU nX-U8/100 and the memory model is “SMALL model”.
For details of the CPU nX-U8/100, see “nX-U8/100 Core Instruction Manual”.
2.2 Program Memory Space
The program memory space is used to store program codes, table data (ROM window), or vector tables.
The program codes have a length of 16 bits and are specified by a 16-bit program counter (PC).
The ROM window area data has a length of 8 bits and can be used as table data.
The vector table, which has 16-bit long data, can be used as reset vectors, hardware interrupt vectors, and software interrupt
vectors. The unused software interrupt vector can use as a program code area.
The program memory space consists of 1 segment and ML610Q111 has 24-Kb yte (12-Kword) capacity, ML610Q112 has
32-Kbyte (16-Kword) capacity.
Figure 2-1 shows the configuration of the program memory space of the ML610Q111.
Figure 2-2 shows the configuration of the p rogram memory space of the ML610Q112.
0:0000H Vector Table Area
or
Program Code
0:0100H
Program Code Area
or
ROM Window Area
0:5FE0H
0:5FFFH
8bit
Test Data Area
Figure 2-1 Configuration of Program Memory Space of the ML610Q1 11
Notes:
− Because test program data is stored in the 32 bytes (16 words) test data area (0: 5FE0H to 0:5FFFH) of the Segment 0,
this area cannot be used as a program code area.
− The address “0: 5FE0H to 0: 5FFFH” in the test area is write-able and erase-able. Fill the area with “0FFH”. If data in the
area is uncertain or other data (i.e. not 0FFH), operating with the code can not be guaranteed.
− Set “0FFFFH” data (BRK instruction) by using HTU8(program development support software) in the unused area of the
program memory space for the fail safe. For the HTU8, see “HTU8 User’s Manual”. For the BRK instruction, see
“nX-U8/100 Core Instruction Manual”.
FEUL610Q111 2-1
ML610Q111/ML610Q112 User’s Manual
CSR:PC
Segment 0
ROM Window Area
0:00FFH
0:7FDFH
0:7FFFH
8bit
Chapter 2 CPU and Memory Space
0:0000H Vector Table Area
or
Program Code
0:0100H
0:7FE0H
Program Code Area
or
ROM Window Area
Test Data Area
Figure 2-2 Configuration of Program Memory Space of the ML610 Q112
Notes:
− Because test program data is stored in the 32 bytes (16 words) test data area (0:7FE0H to 0:7FFFH) of the Segment 0,
this area cannot be used as a program code area.
− The address “0: 7FE0H to 0: 7FFFH” in the test area is write-able and erase-able. Fill the area with “0FFH”. If data in the
area is uncertain or other data (i.e. not 0FFH), operating with the code can not be guaranteed.
− Set “0FFFFH” data (BRK instruction) by using HTU8(program development support software) in the unused area of the
program memory space for the fail safe. For the HTU8, see “HTU8 User’s Manual”. For the BRK instruction, see
“nX-U8/100 Core instruction Manual”.
FEUL610Q111 2-2
ML610Q111/ML610Q112 User’s Manual
Segment 0
DSR: Data
address
2:0FFFH
0:0E7FFH
2:0FFFFH
Segment 8
Segment A
A:1000H
8:0FFFFH
A:0FFFFH
8bit
Chapter 2 CPU and Memory Space
2.3 Data Memory Space
The data memory space of this LSI consists of the ROM window area, 2-Kbyte RAM area(ML610Q111), 4-Kbyte RAM
area(ML610Q112) and SFR area and 4-Kbyte Segment 2 of the data flash area and the ROM reference areas of the
Segment 8 and the data flash reference areas of the Segment A.
The data memory stores 8-bit data and is specified by 20 bits consisting of higher 4 bits as DSR and lower 16 bits as
addressing specified by each instruction.
Figure 2-3 shows the configuration of the data memory space of the ML610Q111.
Figure 2-4 shows the configuration of the data memory space of the ML610Q112.
DSR: Data address
0:0000H
0:5FFFH
0:6000H
0:0DFFFH
0:0E000H
0:0E800H
0:0F000H
0:0FFFFH
8:0000H
8:5FFFH
8:6000H
ROM Window
Unused Area
RAM Area
Unused Area
SFR Area
ROM Reference
Unused Area
Area
2 KB
8bit
Area
Segment 2
2:0000H
2:1000H
Data Flash Area
4 KB
A:0000H
A:0FFFH
Unused Area
Data Flash
Reference Area
8bit
Unused Area
8bit
Figure 2-3 Configuration of Data Memory Space of the ML610Q111
Notes:
− The contents of the 2-Kbyte RAM area are undefined at power-on and system reset. Initialize this area by software.
FEUL610Q111 2-3
ML610Q111/ML610Q112 User’s Manual
Segment 0
address
8bit
8bit
Segment 8
Segment A
Chapter 2 CPU and Memory Space
DSR: Data
2:0000H
2:0FFFH
2:1000H
Segment 2
Data Flash Area
DSR: Data address
0:0000H
0:5FFFH
0:6000H
0:0DFFFH
ROM Window
Area
Unused Area
0:0E000H
0:0EFFFH
0:0F000H
0:0FFFFH
8:0000H
8:5FFFH
8:6000H
RAM Area
SFR Area
ROM Reference
4 KB
Area
Unused Area
2:0FFFFH
A:0000H
A:0FFFH
A:1000H
Data Flash
Reference Area
Unused Area
Unused Area
8:0FFFFH
A:0FFFFH
8bit
8bit
Figure 2-4 Configuration of Data Memory Space of the ML610Q112
Notes:
− The contents of the 4-Kbyte RAM area are undefined at power-on and system reset. Initialize this area by software.
− Although segment 0 of the program memory space and segment 0 of the data memory space are separate space, the
contents of segment 0 of the program memory space can read via R OM Window area of the data space.
− Segment 8 is a mirror area of segment 0 of the program memory space. The contents of segment 0 of the program
memory space can read from segment 8 of ROM reference area.
− Segment A is a mirror area of segment 2. The contents of segment 2 of the data flash area can read from segment A of
data flash reference area.
FEUL610Q111 2-4
2.4 Instruction Length
The length of an instruction is 16 bits.
2.5 Data Type
The data types supported include byte (8 bits) and word (16 bits).
ML610Q111/ML610Q112 User’s Manual
Chapter 2 CPU and Memory Space
FEUL610Q111 2-5
ML610Q111/ML610Q112 User’s Manual
0F000H
Data segment register
DSR
R/W 8 00H
Chapter 2 CPU and Memory Space
2.6 Description of Registers
2.6.1 List of Registers
Address Name Symbol (Byte) Symbol (Word) R/W Size Initial value
FEUL610Q111 2-6
ML610Q111/ML610Q112 User’s Manual
7 6 5 4 3 2 1 0
DSR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
DSR3
DSR2
DSR1
DSR0
Description
0 0 0
0
Data segment 0 (initial value)
0 0 0
1
Prohibited
0 0 1
0
Data segment 2
0 0 1
1
0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0
0
Data segment 8
1 0 0
1
Prohibited
1 0 1
0
Data segment A
1 0 1
1
1 1 0 0 1 1 0 1 1 1 1 0 1 1 1
1
Chapter 2 CPU and Memory Space
2.6.2 Data Segment Register (DSR)
Address: 0F000H
Access: R/W
Access size: 8 bits
Initial value: 00H
DSR3 DSR2 DSR1 DSR0
DSR is a special function register (SFR) to retain a data segment address. For details of DSR, see “nX-U8/100 Core
Instruction Manual”.
[Description of Bits]
• DSR3-DSR0 (bits 3-0)
Prohibited
Prohibited
FEUL610Q111 2-7
Chapter 3
Reset Function
ML610Q111/ML610Q112 User’s Manual
Pin name
I/O
Description
RESET_N
I
VDD
Chapter 3 Reset Function
3 Reset Function
3.1 Overview
This LSI has the five reset functions shown below. If any of the five reset conditions is satisfied, this LSI enters system
reset mode.
• Reset by the RESET_N pin
• Reset by power-on detection
• Reset by the 2
• Reset by the voltage level supervisor (VLS)
• Software reset by execution of the BRK instruction
3.1.1 Features
• The RESET_N pin has an internal pull-up resistor
• 46.8ms, 62.5ms, 125ms, 250ms, 1sec, 4 sec, or 16sec can be selected as the watchdog timer (WDT) second overflow
period
• Built-in reset status register (RSTAT) indicating the reset generation causes
• Only the CPU is reset b y the BRK instruction (the SFR area are not reset).
3.1.2 Configuration
nd
watchdog timer (WDT) overflow
Figure 3-1 shows the configuration of the r eset generation c ircuit.
RESET_N
RSTAT: Reset status register
3.1.3 List of Pin
Power-on reset
VLS reset
WDT reset
Figure 3-1 Configuration of Reset Generation Circuit
Reset input pin
Reset signal
RSTAT
Data bus
FEUL610Q111 3-1
ML610Q111/ML610Q112 User’s Manual
0
1
Power-on reset generated
0
Watchdog timer reset not occurred
VLSR
Description
1
Chapter 3 Reset Function
3.2 Description of Registers
3.2.1 List of Registers
Address Name Symbol (Byte) Symbol (Word) R/W Size Initial value
0F001H Reset status register RSTAT R/W 8 Undefined
3.2.2 Reset Status Register (RSTAT)
Address: 0F001H
Access: R/W
Access size: 8 bits
Initial value: Undefined
7 6 5 4 3 2 1 0
RSTAT ― ― VLSR ― ― WDTR ― POR
R/W ― ― R/W ― ― R/W ― R/W
Initial value 0 0 0/1 0 0 0/1 0 0/1
RSTAT is a special function register (SFR) that indicates the causes by which the reset is generated.
At the occurrence of reset, the contents of RSTAT are not initialized, while the bit indicating the cause of the reset is set
to ”1”. W hen checking the reset cause using this function, perform write operation to RSTAT after read RSTAT and
initialize the contents of RSTAT to “00H” for checking the next reset cause.
[Description of Bits]
• POR (bit 0)
The POR bit is a flag that indicates that the power-on reset is generated. This bit is set to “1” when powered on.
POR Description
Power-on reset not generated
• WDTR (bit 2)
The WDTR is a flag that indicates that the watchdog timer reset is generated. This bit is set to “1” when the reset by
overflow of the watchdog timer is generated.
WDTR Description
1
Watchdog timer reset occurred
• VLSR (bit 5)
The VLSR is a flag that indicates that the voltage level supervisor (VLS) reset is generated. This bit is set to “1” when the
reset by the VLS is generated.
0
Voltage level supervisor (VLS) reset not occurred
Voltage level supervisor (VLS) reset occurred
Note:
- Even if when power-on reset does not occur at the time of power-on, POR bit may become "1". Therefore, when you
distinguish power-on, we recommend using the RAM. When the power down occurs, the contents of the RAM become
random. Due to this, it can distinguish a power-on supply by confirming the change of the content of the RAM which was
written in beforehand.
- No flag is provided that indicates the occurrence of reset by the RESET_N pin.
FEUL610Q111 3-2
ML610Q111/ML610Q112 User’s Manual
Chapter 3 Reset Function
3.3 Description of Operation
3.3.1 Operation of System Reset Mode
System reset has the highest priority among all the pro cessing and any other p rocessing being executed up to then is
cancelled.
The system reset mode is set by any of the following causes.
• Reset by the RESET_N pin
• Reset by power-on detection
• Reset by the 2
• Reset by the voltage level supervisor (VLS)
• Software reset by the BRK instruction (only the CPU is reset)
In system reset mode, the following processing is performed.
(1) All the special function registers (SFRs) whose initial value is not undefined are initialized. However, the initialization
is not performed by software reset due to execution of the BRK instruction. See Appendix A “Registers” for the initial
values of the SFRs.
(2) CPU is initialized.
• All the registers in CPU are initialized.
• The contents of addresses 0000H and 0001H in the program memory are set to the stack pointer (SP).
• The contents of addresses 0002H and 0003H in the program memory are set to the program counter (PC). However,
when the interrupt level (ELEEVL) of the program status word (PSW) at reset by the BRK instructio n is 1 or lower,
the contents of addresses 0004H and 0005H of the program memory are set in the program counte r (PC). For the
BRK instruction, see “nX-U8/100 Core Instruction Manual”.
nd
watchdog timer (WDT) overflow
Note:
In system reset mode, the contents of data memory and those of any SFR whose initial value is undefined are not
initialized and are undefined. Initialize them by software.
In system reset mode by the BRK instruction, all SFRs are not initialized. Therefore initialize SFRs by software.
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Reset or BRK
Interrupt
Chapter 4 MCU Control Function
4 MCU Control Function
4.1 Overview
The operating states of this LSI are classified into the following 4 modes including system reset mode:
• System reset mode
• Program run mode
• HALT mode
• STOP mode
For system reset mode, see Chapter 3, “Reset Function”.
This LSI has a block control func tion, which power downs the circuits of unused peripherals (reset registers and stop clock
supplies) to make even more reducing the current consumption.
4.1.1 Features
• HALT mode, where the CPU sto ps operating and only the peripheral circuit is operating
• STOP mode, where both low-speed oscillation and high-speed oscillation stop
• Stop code acceptor function, which controls transition to STOP mode
• Block control function, which power downs the circuits of unused peripherals (reset registers and stop clock supplies).
4.1.2 Configuration
Figure 4-1 shows a CPU o perating state transition diagram.
Power on
System reset
mode
Reset
Reset
STP = “1”
Figure 4-1 Operating State Transition Diagram
Release of reset
Program
run mode
instruction
HLT = “1”
External interrupt
HALT mode STOP mode
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0F02FH
Block control register 7
BLKCON7
R/W 8 00H
Chapter 4 MCU Control Function
4.2 Description of Registers
4.2.1 List of Registers
Address Name Symbol (Byte) Symbol (Word) R/W Size Initial value
0F008H
0F009H
0F02AH
0F02CH
0F02EH
Stop code acceptor
Standby control register
Block control register 2
Block control register 4
Block control register 6
STPACP W 8 00H
SBYCON W 8 00H
BLKCON2 R/W 8 00H
BLKCON4 R/W 8 00H
BLKCON6 R/W 8 00H
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7 6 5 4 3 2 1 0
Chapter 4 MCU Control Function
4.2.2 Stop Code Acceptor (STPACP)
Address: 0F008H
Access: W
Access size: 8 bits
Initial value: (Undefined)
STPACP d7 d6 d5 d4 d3 d2 d1 d0
R/W W W W W W W W W
Initial value 0 0 0 0 0 0 0 0
STPACP is a write-only special function register (SFR) which enables for entering a STOP mode.
When STPACP is read, “00H” is read.
When data is written to STPACP in the order of “5nH” (n: an arbitrary value) a nd “0AnH” (n: an arbitrary value), the
entering the STOP mode is enabled 1 time only. When the STP bit o f the standb y control r e gister (SBYCON) is set to “1”
in this state, the mode is changed to the STOP mode. When the STOP mode is released, the entering the STOP mode is
disabled.
When another instruction is execut ed between the instruc tion that writes “5nH” to STPACP and the instruction that writes
“0AnH”, the entering the STOP mode is enabled after “0AnH” is written. However, if data other than “0AnH” is written to
STPACP after “5nH” is written, the “5nH” write processing becomes invalid so that data must be written again starting
from “5nH”.
For failsafe, we recommend changing to the STOP mode by the following procedures.
1. Enable the status of the change to the STOP mode by using the stop code acceptor.
2. Set an interrupt to release the STOP mode.
3. Change to the STOP mode by setting to "1" the STP bit of SBYCON.
During a system reset, the entering the STOP mode is disabled.
Note:
When MIE(Master Interrupt Enable flag) of PSW (Program Status W ord of nX-U8/100 Core) is "0" and both any interrupt
enable flag and the corresponding interrupt request flag are "1", the entering the STOP mode is disabled.
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R/W
― ― ― ― ― ― W
W
Initial value
0 0 0 0 0 0 0
0
STP
HLT
Description
0
1
1
1
Chapter 4 MCU Control Function
4.2.3 Standby Control Register (SBYCON)
Address: 0F009H
Access: W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
SBYCON ― ― ― ― ― ― STP HLT
SBYCON is a special function register (SFR) to control operating mode of MCU.
[Description of Bits]
• HLT (bit 0)
The HALT bit is used for setting a H ALT mode. When the HALT bit is set to “1”, the mode is changed to the HALT
mode. When the WDT interrupt request, or enabled (the interrupt enable flag is “1”) interrupt request is issued, the
HALT bit is set to “1” and the mode is returned to program run mode.
• STP (bit 1)
The STP bit is used for setting the STOP mode. When the ente r ing the STOP mode is enab le d b y using ST P ACP , when
the STP bit is set to “1”, the mode is changed to the STOP mode. When the interrupt r equest enab led by the i nterrupt
enable register (IE0-IE7) is issued, the STP bit is set to “0” and the LSI returns to the pro gram run mode. W hen the state
of entering the STOP mode is disabled, STP bit does not change to “1”.
0 0
1 0
Program run mode (initial value)
HALT mode
STOP mode
Prohibited
Note:
When the master interrupt enable flag(MIE) of the program status word of nX-U8/100 Core (PSW) is "0" and both any
interrupt enable flag and the corresponding interrupt request flag are "1", the mode does not be changed to HALT mode
or STOP mode.
When a maskable interrupt (interrupt with enable bit) occurs while the MIE is “0”, the STOP mode and the HALT mode
are simply released and interrupt processing is not performed. Refer to the “nX-U8/100 Core Instruction Manual” for
details of PSW.
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R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
DSIO0
Description
1
Disables the operation of Synchronous Serial Port 0.
DUA0
Description
0
Enables the operation of UART0 (initial value).
0
1
Disables the operation of UART1.
DI2C1
Description
2
1
0
2
Chapter 4 MCU Control Function
4.2.4 Block Control Register 2 (BLKCON2)
Address: 0F02AH
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
BLKCON2 DI2C0 DI2C1 DUA1 DUA0 DSIO0
BLKCON2 is a special function register (SFR) that controls the operation of the relevant block.
[Description of Bits]
• DSIO0 (bit 0)
DSIO0 controls the operation of Synchronous Serial Port 0.
0
Enables the operation of Synchronous Serial Port 0 (initial value).
• DUA0 (bit 2)
DUA0 controls the operation of UART0.
1
Disables the operation of UART0.
• DUA1 (bit 3)
DUA1 controls the operation of UART1.
DUA1 Description
Enables the operation of UART1 (initial value).
• DI2C1 (bit 6)
DI2C1 controls the operation of I
0
Enables the operation of I
Disables the operation of I2C bus Interface (Slave).
• DI2C0 (bit 7)
DI2C0 controls the operation of I
DI2C0 Description
Enables the operation of I2C bus Interface (Master) (initial value).
1
Disables the operation of I
2
C bus Interface (Slave).
C bus Interface (Slave) (initial value).
2
C bus Interface (Master).
C bus Interface (Master).
Note:
− If the appropriate bit is set to “1” (operation disabled), the relevant block will be reset (all registers are initialized), and the
clock of the relevant block will stop. When this bit is set to "1", the writing to all the registers of the relevant block will be
invalid, an initial value is read when a register is read. To use the function of the relevant block, reset (enable operation)
the appropriate bit of the block control register to “0”.
− Refer to Chapter 11, “Synchronous Serial Port” for details of the Synchronous Serial Port operation.
− Refer to Chapter 12, “UART” for details of the UART operation.
− Refer to Chapter 13, “I2C Bus Interface Master” for details of the I2C Bus Interface Master operation.
− Refer to Chapter 14, “I2C Bus Interface Slave” for details of the I2C Bus Interface Slave operation.
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R/W
R/W
Initial value
0 0 0 0 0 0 0
0
DSAD
Description
1
Chapter 4 MCU Control Function
4.2.5 Block Control Register 4 (BLKCON4)
Address: 0F02CH
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
BLKCON4 DSAD
BLKCON4 is a special function register (SFR) that controls the operation of the relevant block.
[Description of Bits]
• DSAD (bit 0)
The DSAD bit is used to control SA type A/D converter operation. When the DSAD bit is set to “1”, the circuits related
to SA type A/D converter are reset and turned off.
0
Enables operating SA type A/D converter (initial value)
Disables operating SA type A/D converter
Note:
− If the appropriate bit is set to “1” (operation disabled), the relevant block will be reset (all registers are initialized), and the
clock of the relevant block will stop. When this bit is set to "1", the writing to all the registers of the relevant block will be
invalid, an initial value is read when a register is read. To use the function of the relevant block, reset (enable operation)
the appropriate bit of the block control register to “0”.
− Refer to Chapter 20, “Successive Approximation Type A/D Converter” for details of the successive approximation type
A/D converter operation.
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R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
DTM8
Description
1
Disables the operation of the Timer8.
DTM9
Description
0
Enables the operation of the Timer9 (initial value).
0
1
Disables the operation of the TimerA.
DTMB
Description
1
0
DTMF
Description
1
Chapter 4 MCU Control Function
4.2.6 Block Control Register 6 (BLKCON6)
Address: 0F02EH
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
BLKCON6 DTMF DTME DTMB DTMA DTM9 DTM8
BLKCON6 is a special function register (SFR) that controls the operation of the relevant block.
[Description of Bits]
• DTM8 (bit 0)
DTM8 controls the operation of the Timer8.
0
Enables the operation of the Timer8 (initial value).
• DTM9 (bit 1)
DTM9 controls the operation of the Timer9.
1
Disables the operation of the Timer9.
• DTMA (bit 2)
DTMA controls the operation of the TimerA.
DTMA Description
Enables the operation of the TimerA (initial value).
• DTMB (bit 3)
DTMB controls the opera tion of the TimerB.
0
Enables the operation of the TimerB (initial value).
Disables the operation of the TimerB.
• DTME (bit 6)
DTME controls the operation of the TimerE.
DTME Description
Enables the operation of the TimerE (initial value).
1
Disables the operation of the TimerE.
• DTMF (bit 7)
DTMF controls the operation o f the TimerF.
0
Enables the operation of the TimerF (initial value).
Disables the operation of the TimerF.
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Note:
− If the appropriate bit is set to “1” (operation disabled), the relevant block will be reset (all registers are initialized), and the
clock of the relevant block will stop. When this bit is set to "1", the writing to all the registers of the relevant block will be
invalid, an initial value is read when a register is read. To use the function of the relevant block, reset (enable operation)
the appropriate bit of the block control register to “0”.
− Refer to Chapter 8, “Timers” for details of the Timer operation.
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R/W
R/W
R/W
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
DPWC
Description
1
Disables the operation of the PWMC.
DPWD
Description
0
Enables the operation of the PWMD (initial value).
0
1
Disables the operation of the PWME.
DPWF
Description
1
Chapter 4 MCU Control Function
4.2.7 Block Control Register 7 (BLKCON7)
Address: 0F02FH
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
BLKCON7 DPWF DPWE DPWD DPWC
BLKCON7 is a special function register (SFR) that controls the operation of the relevant block.
[Description of Bits]
• DPWC (bit 0)
DPWC controls the operation of the PWM C.
0
Enables the operation of the PWMC (initial value).
• DPWD (bit 1)
DPWD controls the operation o f the PWMD.
1
Disables the operation of the PWMD.
• DPWE (bit 2)
DPWE controls the operation of the PWME.
DPWE Description
Enables the operation of the PWME (initial value).
• DPWF (bit 3)
DPWF controls the operation o f the PWMF.
0
Enables the operation of the PWMF (initial value).
Disables the operation of the PWMF.
Note:
− If the appropriate bit is set to “1” (operation disabled), the relevant block will be reset (all registers are initialized), and the
clock of the relevant block will stop. When this bit is set to "1", the writing to all the registers of the relevant block will be
invalid, an initial value is read when a register is read. To use the function of the relevant block, reset (enable operation)
the appropriate bit of the block control register to “0”.
− Refer to Chapter 10, “PWM” for details of the Timer operation.
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Chapter 4 MCU Control Function
4.3 Description of Operation
4.3.1 Program Run Mode
The program run mode is the state where the CPU executes instructions sequentially.
At power-on reset, RESET_N pin reset, lo w level detection reset, VLS reset, or WDT overflow reset, the CPU executes
instructions from the addresses that are set in addresses 0002H and 0003H of program memory (ROM) after the system
reset mode is released.
At reset by the BRK instruction, the CPU executes instructions from the addresses that are set in the addresses 0004H and
0005H of the program memory after the system reset mode is released. However, when the value of the interrupt level bit
(ELEVEL) of the program status word (PSW) is 02H or higher at execution of the BRK instruction (after the occurrence of
the WDT interrupt), the CPU executes instructions from the addresses that are set in the addresses 0002H and 0003H.
For details of the BRK instruction and PSW, see the “nX-U8/100 Core Instruction Manual” and for the reset function, see
Chapter 3, “Reset Function”.
4.3.2 HALT Mode
The HALT mode is the state where the CPU interrupts execution of instructions and only the peripheral circuits are
running.
When the HLT bit of the standby control register (SBYCON) is set to “1”, the HALT mode is set.
When a WDT interrupt request, or an interrupt request enabled by an interrupt enable register (IE0–IE7) is issued, the HLT
bit is set to “0” on the falling edge of the next system clock (SYSCLK) and the HALT mode is returned to the program run
mode released.
Figure 4-2 shows the operation waveforms in HALT mode.
System base clock
(low or high-speed)
SYSCLK
SBYCON.HLT
Interrupt request
Program run mode HALT mode
Program run mode
Figure 4-2 Operation Waveforms in HALT Mode
Note:
Since up to two instructions are executed during the period between HALT mode release and a transition to interrupt
processing, place two NOP instructions next to the instruction that sets the HLT bit to “1”. When the master interrupt
enable flag(MIE) of the program status word of the nX-U8 Core (PSW) is "1", the interrupt shift cycle (system clock: 3
clock) is executed after these two NOP instructions are executed and the instruction execution of the interrupt routine is
started. When the MIE is "0", it does not shift to the interrupt after also these two NOP instructions and next instruction
of NOP is continued.
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32 pulse count
Low-speed
oscillation
Oscillation waveform
SYSCLK
speed
oscillation
SBYCON.STP bit
LSCLK
HSCLK waveform
HSCLK
Interrupt request
Oscillation waveform
Chapter 4 MCU Control Function
4.3.3 STOP Mode
The STOP mode is the state where low-speed oscillation and high-speed oscillation stop and the CPU and peripheral
circuits stop the operation.
When the entering the STOP mode is enabled by writing “5nH” (n: an arbit rary value) and “0AnH” (n: an arbitrary value)
to the stop code acceptor ( STPACP) sequentially and the STP bit of the standby control register (SBYCON) is set to “1”,
the STOP mode is entered. When the STOP mode is set, the entering the STOP mode is disabled.
When a VLS interrupt request or a n i nterrupt-enabled (the interrupt enable flag is “1”) interr up t r e quest is issued, the STP
bit is set to “0”, the STOP mode is released, and the mode is returned to the program run mode.
4.3.3.1 STOP Mode When CPU Operates with Low-Speed Clock
When the entering the STOP mode (by using the stop code acceptor(STPACP)) is in the enabled state and the STP bit of
SBYCON is set to “1”, the STOP mode is entered, sto pping low-speed oscillation and high-speed oscillation.
When interrupt-enabled (the interrupt enable flag is “1”) interrupt request occurs, the STP bit is set to “0” and low-speed
oscillation restarts. If the high-speed clock was oscillating before the STOP mode is entered, the high-speed oscillation
restarts after the low-speed clock was oscillating. When the high-speed clock was not oscillating before the STOP mode
is entered, hi gh-spe e d oscillation does not start.
When an interrupt request occurs, the STOP mode is released after counting low-speed clock (LSCLK) 32 times., the mode
is returned to the program run mode, and the low-speed clock(LSCLK) restarts supply to the peripheral circuits. When the
low-speed clock (LSCLK) restart, the high-speed clocks (OSCLK and HSCLK) restarts supply to the peripheral circuits
after counting for stabilizing the clock oscillation (16384-pulse count for PLL or 128-pulse count for External clock).
Figure 4-3 shows the operation waveforms in STOP mode when CPU operates with the low-speed clock.
Low-speed oscillation
High-
Oscillation waveform
HSCLK waveform
Program run mode
STOP mode
High-speed
oscillation
16384 or 128 pulse count
Program run mode
Figure 4-3 Operation Waveforms in STOP Mode When CPU Operates with Low-Speed Clock
Note:
Since up to two instructions are executed during the period between STOP mode release and a transition to interrupt
processing, place two NOP instructions next to the instruction that sets the STP bit to “1”. When the master interrupt
enable flag(MIE) of the program status word of the nX-U8 Core (PSW) is "1", after executed these two NOP instructions,
interrupt shift cycle (system clock: 3 clock) is executed. Then, instruction execution of the interrupt routine is started.
When the MIE is "0", after executed these two NOP instructions, it does not shift to the interrupt. Then, next instruction
execution of NOP instruction is continued.
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32 pulse count
Chapter 4 MCU Control Function
4.3.3.2 STOP Mode When CPU Operates with High-Speed Clock
When the CPU is operating with a high-speed cloc k and the STP bit of SBYCON is set to “1” with the entering the STOP
mode enabled (by using the stop code acceptor(STPACP)), the STOP mode is entered and high-speed oscillation and
low-speed oscillation stop.
When interrupt-enabled (the interrupt enable flag is “1”) interrupt request occurs, the STP bit is set to “0” and the
low-speed and high-speed oscillation restart.
When an interr upt request is issue d, after counting t he low-speed clock oscillation stabilization time (32-pulse count) , and
the low-speed clock oscillation restarts supply to the peripheral circuits. Then after, the STOP mode is released after the
elapse of the high-speed clock (OSCLK) oscillation stabilization time (16384-pulse count for PLL or 128-pulse count for
External clock), the mode is returned to the program run mode, and at the same time the high-speed clocks (OSCLK and
HSCLK) restart supply to the peripheral circuits.
For the high-speed oscillation start time (T
Figure 4-4 shows the o peration waveforms in STOP mode when CPU operates with the high-speed clock.
High-speed oscillation
waveform
High-speed oscillation waveform
), see Appendix C “Electrical Characteristics”.
PLL
High-speed oscillation waveform
OSCLK, HSCLK
SYSCLK
Low-speed oscillation
waveform
LSCLK
SBYCON.STP bit
Interrupt request
OSCLK,HSCLK waveform
16384 or 128 pulse count
HSCLK waveform HSCLK waveform
Low-speed oscillation
Program run mode
STOP mode Program run mode
OSCLK, HSCLK waveform
Figure 4-4 Operation Waveforms in STOP Mode When CPU Operates with High-Speed Clock
Note:
Since up to two instructions are executed during the period between STOP mode release and a transition to interrupt
processing, place two NOP instructions next to the instruction that sets the STP bit to “1”. When the master interrupt
enable flag(MIE) of the program status word of the nX-U8 Core (PSW) is "1", after executed these two NOP instructions,
interrupt shift cycle (system clock: 3 clock) is executed. Then, instruction execution of the interrupt routine is started.
When the MIE is "0", after executed these two NOP instructions, it does not shift to the interrupt. Then, next instruction
execution of NOP instruction is continued.
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interrupt routine.
sets the STP/HLT bit to “1”, then goes to the interrupt routine.
ELEVEL
MIE
IEn.m
IRQn.m
Return operation from STOP/HALT mode
* * *
0
interrupt routine.
Chapter 4 MCU Control Function
4.3.3.3 Note on Return Operation from STOP/HALT Mode
The operation of returning from the STOP mode and HALT mode varies according to the interrupt level (ELEVEL) of the
program status word (PSW), master interrupt enable flag (MIE), the contents of the interrupt enable register (IE0 to IE7),
and whether the interrupt is a non-maskable interrupt or a maskable interrupt.
For details of PSW and the IE and IRQ registers, see “nX-U8/100 Core Instruction Manual” and Chapter 5, “Interrupt”,
respectively.
Table 4-1 and Table 4-2 show the return operations from STOP/HALT mode.
Table 4-1 Return Operation from STOP/HALT Mode (Non-Maskable Interrupt)
ELEVEL MIE IEn.m IRQn.m Return operation from STOP/HALT mode
* * − 0
3 * − 1
0, 1, 2 * − 1
Not returned from STOP/HALT mode.
After the mode is returned from STOP/HALT mode, the program
operation restarts from the instruction following the instruction that
sets the STP/HLT bit to “1”. The program operation does not go to the
After the mode is returned from the STOP/HALT mode, program
operation restarts from the instruction following the instruction that
Table 4-2 Return Operation from STOP/HALT Mode (Maskable Interrupt)
* * 0 1
* 0 1 1
2,3 1 1 1
0, 1 1 1 1
Not returned from STOP/HALT mode.
After the mode is returned from STOP/HALT mode, the program
operation restarts from the instruction following the instruction that
sets the STP/HLT bit to “1”. The program operation does not go to the
After the mode is returned from the STOP/HALT mode, program
operation restarts from the instruction following the instruction that
sets the STP/HLT bit to “1”, then goes to the interrupt routine.
The interrupt level (ELEVEL) of the program status word (PSW) is bits for indicating the status of the interrupt of the CPU.
The ELEVEL is set by the hardware when the processing shifts to the interrupt and returns from the interrupt.
−If the ELEVEL is 0, it indicates that the CPU is performing neither nonmaskable interrupt processing nor maskable
interrupt p rocessing nor soft ware interrupt processing.
−If the ELEVEL is 1, it indicates that the CPU is performing maskable interrupt processing or software interrupt
processing.
−If the ELEVEL is 2, it indicates that the CPU is performing non-maskable interrupt processing.
−If the ELEVEL is 3, it indicates that the CPU is performing interrupt processing specific to the emulator. This setting is
not allowed in normal applications.
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Chapter 4 MCU Control Function
4.3.4 Block Control Function
This LSI has a block control func tion, which resets and completely turns operating circuits of unused peripherals off to
make even more reducing current consumpti on.
When certain bits of block control registers are set to “1”, corresponding peripherals are reset (all registers are reset) and
operating clocks for the peripherals stop. Writing to every SFR (special function register) in the corresponding perip her a ls
is not valid while the bits of block control registers are set to “1” and returns the initial value for read. Ensure the b its are
reset to “0” before using the peripherals to enable the operation.
BLKCON2 register controls (enables or disables) the operation of Synchronous Serial Port, UART0, UART1, and I2C.
BLKCON4 register controls (enables or disables) the operation of SA type A/D converter.
BLKCON6 register controls (enables or disables) the operation of Timer8, Timer9, TimerA, TimerB, TimerE and TimerF.
BLKCON7 register controls (enables or disables) the operation of PWMC, PWMD, PWME and PWMF.
Note:
− If the appropriate bit of the block control register is set to “1”, all relevant registers are initialized.
− Refer to the relevant chapter for details of operation or notes of each block.
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Interrupts (INTs)
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Chapter 5 Interrupts (INTs)
5 Interrupts (INTs)
5.1 Overview
This LSI has 31 inter rupt sources (External interrupts: 7 sources, Internal interrupts: 24 sources) and a software interrupt
(SWI).
For details of each interrupt, see the following chapters:
Chapter 7, “Time Base Counter”
Chapter 8, “Timers”
Chapter 9, “Watchdog Timer”
Chapter 10, “PWM”
Chapter 11, “Synchronous Serial Port”
Chapter 12, “UART”
Chapter 13, “I
Chapter 14, “I
Chapter 15, “Por tA”
Chapter 16, “Por tB”
Chapter 19, “Por tAB Interrupts”
Chapter 20, “Successive Approximation Type A/D Converter”
Chapter 21, “Voltage Level Supervisor”
Chapter 22, “Analog Comparator”
5.1.1 Features
2
C Bus Interface (Master)”
2
C Bus Interface (Slave)”
• 1 non-maskable interrupt source s (Internal source)
• 30 maskable interrupt sources (Internal sources: 23, External sources: 7)
• Software interrupt (SWI): 64 sources max.
• External interrupts and Analog Comparator interrupts allow edge selection and sampling selection.
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0F010H
Interrupt enable register 0
IE0
R/W 8 00H
0F011H
Interrupt enable register 1
IE1
R/W 8 00H
0F012H
Interrupt enable register 2
IE2
R/W 8 00H
0F013H
Interrupt enable register 3
IE3
R/W 8 00H
0F014H
Interrupt enable register 4
IE4
R/W 8 00H
0F015H
Interrupt enable register 5
IE5
R/W 8 00H
0F016H
Interrupt enable register 6
IE6
R/W 8 00H
0F017H
Interrupt enable register 7
IE7
R/W 8 00H
0F018H
Interrupt request register 0
IRQ0
R/W 8 00H
0F019H
Interrupt request register 1
IRQ1
R/W 8 00H
0F01AH
Interrupt request register 2
IRQ2
R/W 8 00H
0F01BH
Interrupt request register 3
IRQ3
R/W 8 00H
0F01CH
Interrupt request register 4
IRQ4
R/W 8 00H
0F01DH
Interrupt request register 5
IRQ5
R/W 8 00H
0F01EH
Interrupt request register 6
IRQ6
R/W 8 00H
0F01FH
Interrupt request register 7
IRQ7
R/W 8 00H
Chapter 5 Interrupts (INTs)
5.2 Description of Registers
5.2.1 List of Registers
Address Name Symbol (Byte) Symbol (Word) R/W Size Initial value
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ML610Q111/ML610Q112 User’s Manual
7 6 5 4 3 2 1 0
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
Chapter 5 Interrupts (INTs)
5.2.2 Interrupt Enable Register 0 (IE0)
Address: 0F010H
Access: R/W
Access size: 8 bits
Initial value: 00H
IE0 EVLS
IE0 is a special function register (SFR) to control enable/disable for each interrupt request.
When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corr esponding flag of IE0 is not
reset.
[Description of Bits]
• EVLS (bit 6)
EVLS is the enable flag for the voltage level supervisor interrupt (VLSINT).
EVLS Description
0 Disabled (initial value)
1 Enabled
FEUL610Q111 5-3
ML610Q111/ML610Q112 User’s Manual
7 6 5 4 3 2 1 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
EPB1
Description
0
Disabled (initial value)
1
Enabled
Chapter 5 Interrupts (INTs)
5.2.3 Interrupt Enable Register 1 (IE1)
Address: 0F011H
Access: R/W
Access size: 8 bits
Initial value: 00H
IE1 EPB3 EPB2 EPB1 EPB0 EPA2 EPA1 EPA0
IE1 is a special function register (SFR) to control enable/disable for each interrupt request.
When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE1 is not
reset.
[Description of Bits]
• EPA0 (bit 0)
EPA0 is the enable flag for the input/output port PA0 pin interrupt (PA0INT).
EPA0 Description
0 Disabled (initial value)
1 Enabled
• EPA1 (bit 1)
EPA1 is the enable flag for the input/output port PA1 pin interrupt (PA1INT).
EPA1 Description
0 Disabled (initial value)
1 Enabled
• EPA2 (bit 2)
EPA2 is the enable flag for the input/output port PA2 pin interrupt (PA2INT).
EPA2 Description
0 Disabled (initial value)
1 Enabled
• EPB0 (bit 4)
EPB0 is the enable flag for the input/output port PB0 pin interrupt (PB0INT).
EPB0 Description
0 Disabled (initial value)
1 Enabled
• EPB1 (bit 5)
EPB1 is the enable flag for the input/output port PB1 pin interrupt (PB1INT).
FEUL610Q111 5-4
EPB2
Description
0
Disabled (initial value)
1
Enabled
EPB3
Description
0
Disabled (initial value)
1
Enabled
• EPB2 (bit 6)
EPB2 is the enable flag for the input/output port PB2 pin interrupt (PB2INT).
• EPB3 (bit 7)
EPB3 is the enable flag for the input/output port PB3 pin interrup t (PB3INT).
ML610Q111/ML610Q112 User’s Manual
Chapter 5 Interrupts (INTs)
FEUL610Q111 5-5
ML610Q111/ML610Q112 User’s Manual
7 6 5 4 3 2 1 0
R/W
R/W
R/W
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
Chapter 5 Interrupts (INTs)
5.2.4 Interrupt Enable Register 2 (IE2)
Address: 0F012H
Access: R/W
Access size: 8 bits
Initial value: 00H
IE2 EI2CM EI2CS ESAD ESIO0
IE2 is a special function register (SFR) to control enable/disable for each interrupt request.
When an interr upt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE2 is not
reset.
[Description of Bits]
• ESIO0 (bit 0)
ESIO0 is the enable flag for the synchronous ser ial port0 interrupt (SIO0INT).
ESIO0 Description
0 Disabled (initial value)
1 Enabled
• ESAD (bit 2)
ESAD is the enable flag for the successive approximation type A/D converter interrupt (SADINT).
ESAD Description
0 Disabled (initial value)
1 Enabled
• EI2CS (bit 6)
EI2CS is the enable flag for the I
EI2CS Description
0 Disabled (initial value)
1 Enabled
• EI2CM (bit 7)
EI2CM is the enable flag for the I
EI2CM Description
0 Disabled (initial value)
1 Enabled
2
C bus interface (slave) interrupt (I2CSINT).
2
C bus interface (master) interrupt (I2CMINT).
FEUL610Q111 5-6
ML610Q111/ML610Q112 User’s Manual
7 6 5 4 3 2 1 0
R/W
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
ETM8
Description
0
Disabled (initial value)
1
Enabled
ETM9
Description
0
Disabled (initial value)
1
Enabled
Chapter 5 Interrupts (INTs)
5.2.5 Interrupt Enable Register 3 (IE3)
Address: 0F013H
Access: R/W
Access size: 8 bits
Initial value: 00H
IE3 ETM9 ETM8
IE3 is a special function register (SFR) to control enable/disable for each interrupt request.
When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE3 is not
reset.
[Description of Bits]
• ETM8 (bit 2)
ETM8 is the enable flag for the timer 8 interrupt (TM8INT).
• ETM9 (bit 3)
ETM9 is the enable flag for the timer 9 interrupt (TM9INT).
FEUL610Q111 5-7
ML610Q111/ML610Q112 User’s Manual
7 6 5 4 3 2 1 0
R/W
R/W
R/W
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
EUA0
Description
0
Disabled (initial value)
1
Enabled
EUA1
Description
0
Disabled (initial value)
1
Enabled
ECMP0
Description
1
Enabled
Chapter 5 Interrupts (INTs)
5.2.6 Interrupt Enable Register 4 (IE4)
Address: 0F014H
Access: R/W
Access size: 8 bits
Initial value: 00H
IE4 ECMP1 ECMP0 EUA1 EUA0
IE4 is a special function register (SFR) to control enable/disable for each interrupt request.
When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE4 is not
reset.
[Description of Bits]
• EUA0 (bit 0)
EUA0 is the enable flag for the UART0 interrupt (UA0INT).
• EUA1 (bit 1)
EUA1 is the enable flag for the UART1 interrupt (UA1INT).
• ECMP0 (bit 6)
ECMP0 is the enable flag for the comparator0 interrupt (CMP0INT).
0 Disabled (initial value)
1 Enabled
• ECMP1 (bit 7)
ECMP1 is the enable flag for the comparator1 interrupt (CMP1INT).
ECMP1 Description
0 Disabled (initial value)
FEUL610Q111 5-8
ML610Q111/ML610Q112 User’s Manual
7 6 5 4 3 2 1 0
R/W
R/W
R/W
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
ETME
Description
0
Disabled (initial value)
1
Enabled
ETMF
Description
0
Disabled (initial value)
1
Enabled
0
Disabled (initial value)
1
Enabled
ETMB
Description
0
Disabled (initial value)
1
Enabled
Chapter 5 Interrupts (INTs)
5.2.7 Interrupt Enable Register 5 (IE5)
Address: 0F015H
Access: R/W
Access size: 8 bits
Initial value: 00H
IE5 ETMB ETMA ETMF ETME
IE5 is a special function register (SFR) to control enable/disable for each interrupt request.
When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE5 is not
reset.
[Description of Bits]
• ETME (bit 4)
ETME the enable flag for the timer E interrupt (TMEINT).
• ETMF (bit 5)
ETMF the enable flag for the timer F interrupt (TMFINT)
• ETMA (bit 6)
ETMA the enable flag for the timer A interrupt (TMAINT).
ETMA Description
• ETMB (bit 7)
ETMB the enable flag for the timer B interrupt (TMBINT)
FEUL610Q111 5-9
ML610Q111/ML610Q112 User’s Manual
7 6 5 4 3 2 1 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
EPWC
Description
0
Disabled (initial value)
1
Enabled
EPWD
Description
0
Disabled (initial value)
1
Enabled
EPWE
Description
1
Enabled
0
Disabled (initial value)
1
Enabled
E32H
Description
0
Disabled (initial value)
1
Enabled
Chapter 5 Interrupts (INTs)
5.2.8 Interrupt Enable Register 6 (IE6)
Address: 0F016H
Access: R/W
Access size: 8 bits
Initial value: 00H
IE6 E32H E128H EPWF EPWE EPWD EPWC
IE6 is a special function register (SFR) to control enable/disable for each interrupt request.
When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE6 is not
reset.
[Description of Bits]
• EPWC (bit 0)
EPWC is the enable flag for the PWMC interrupt (PWCINT)
• EPWD (bit 1)
EPWD is the enable flag for the PWMD interrupt (PWDINT)
• EPWE (bit 2)
EPWE is the enable flag for the PWME interrupt (PWEINT)
0 Disabled (initial value)
1 Enabled
• EPWF (bit 3)
EPWF is the enable flag for the PWMF interrupt (PWFINT)
EPWF Description
0 Disabled (initial value)
• E128H (bit 5)
E128H is the enable flag for the time base counter 128 Hz interrupt (T128HINT).
E128H Description
• E32H (bit 7)
E32H is the enable flag for the time base counter 32 Hz interrupt (T32HINT).
FEUL610Q111 5-10
5.2.9 Interrupt Enable Register 7 (IE7)
7 6 5 4 3 2 1 0
R/W
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
Address: 0F017H
Access: R/W
Access size: 8 bits
Initial value: 00H
ML610Q111/ML610Q112 User’s Manual
Chapter 5 Interrupts (INTs)
IE7
IE7 is a special function register (SFR) to control enable/disable for each interrupt request.
When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE7 is not
reset.
[Description of Bits]
• E16H (bit 0)
E16H is the enable flag for the time base counter 16 Hz interrupt (T16HINT).
E16H Description
0 Disabled (initial value)
1 Enabled
• E2H (bit 3)
E2H is the enable flag for the time base counter 2 Hz interrupt (T2HINT).
E2H Description
0 Disabled (initial value)
1 Enabled
E2H E16H
FEUL610Q111 5-11
ML610Q111/ML610Q112 User’s Manual
7 6 5 4 3 2 1 0
R/W
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
QVLS
Description
0
No request (initial value)
1
Request
Chapter 5 Interrupts (INTs)
5.2.10 Interrupt Request Register 0 (IRQ0)
Address: 0F018H
Access: R/W
Access size: 8 bits
Initial value: 00H
IRQ0 QVLS QWDT
IRQ0 is a special function register (SFR) to request an interrupt for each interrupt source.
The watchdog timer interrupt (WDTINT) is a non-maskable interrupt that do not depend on MIE. In this case, an interrupt
is requested to the CPU regardless of the value of the Mask Interrupt Enable flag (MIE).
Each IRQ0 request flag is set to “1” regardless of the MIE value when an interrupt is generated. By setting the IRQ0
request flag to “1” by software, an interrupt can be generated.
The corr esponding flag of IRQ0 is set to “0” by hardware when the interrupt request is accepted by the CPU.
[Description of Bits]
• QWDT (bit 0)
QWDT is the request flag for the watchdog timer interrupt (WDTINT).
QWDT Description
0 No request (initial value)
1 Request
• QVLS (bit 6)
QVLS is the request fla g for the volage level supervisor interrupt (VLSINT)
Note:
When an interrupt is generated by the write instruction to the interrupt request register (IRQ0), the interrupt shift cycle
starts after the next 1 instruction is executed.
FEUL610Q111 5-12
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7 6 5 4 3 2 1 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
QPA1
Description
0
No request (initial value)
1
Request
QPA2
Description
0
No request (initial value)
1
Request
QPB0
Description
0
No request (initial value)
1
Request
Chapter 5 Interrupts (INTs)
5.2.11 Interrupt Request Register 1 (IRQ1)
Address: 0F019H
Access: R/W
Access size: 8 bits
Initial value: 00H
IRQ1 QPB3 QPB2 QPB1 QPB0 QPA2 QPA1 QPA0
IRQ1 is a special function register (SFR) to request an interrupt for each interrupt source.
Each IRQ1 request flag is set to “1” regardless of the IE1 and MIE values when an interrupt is generated. In this case, an
interrupt is requested to the CPU when the related flag of the interrupt enable register (IE1) is set to “1” and the master
interrupt enable flag (MIE) is set to “1”.
By setting the IRQ1 request flag to “1” by software, an interrupt can be generated.
The corresponding flag of IRQ1 is set to “0” by hardware when the interrupt request is accepted by the CPU.
[Description of Bits]
• QPA0 (bit 0)
QPA0 is the request flag for the input port PA0 pin interrupt (PA0INT).
QPA0 Description
0 No request (initial value)
1 Request
• QPA1 (bit 1)
QPA1 is the request flag for the input port PA1 pin interrupt (PA1INT).
• QPA2 (bit 2)
QPA2 is the request flag for the input port PA2 pin interrupt (PA2INT).
• QPB0 (bit 4)
QPB0 is the request flag for the input port PB0 pin interrupt (PB0INT).
FEUL610Q111 5-13
• QPB1 (bit 5)
QPB1
Description
0
No request (initial value)
1
Request
QPB1 is the request flag for the input port PB1 pin interrupt (PB1INT).
• QPB2 (bit 6)
QPB2 is the request flag for the input port PB2 pin interrupt (PB2INT).
QPB2 Description
0 No request (initial value)
1 Request
• QPB3 (bit 7)
QPB3 is the request flag for the input port PB3 pin interrupt (PB3INT).
QPB3 Description
0 No request (initial value)
1 Request
ML610Q111/ML610Q112 User’s Manual
Chapter 5 Interrupts (INTs)
Note:
When an interrupt is generated by the write instruction to the interrupt request register (IRQ1) or to the interrupt enable
register (IE1), the interrupt shift cycle starts after the next 1 instruction is executed.
FEUL610Q111 5-14
ML610Q111/ML610Q112 User’s Manual
7 6 5 4 3 2 1 0
R/W
R/W
R/W
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
QSAD
Description
0
No request (initial value)
1
Request
QI2CS
Description
0
No request (initial value)
1
Request
QI2CM
Description
0
No request (initial value)
1
Request
Chapter 5 Interrupts (INTs)
5.2.12 Interrupt Request Register 2 (IRQ2)
Address: 0F01AH
Access: R/W
Access size: 8 bits
Initial value: 00H
IRQ2 QI2CM QI2CS QSAD QSIO0
IRQ2 is a special function register (SFR) to request an interrupt for each interrupt source.
Each IRQ2 request flag is set to “1” regardless of the IE2 and MIE values when an interrupt is generated. In this case, an
interrupt is requested to the CPU when the related flag of the interrupt enable register (IE2) is set to “1” and the master
interrupt enable flag (MIE) is set to “1”.
By setting the IRQ2 request flag to “1” by software, an interrupt can be generated.
The corr esponding flag of IRQ2 is set to “0” by hardware when the interrupt request is accepted by the CPU.
[Description of Bits]
• QSIO0 (bit 0)
QSIO0 is the request flag for the synchronous serial port 0 interrupt (SIO0INT)
QSIO0 Description
0 No request (initial value)
1 Request
• QSAD (bit 2)
QSAD is the request flag for the successive approximation type A/D converter interrupt (SADINT)
• QI2CS (bit 6)
QI2CS is the request flag for the I
2
C bus interface (slave) interrupt (I2CSINT)
• QI2CM (bit 7)
QI2CM is the request flag for the I
2
C bus interface (master) interrupt (I2CMINT)
Note:
When an interrupt is generated by the write instruction to the interrupt request register (IRQ2) or to the interrupt enable
register (IE2), the interrupt shift cycle starts after the next 1 instruction is executed.
FEUL610Q111 5-15
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7 6 5 4 3 2 1 0
R/W
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
QTM9
Description
0
No request (initial value)
1
Request
Chapter 5 Interrupts (INTs)
5.2.13 Interrupt Request Register 3 (IRQ3)
Address: 0F01BH
Access: R/W
Access size: 8 bits
Initial value: 00H
IRQ3 QTM9 QTM8
IRQ3 is a special function register (SFR) to request an interrupt for each interrupt source.
Each IRQ3 request flag is set to “1” regardless of the IE3 and MIE values when an interrupt is generated. In this case, an
interrupt is requested to the CPU when the related flag of the interrupt enable register (IE3) is set to “1” and the master
interrupt enable flag (MIE) is set to “1”.
By setting the IRQ3 request flag to “1” by software, an interrupt can be generated.
The corr esponding flag of IRQ3 is set to “0” by hardware when the interrupt request is accepted by the CPU.
[Description of Bits]
• QTM8 (bit 2)
QTM8 is the request flag for the timer 8 interrupt (TM8INT).
QTM8 Description
0 No request (initial value)
1 Request
• QTM9 (bit 3)
QTM9 is the request flag for the timer 9 interrupt (TM9INT).
Note:
When an interrupt is generated by the write instruction to the interrupt request register (IRQ3) or to the interrupt enable
register (IE3), the interrupt shift cycle starts after the next 1 instruction is executed.
FEUL610Q111 5-16
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7 6 5 4 3 2 1 0
R/W
R/W
R/W
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
QUA1
Description
0
No request (initial value)
1
Request
QCMP0
Description
0
No request (initial value)
1
Request
QCMP1
Description
0
No request (initial value)
1
Request
Chapter 5 Interrupts (INTs)
5.2.14 Interrupt Request Register 4 (IRQ4)
Address: 0F01CH
Access: R/W
Access size: 8 bits
Initial value: 00H
IRQ4 QCMP1 QCMP0 QUA1 QUA0
IRQ4 is a special function register (SFR) to request an interrupt for each interrupt source.
Each IRQ4 request flag is set to “1” regardless of the IE4 and MIE values when an interrupt is generated. In this case, an
interrupt is requested to the CPU when the related flag of the interrupt enable register (IE4) is set to “1” and the master
interrupt enable flag (MIE) is set to “1”.
By setting the IRQ4 request flag to “1” by software, an interrupt can be generated.
The corr esponding flag of IRQ4 is set to “0” by hardware when the interrupt request is accepted by the CPU.
[Description of Bits]
• QUA0 (bit 0)
QUA0 is the request flag for the UART0 interrupt (UA0INT).
QUA0 Description
0 No request (initial value)
1 Request
• QUA1 (bit 1)
QUA1 is the request flag for the UART1 interrupt (UA1INT).
• QCMP0 (bit 6)
QCMP0 is the request flag for comparator0 interrupt (CMP0INT).
• QCMP1 (bit 7)
QCMP1 is the request flag for comparator1 interrupt (CMP1INT).
Note:
When an interrupt is generated by the write instruction to the interrupt request register (IRQ4) or to the interrupt enable
register (IE4), the interrupt shift cycle starts after the next 1 instruction is executed.
FEUL610Q111 5-17
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7 6 5 4 3 2 1 0
R/W
R/W
R/W
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
QTMF
Description
0
No request (initial value)
1
Request
QTMA
Description
0
No request (initial value)
1
Request
QTMB
Description
0
No request (initial value)
1
Request
Chapter 5 Interrupts (INTs)
5.2.15 Interrupt Request Register 5 (IRQ5)
Address: 0F01DH
Access: R/W
Access size: 8 bits
Initial value: 00H
IRQ5 QTMB QTMA QTMF QTME
IRQ5 is a special function register (SFR) to request an interrupt for each interrupt source.
Each IRQ5 request flag is set to “1” regardless of the IE5 and MIE values when an interrupt is generated. In this case, an
interrupt is requested to the CPU when the related flag of the interrupt enable register (IE5) is set to “1” and the master
interrupt enable flag (MIE) is set to “1”.
By setting the IRQ5 request flag to “1” by software, an interrupt can be generated.
The corr esponding flag o f IRQ5 is set to “0” by hardware when the interrupt request is accepted by the CPU.
[Description of Bits]
• QTME (bit 4)
QTME is the request flag for the timer E interrupt (TMEINT).
QTME Description
0 No request (initial value)
1 Request
• QTMF (bit 5)
QTMF is the request flag for the timer F interrupt (TMFINT).
• QTMA (bit 6)
QTMA is the request flag for the timer A interrupt (TMAINT).
• QTMB (bit 7)
QTMB is the request flag for the timer B interrupt (TMBINT).
Note:
When an interrupt is generated by the write instruction to the interrupt request register (IRQ5) or to the interrupt enable
register (IE5), the interrupt shift cycle starts after the next 1 instruction is executed.
FEUL610Q111 5-18
ML610Q111/ML610Q112 User’s Manual
7 6 5 4 3 2 1 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
QPWD
Description
0
No request (initial value)
1
Request
QPWE
Description
0
No request (initial value)
1
Request
QPWF
Description
0
No request (initial value)
1
Request
Q128H
Description
0
No request (initial value)
1
Request
Chapter 5 Interrupts (INTs)
5.2.16 Interrupt Request Register 6 (IRQ6)
Address: 0F01EH
Access: R/W
Access size: 8 bits
Initial value: 00H
IRQ6 Q32H Q128H QPWF QPWE QPWD QPWC
IRQ6 is a special function register (SFR) to request an interrupt for each interrupt source.
Each IRQ6 request flag is set to “1” regardless of the IE6 and MIE values when an interrupt is generated. In this case, an
interrupt is requested to the CPU when the related flag of the interrupt enable register (IE6) is set to “1” and the master
interrupt enable flag (MIE) is set to “1”.
By setting the IRQ6 request flag to “1” by software, an interrupt can be generated.
The corr esponding flag of IRQ6 is set to “0” by hardware when the interrupt request is accepted by the CPU.
[Description of Bits]
• QPWC (bit 0)
QPWC is the request flag for the PWMC interrupt (PWCINT).
QPWC Description
0 No request (initial value)
1 Request
• QPWD (bit 1)
QPWD is the request flag for the PWMD interrupt (PWDINT).
• QPWE (bit 2)
QPWE is the request flag for the PWME interrupt (PWEINT).
• QPWF (bit 3)
QPWF is the request flag for the PWMF interrupt (PWFCINT).
• Q128H (bit 5)
Q128H is the request flag for the time base counter 128 Hz interrupt (T128HINT).
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Q32H
Description
0
No request (initial value)
1
Request
Chapter 5 Interrupts (INTs)
• Q32H (bit 7)
Q32H is the request flag for the time base counter 32 Hz interrupt (T32HINT).
Note:
When an interrupt is generated by the write instruction to the interrupt request register (IRQ6) or to the interrupt enable
register (IE6), the interrupt shift cycle starts after the next 1 instruction is executed.
FEUL610Q111 5-20
5.2.17 Interrupt Request Register 7 (IRQ7)
7 6 5 4 3 2 1 0
R/W
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
Q2H
Description
0
No request (initial value)
1
Request
Address: 0F01FH
Access: R/W
Access size: 8 bits
Initial value: 00H
ML610Q111/ML610Q112 User’s Manual
Chapter 5 Interrupts (INTs)
IRQ7
Q2H Q16H
IRQ7 is a special function register (SFR) to request an interrupt for each interrupt source.
Each IRQ7 request flag is set to “1” regardless of the IE7 and MIE values when an interrupt is generated. In this case, an
interrupt is requested to the CPU when the related flag of the interrupt enable register (IE7) is set to “1” and the master
interrupt enable flag (MIE) is set to “1”.
By setting the IRQ7 request flag to “1” by software, an interrupt can be generated.
The corresponding flag of IRQ7 is set to “0” by hardware when the interrupt request is accepted by the CPU.
[Description of Bits]
• Q16H (bit 0)
Q16H is the request flag for the time base counter 16 Hz interrupt (T16HINT).
Q16H Description
0 No request (initial value)
1 Request
• Q2H (bit 3)
Q2H is the request flag for the time base counter 2 Hz interrupt (T2HINT).
Note:
When an interrupt is generated by the instruction to write to the interrupt request register (IRQ7) or to the interrupt enable
register (IE7), the interrupt shift cycle starts after the next 1 instruction is executed.
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Chapter 5 Interrupts (INTs)
5.3 Description of Operation
With the exception of the watchdog timer interrupt (WDTINT), interrupt enab le /disable for 30 sources is controlled by the
master interrupt enable flag (MIE) and the individual interrupt enable registers (I E0 to 7). WDTINT is non-maskable
interrupts.
When the interrupt conditions are satisfied, the CPU calls a branching destination address from the vector table determined
for each interrupt source and the interrupt shift cycle starts to branch to the interrupt processing routine.
Table 5-1 lists the interrupt sources.
Table 5-1 Interrupt Sources
Priority Interrupt source Symbol
1 Watchdog timer interrupt WDTINT 0008H
3 Voltage level supervisor interrupt VLSINT 000CH
5 PA0 interrupt PA0INT 0010H
6 PA1 interrupt PA1INT 0012H
7 PA2 interrupt PA2INT 0014H
9 PB0 interrupt PB0INT 0018H
10 PB1 interrupt PB1INT 001AH
11 PB2 interrupt PB2INT 001CH
12 PB3 interrupt PB3INT 001EH
13 Synchronous Serial Port0 interrupt SIO0INT 0020H
15 Successive approximation type A/D converter interrupt SADINT 0024H
19 I2C Bus Interface (Slave) interrupt I2CSINT 002CH
20 I2C Bus Interface (Master) interrupt I2CMINT 002EH
23 Timer 8 interrupt TM8INT 0034H
24 Timer 9 interrupt TM9INT 0036H
29 UART 0 interrupt UA0INT 0040H
30 UART 1 interrupt UA1INT 0042H
35 Comparator interrupt0 CMP0INT 004CH
36 Comparator interrupt1 CMP1INT 004EH
41 Timer E interrupt TMEINT 0058H
42 Timer F interrupt TMFINT 005AH
43 Timer A interrupt TMAINT 005CH
44 Timer B interrupt TMBINT 005EH
45 PWMC interrupt PWCINT 0060H
46 PWMD interrupt PWDINT 0062H
47 PWME interrupt PWEINT 0064H
48 PWMF interrupt PWFINT 0066H
50 TBC128Hz interrupt T128HINT 006AH
52 TBC32Hz interrupt T32HINT 006EH
53 TBC16Hz interrupt T16HINT 0070H
56 TBC2Hz interrupt T2HINT 0076H
Vector table
address
Note:
− When multiple interrupts are generated concurrently, the interrupts are serviced according to this priority and processing
of low-priority interrupts is pending.
− Watchdog timer (W DTINT) is a non-maskable interrupt. When WDTINT occurs during maskable interrupt processing,
regardless of permission, the prohibition of the multiplex interrupt of the maskable interrupt, the interrupt processing is
suspended and WDTINT is processed with high priority.
− Please define vector tables for all unused interrupts for fail safe. If unused interrupt occurs, CPU may lose control. We
recommend initializing the LSI via watchdog timer reset which occurs by the infinite loop.
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Chapter 5 Interrupts (INTs)
5.3.1 Maskable Interrupt Processing
When an interr upt is generated with the MIE flag set to “1”, the following processing is executed by hardware and the
processing of program shifts to the interrupt destination.
(1) Transfer the program counter (PC) to ELR1.
(2) Transfer CSR to ECSR1.
(3) Transfer PSW toEPSW1.
(4) Set the MIE flag to “0”.
(5) Set the ELEVEL field to“1”.
(6) Load the interrupt start address into PC.
5.3.2 Non-Maskable Interrupt Processing
When an interr upt is generated regardless of the state of MIE flag, the following processing is performed by hardware and
the processing of program shifts to the interrupt destination.
(1) Transfer PC to ELR2.
(2) Transfer CSR to ECSR2.
(3) Transfer PSW to EPSW2.
(4) Set the ELEVEL field to “2”.
(5) Load the interrupt start address into PC.
5.3.3 Software Interrupt Processing
A software interrupt is generated as required within an application program. When the SWI instruction is performed within
the program, a software interrupt is generated, the following processing is performed by hardware, and the processing
program shifts to the interrupt destination. The vector table is specified by the SWI instruction.
(1) Transfer PC to ELR1.
(2) Transfer CSR to ECSR1.
(3) Transfer PSW to EPSW1.
(4) Set the MIE flag to “0”.
(5) Set the ELEVEL field to “1”.
(6) Load the interrupt start address into PC.
Reference:
For the MIE flag, Program Counter (PC), CSR, PSW, and ELEVEL, see “nX-U8/100 Core Ins truction Manual”.
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Example of description: State A-1-1
Example of description: State A-1-2
Intrpt_A-1-1;
; A-1-1 state
Intrpt_A-1-2;
; Start
beginning
:
EI
; Enable interrupt
:
: RTI
; Return PC from ELR
: ; Return PSW form EPSW
: ; End :
:
POP PC, PSW
; Return PC from the stack
; Return PSW from the stack
; End
Chapter 5 Interrupts (INTs)
5.3.4 Notes on Interrupt Routine
Notes are different in programming depending on whether a subroutine is called or not by the program in executing an
interrupt routine, whether multiple interrupts are enabled or disabled, and whether such interrupts are maskable or
non-maskable.
State A: Maskable interrupt is being processed
A-1: When a subrouti ne is not called by the program in executi ng an interrupt routine
A-1-1: When multiple interrupts are disabled
• Processing immediately after the start of interrupt routine execution
No specific notes.
• Processing at the end of interrupt routine execution
Specify the RTI instruction to return the contents of the ELR register to the PC and those of the EPSW register to
PSW.
A-1-2: When multiple interrupts are enabled
• Processing immediately after the start of interrupt routine execution
Specify “PUSH ELR, EPSW” to save the interrupt return address and the PSW status in the stack.
• Processing at the end of interrupt routine execution
Specify “POP PC, PSW” instead of the RTI instruction to return the contents of the stack to PC and PSW.
DI ; Disable interrupt PUSH ELR, EPSW
:
; Save ELR and EPSW at the
FEUL610Q111 5-24
Example of description: A-2-2
Intrpt_A-2-2;
; Start
EI
; Enable interrupt
: Sub_1; ; :
DI
; Disable interrupt
:
: :
BL Sub_1
; Call subroutine Sub_1
:
:
RT
; Return PC from LR
POP PC, PSW, LR
; Return PC from the stack
; End of subroutine
; Return PSW from the stack
; Return LR from the stack
; End
A-2: When a subroutine is called by the program in executing an interrupt routine
A-2-1: When multiple interrupts are disabled
• Processing immediately after the start of interrupt routine execution
Specify the “PUSH LR” instruction to save the subroutine return address in the stack.
• Processing at the end of interrupt routine execution
Specify “POP LR” immediately before the RTI instruction to return from the inter rupt proce ssing after retur ning the
subroutine return address to LR.
A-2-2: When multiple interrupts are enabled
• Processing immediately after the start of interrupt routine execution
Specify “PUSH LR, ELR, EPSW” to save the interrup t r etur n add re ss, the subro utine retur n ad dre ss, and the EPSW
status in the stack.
• Processing at the end of interrupt routine execution
Specify “POP PC, PSW, LR” instead of the RTI instruction to return the saved d ata of the interrupt return address to
PC, the saved data of EPSW to PSW, and the saved data of LR to LR.
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Chapter 5 Interrupts (INTs)
PUSH ELR, EPSW,
LR
; Save ELR, EPSW, LR at
the beginning
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Example of description: State B-1
Example of description: State B-2-1
Intrpt_B-1;
; B-1 state
Intrpt_B-2-2;
; Start
beginning
; Return PSW form EPSW
: ; End :
:
POP PC, PSW
; Return PC from the stack
; Return PSW from the stack
; End
Intrpt_B-2-2;
; Start
:
Sub_1; :
:
: :
BL Sub_1
; Call subroutine Sub_1
:
:
RT
; Return PC from LR
POP PC, PSW, LR
; Return PC from the stack
; End of subroutine
stack
State B: Non-maskable interrupt is being processed
B-1: When a subroutine is not called
• Processing immediately after the start of interrupt routine execution
Specify the RTI instruction to return the contents of the ELR register to PC and those of the EPSW register to PSW.
B-2: When a subroutine is called
B-2-1: When a subroutine is not called for an interrupti on routine to a r un time by a program
• Processing immediately after the start of interrupt routine execution
"PUSH ELR, EPSW" are specified and the return address of an interruption and the status of EPSW are evacuated to
a stack.
• Processing at the end of interrupt routine execution
Specifying "POP PC, PSW" instead of a RTI supervisor call, the save data of EPSW returns the save data of the
return address of an interruption to PC at PSW. B-2-2: Whe n a sub ro uti ne i s ca lle d for a n inte r rup ti on r o uti ne to a run
time by a program
• Processing immediately after the start of interrupt routine execution
"PUSH LR, ELR, EPSW" are specified and the return address of an inte rruption, the r eturn addre ss of a subroutine ,
and the status of EPSW are evacuated to a stack.
• Processing at the end of interrupt routine execution
Specifying "POP PC, PSW, LR" instead of a RTI supervisor call, as for the save data of the return address of an
interruption, the save data of EPSW returns the save data o f LR to LR to PC to PSW.
Chapter 5 Interrupts (INTs)
RTI ; Return PC from ELR PUSH ELR, EPSW
Example of description: B-2-2
PUSH ELR, EPSW,
LR
; Save ELR, EPSW, LR at
the beginning
; Return PSW from the
; Save ELR and EPSW at the
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Chapter 5 Interrupts (INTs)
5.3.5 Interrupt Disable State
Even if the interrupt conditions are satisfied, an interrupt may not be accepted depending on the operating state. This is
called an interrupt disabled state. See b e low for the interrupt disabled state and the handling of interrupts in this state.
Interrupt disabled state 1: Between the interrupt shift cycle and the instruction at the beginning of the interrupt routine
When the interrupt conditions are satisfied in this section, an interrupt is generated immediately following the execution
of the instruction at the beginning of the interrupt rout ine correspo nding to the interrupt that has already been enabled.
Interrupt disabled state 2: Between the DSR prefix instruction and the next instruction
When the interrupt conditions are satisfied in this section, an interrupt is generated immediately after execution of the
instruction following the DSR prefix instruction.
Reference:
For the DSR prefix instruction, see “nX-U8/100 Core Instruction Manual”.
FEUL610Q111 5-27
Chapter 6
Clock Ge neration Circuit
ML610Q111/ML610Q112 User’s Manual
OSCLK
Chapter 6 Clock Generation Circuit
6 Clock Gener at ion Circ uit
6.1 Overview
The clock generation circuit generates and provides a low-speed clock (LSCLK), high-speed clock (HSCLK), built-in PLL
clock (PLLCLK), high-speed oscillation clock (OSCLK), system clock (SYSCLK), low-speed output clock ( LSCLK), and
high-speed output clock (OUTCLK). LSCLK, and HSCLK are time base clocks for the peripheral circuits, SYSCLK is a
basic operation clock of CPU, and LSCLK/OUTCLK is a clock that is output from a port.
For the LSCLK and OUTCLK output port, see Chapter 15, “Port A” and Chapter 16, “Port B”.
Additionally, for the STOP mode described in this chapter, see Chapter 4, “MCU Control Function”.
6.1.1 Features
• Low-speed clock generation circuit:
− Built-in RC oscillation (32.768kHz) mode
• High-speed clock generation circuit: Software selection
− Built-in PLL oscillation mode
− External clock input mode
6.1.2 Configuration
Figure 6-1 shows the configuration of the clock generation circuit.
Low-speed
clock generation
circuit
PA2,PB6/CLKIN
High-speed
clock generation
circuit
PLL
FCON0 : Frequency control register 0
FCON1 : Frequency control register 1
1/2
Divide ratio
selection
1/1, 1/2, 1/4, 1/8
Divide ratio
selection
1/1, 1/2, 1/4, 1/8
FCON0, FCON1
Low-speed output clock
(PA1,PB7/LSCLK)
Low-speed clock
(LSCLK)
System clock
(SYSCLK)
High-speed clock
(HSCLK)
High-speed oscillation c l ock
(OSCLK)
High-speed output clock
(PA0,PB0/OUTCLK)
Built-in PLL clock
(PLLCLK)
Data bus
Figure 6-1 Configuration of Clock Generation Circuit
Note:
This LSI starts operation with the 32.768kHz RC oscillation clock after power-on or a system reset. At initialization by
software, set the FCON0, FCON1 register to switch the clock to a required one.
FEUL610Q111 6-1
6.1.3 List of Pins
Used for the tertiary function of the PA0 pin
Used for the tertiary function of the PB0 pin
Used for the tertiary function of the PA2 pin
Used for the secondary function of the PB6 pin
Used for the tertiary function of the PA1 pin
Used for the secondary function of the PB7 pin
Pin name I/O Description
PA0/OUTCLK O
High-speed clock output pin
ML610Q111/ML610Q112 User’s Manual
Chapter 6 Clock Generation Circuit
PB0/OUTCLK O
PA2/CLKIN I
PB6/CLKIN I
PA1/LSCLK O
PB7/LSCLK O
High-speed clock output pin
External clock input pin
External clock input pin
Low-speed clock output pin
Low-speed clock output pin
6.2 Description of Registers
6.2.1 List of Registers
Address Name Symbol (Byte) Symbol (Word) R/W Size
0F002H
0F003H
Frequency control register 0
Frequency control register 1
FCON0
FCON1 R/W 8 00H
FCON
Initial
value
R/W 8/16 3BH
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ML610Q111/ML610Q112 User’s Manual
R/W
R/W
R/W
R
R/W
R/W
R/W
Initial value
0 0 1 1 1 0 1
1
SYSC1
SYSC0
Description
0
1
1/2OSCLK
1
1
1/8OSCLK (initial value)
OSCM0
Description
0
Built-in PLL oscillation mode (initial value)
0
0
1
0
1
1
1/8 OSCLK (initial value)
Chapter 6 Clock Generation Circuit
6.2.2 Frequency Control Register 0 (FCON0)
Address: 0F002H
Access: R/W
Access size: 8/16 bits
Initial value: 3BH
7 6 5 4 3 2 1 0
FCON0 OUTC1 OUTC0 OSCM1 OSCM0 SYSC1 SYSC0
FCON0 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock.
OSCM1 always returns the value “1”.
[Description of Bits]
• SYSC1, SYSC0 (bits 1, 0)
The SYSC1 and SYSC0 bits are used to select the frequency of the high-speed clock (HSCLK) used for system clock and
peripheral circuits (including high-speed time base counter). OSCLK, 1/2OSCLK, 1/4OSCLK, or 1/8OSCLK can be
selected. The maximum operating frequency guaranteed for the system clock (SYSCLK) of this LSI is 8.192MHz.
At system reset, 1/8OSCLK is selected.
0 0
1 0
OSCLK
1/4OSCLK
• OSCM0 (bits 2)
The OSCM0 bit is used to select the mode of the high-speed clock generation circuit. PLL oscillation mode, or exter nal
clock input mode can be selected.
The setting of OSCM0 can be changed o nly when high-speed oscillation is being stopped (ENOSC bit of FCON1 is “0”).
At system reset, PLL oscillation mode is selected.
1
External clock input mode (PA2,PB6/CLKIN)
• OUTC1, OUTC0 (bits 5, 4)
The OUTC1 and OUTC0 bits are used to select the frequency of the high-speed output cloc k which is output when the
tertiary function of PA0 pin, PB0 pin are used.
OSCLK, 1/2OSCLK, 1/4OSCLK, or 1/8OSCLK can be selected.
At system reset, 1/8OSCLK is selected.
OUTC1 OUTC0 Description
OSCLK
0 1
1/2 OSCLK
1/4 OSCLK
Note:
− To switch the mode of the high-speed clock generation circuit using the OSCM0 bit, stop the high-speed oscillation and
set the system clock to the low-speed clock (set the ENOSC bit and SYSCLK of FCON1 to “0”).
− In external clock mode, an external clock is input from the PA2/CLKIN, PB6/CLKIN pin. And in external clock mode, input
a clock that does not exceed 8.192 MHz.
− In external clock mode, when using PA2/CLKIN and PB6/CLKIN as external clock input pin, PA2/CLKIN has the higher
priority.
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ML610Q111/ML610Q112 User’s Manual
R/W
R
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
0
ENOSC
Description
1
Enables high-speed oscillation
LPLL
Description
1
Chapter 6 Clock Generation Circuit
6.2.3 Frequency Control Register 1 (FCON1)
Address: 0F003H
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
FCON1 LPLL ENOSC SYSCLK
FCON1 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock.
[Description of Bits]
• SYSCLK (bit 0)
The SYSCLK bit is used to select system clock. It allows selection of the low-speed clock (LSCLK) or HSCLK
(1/nOSCLK: n = 1 , 2, 4, 8) selected by using the high-speed clock frequency select bit (SYSC1, 0) of FCON0.
When the oscillation of high-speed clock is stopped (ENOSC bit = “0”), the SYSCLK bit is fixed to “0” and the
low-speed clock (LSCLK) is selected for system clock.
SYSCLK Description
LSCLK (initial value)
1
• ENOSC (bit 1)
The ENOSC bit is used to select enable/disable of the oscillation of the high-speed clock oscillator.
HSCLK
0
Disables high-speed oscillation (initial value)
• LPLL (bit 7)
The LPLL bit is used as a flag to indicate the oscillation state of PLL oscillation.
When the LPLL bit is set to “1”, this indicates that the PLL oscillation is available. W hen the LPLL bit is set to “0”, this
indicates that the PLL oscillation is inactive or the PLL oscillation is not available.
LPLL is a rea d-only bit.
0
Disables the use of PLL oscillation (initial value)
Enables the use of PLL oscillation
Note:
− LPLL flag is a reference flag. The oscillation stabilization time for 3ms (max) is required after PLL oscillation starting.
− Although the oscillated frequency of PLL is 16.384MHz, a CPU clock is a maximum of 8.192MHz.
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RC 32.768kHz
Chapter 6 Clock Generation Circuit
6.3 Description of Operation
6.3.1 Low-Speed Clock
6.3.1.1 Low-Speed Clock Generation Circuit (built-in RC oscillating circuit)
Figure 6-2 shows the circuit configuration of the l ow-speed clock generation circuit.
The 32.768kHz RC oscillation clock generation circuit is activated by the occurrence of power ON reset or port reset or
WDT reset or VLS reset. In starting by reset, after waiting oscillation stable time (256 counts), the clock is supplied to the
peripheral circuit. In the return from a STOP mode, a fter waiting oscillation stable time(32 coounts), a clock is supplied to
a peripheral circuit.
STOP mode
oscillating circuit
Figure 6-2 Circuit Configuration of RC 32.768 kHz Oscillation Mode
Enable of the oscillation
256/32 counts
LSCLK(Low-speed oscillation clock)
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ML610Q111/ML610Q112 User’s Manual
LSCLK
Generation of external interrupt
LSCLK
Low-speed clock
Low-speed clock
LSCLK waveform
STOP
Chapter 6 Clock Generation Circuit
6.3.1.2 Operation of Low-Speed Clock Generation Circuit
The low-speed clock generation circuit is activated by the occurrence of power-on reset.
The low-speed clock (LSCLK) is supplied to the peripheral circuits after a lapse of the low-speed clock oscillation
stabilization period (256 counts) after power-on.
When the low-speed clock generation circuit shifts to STOP mode by software, it stops oscillation. It resumes oscillation
when the STOP mode is released by an external interrupt. Then, LSCLK is supplied to the peripheral circuits after a lapse
of the low-speed clock oscillation stabilization period (32 counts). For STOP mode, see Chapter 4, “MCU Control
Function”.
Figure 6-3 shows the waveforms of the low-speed clock generation circuit.
Power supply V
Low-speed clock
oscillation waveform
Low-speed clock
RESET
LSCLK
DD
Low-speed clock oscillati on waveform
LSCLK
256 counts
supply start
waveform
mode
Low-speed clock oscillati on waveform
32 counts
supply start
Figure 6-3 Operation of Low-Speed Clock Generation Circuit
Note:
After the power supply is turned on, CPU starts operation with a low-speed clock (RC 32.768kHz oscillation).
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ML610Q111/ML610Q112 User’s Manual
ENOSC (Enables oscillation)
1/2
Chapter 6 Clock Generation Circuit
6.3.2 High-Speed Clock
For the high-speed clock generation circuit, built-in PLL oscillation mode or external clock input mode can be selected by
the OSCM1 bit and OSCM0 bit of the frequecy control register0 (FCON0).
6.3.2.1 Built-in PLL Oscillation Mode
The PLL oscillation circuit generates the PLLCLK, which is a clock of 16.384 MHz (= 32.768 kHz × 500).
And the clock generated by dividing the PLLCLK by 2, which is used as high-speed oscillation clock (OSCLK).
When the frequency of a PLL oscillation clock is less than 16.384MHz ± 1.0%, the LPLL flag of FCON1 is set t o "1."
In built-in PLL oscillation mode (OSCM0 = “0”, OSCM1 = “1”), supply of OSCLK (high-speed oscillation clock) is
started when the clock pulse, which is gener ated by dividing the PLLCLK by 2 count reaches 8192 after oscillation is
enabled (ENOSC is set to “1”).
In built-in PLL oscillation mode, both the PA2,PB6/CLKIN pin can be used as general-purpose input ports.
Figure 6-4 shows the circuit configuration in PLL oscillation mode.
32.768kHz
PLL oscillation
circuit
STOP mode
Count: 8192
OSCLK
(High-speed oscillation clock)
Figure 6-4 Circuit Configuration in PLL Oscillation Mode
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ML610Q111/ML610Q112 User’s Manual
PA2,PB6/CLKIN
External clock input
VDD
STOP mode
High-speed oscillation clock
ENOSC (oscillation enable)
Chapter 6 Clock Generation Circuit
6.3.2.2 High-Speed External Clock Input Mode
In high-speed external clock input mode, an external clock is input from the PA2 or PB6/CLKIN pin.
When set as external clock input mode(OSCM0=”1”), supply of OSCLK is started after permitting an oscillation(ENOSC
is set to "1.") and counting an external input clock 128 times.
Figure 6-5 shows the circuit configuration in high-speed external clock input mode.
Count: 128
(OSCLK)
Figure 6-5 Circuit Configuration in High-Speed External Clock Input Mode
Notes:
− If the PA2,PB6/CLKIN pin is left open in high-speed external clock input mode, excessive current can flow. Therefore,
be sure to input a “H” level (V
− The clock that is input must not exceed 8.192 MHz, the guaranteed maximum operating frequency of the system clock
(SYSCLK) of this LSI.
− In external clock input mode, priority is given to PA2 when both PA2 and PB6 are set as a clock input pin
) or a “L” level (VSS) to the CLKIN pin.
DD
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ML610Q111/ML610Q112 User’s Manual
speed oscillation
High-speed clock
speed clock
oscillation enable
ENOSC
Chapter 6 Clock Generation Circuit
6.3.2.3 Operation of High-Speed Clock Generation Circuit
For the high-speed cloc k generation circuit, starting/stopping oscillation can be controlled by the frequency control register
0,1 (FCON0,1).
After selecting high-speed oscillation mode and its frequency in FCON0, the oscillation will be started if the ENOSC bit of
FCON1 is set to "1." After an oscillation start, after waiting the oscillation stabilization period of a high-speed oscillation
clock(OSCLK) in each mode, HSCLK begins to be supplied to a peripheral circuit.
The high-speed clock generation circuit stops oscillation when it enters STOP mode by software. When a STOP mode is
canceled by external interruption and an oscillation restarts, after waiting the oscillation stabilization period of a low-speed
oscillation(LSCLK) and a high-speed oscillation(OSCLK) clock in each mode, HSCLK begins to be supplied to a
peripheral circuit. The oscilla tion stabilization period is the duration of 128 clock pulses in high-speed external cloc k i nput
mode and the duration of 8192 clock pulses in PLL oscillation mode.
Figure 6-6 shows the wavefor ms o f t he high-speed clock generation circuit in bult-in PLL oscillation mode.
High-
High-
waveform
HSCLK
Low-speed clock
oscillation waveform
High-speed oscillation waveform
High-speed oscillation 8192 c ounts
HSCLK waveform
Low-speed oscillation waveform
High-speed
oscillation start
Low-speed oscillation waveform
Low-speed oscillation
32 counts
STOP
mode
Generation of external
interrupt
High-speed oscillation waveform
High-speed oscillation
8192 counts
HSCLK waveform
Program
restart
High-speed
oscillation stop
Figure 6-6 Operation of the Hig h-Speed Clock Generation Circuit in bult-in PLL Oscillation Mode
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ML610Q111/ML610Q112 User’s Manual
→
→
System clock switching
High-speed operation mode
T
= 3ms @bult-in PLL oscillation mode
System clock switching (Low-speed clock→High-speed clock)
Chapter 6 Clock Generation Circuit
6.3.3 Switching of System Clock
The system clock can be switched between high-speed clock (HSCLK) and low-speed clock (LSCLK) by using the
frequency control registers (FCON0, FCON1).
Figure 6-7 shows a flow of system clock switching proce ssi ng ( HSCLK→LSCLK) and Figure 6-8 shows a flow of system
clock switching processing (LSCLK→HSCLK).
System clock switching
SYSCLK←”0”
ENOSC←”0”
Low-speed operation mode
System clock switching (High-speed clock→Low-speed clock)
Stop of high-speed oscillation
(* do not need to stop the oscillation if the high-speed clock is used
for any peripheral)
Figure 6-7 Flow of System Clock Switching Processing (HSCLK
LSCLK)
A high-speed
clock is used?
Yes
ENOSC←”1”
Wait until oscillation
stabilizes (T
SYSCLK←”1”
WAIT
No
It is continuous use about a low-speed clock (LSCLK).
Start of high-speed oscillation
)
WAIT
T
= 1ms @External clock input mode
WAIT
Figure 6-8 Flow of System Clock Switching Processing (LSCLK
Note:
If the system clock is switched from a low-speed clock to a high-speed clock before the high-speed clock (HSCLK) starts
oscillation, the CPU becomes inactive until HSCLK starts clock supply to the peripheral circuits.
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HSCLK)
ML610Q111/ML610Q112 User’s Manual
Chapter 6 Clock Generation Circuit
6.4 Specifying port registers
For enable a clock output function, each related port register needs to be set up. Refer to the Chapter 15, “Port A” and the
Chapter 16 “Port B” for details of each register.
6.4.1 Functioning PB7 (LSCLK) as the low speed clock output
Set PB7MD0 bit (bit7 of PBMOD0 register) to “1” for specifying the low speed clock output as the secondary function of
PB7.
Reg. name PBMOD1 register (Address: 0F25DH)
Bit 7 6 5 4 3 2 1 0
Bit name
Data 0 * * * * * * *
Reg. name PBMOD0 register (Address: 0F25CH)
Bit 7 6 5 4 3 2 1 0
Bit name
Data 1 * * * * * * *
Set PB7C1 bit (bit7 of PBCON1 register) to “1” and set PB7C0 bit(bit7 of PBCON0 register) to “1”, and set PB7DIR
bit(bit7 of PBDIR register) to “0”for specifying the PB7 as CMOS outp ut.
Reg. name PBCON1 register (Address: 0F25BH)
Bit 7 6 5 4 3 2 1 0
Bit name
Data 1 * * * * * * *
Reg. name PBCON0 register (Address: 0F25AH)
Bit 7 6 5 4 3 2 1 0
Bit name
Data 1 * * * * * * *
Reg. name PBDIR register (Address: 0F259H)
Bit 7 6 5 4 3 2 1 0
Bit name
Data 0 * * * * * * *
Data of PB7D bit (bit7 of PBD register) does not affect to the high speed clock output function, so don’t care the data for
the function.
Reg. name PBD register (Address: 0F258H)
Bit 7 6 5 4 3 2 1 0
Bit name
Data ** * * * * * * *
- : Bit does not exist.
* : Bit not related to the high speed clock function
** : Don’t care the data.
PB7MD1 PB6MD1 PB5MD1 PB4MD1 PB3MD1 PB2MD1 PB1MD1 PB0MD1
PB7MD0 PB6MD0 PB5MD0 PB4MD0 PB3MD0 PB2MD0 PB1MD0 PB0MD0
PB7C1 PB6C1 PB5C1 PB4C1 PB3C1 PB2C1 PB1C1 PB0C1
PB7C0 PB6C0 PB5C0 PB4C0 PB3C0 PB2C0 PB1C0 PB0C0
PB7DIR PB6DIR PB5DIR PB4DIR PB3DIR PB2DIR PB1DIR PB0DIR
PB7D PB6D PB5D PB4D PB3D PB2D PB1D PB0D
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Chapter 6 Clock Generation Circuit
6.4.2 Functioning PB0 (OUTCLK) as the High speed clock output
Set PB0MD1 bit (bit0 of PBMOD1 register) to “1” for specifying the low speed clock output as the tertiary function of
PB0.
Reg. name PBMOD1 register (Address: 0F25DH)
Bit 7 6 5 4 3 2 1 0
Bit name
Data * * * * * * * 1
Reg. name PBMOD0 register (Address: 0F25CH)
Bit 7 6 5 4 3 2 1 0
Bit name
Data * * * * * * * 0
Set PB0C1 bit (bit0 of PBCON1 register) to “1” and set PB0C0 bit(bit0 of PBCON0 register) to “1”, and set PB0DIR
bit(bit0 of PBDIR register) to “0”for specifying the PB0 as CMOS output .
Reg. name PBCON1 regi ster (Address: 0F25BH)
Bit 7 6 5 4 3 2 1 0
Bit name
Data * * * * * * * 1
Reg. name PBCON0 register (Address: 0F25AH)
Bit 7 6 5 4 3 2 1 0
Bit name
Data * * * * * * * 1
Reg. name PBDIR register (Address: 0F259H)
Bit 7 6 5 4 3 2 1 0
Bit name
Data * * * * * * * 0
Data of PB0D bit (bit0 of PBD register) does not affect to the high speed clock output function, so don’t care the data for
the function.
Reg. name PBD register (Address: 0F258H)
Bit 7 6 5 4 3 2 1 0
Bit name
Data * * * * * * * **
- : Bit does not exist.
* : Bit not related to the high speed clock function
** : Don’t care the data.
PB7MD1 PB6MD1 PB5MD1 PB4MD1 PB3MD1 PB2MD1 PB1MD1 PB0MD1
PB7MD0 PB6MD0 PB5MD0 PB4MD0 PB3MD0 PB2MD0 PB1MD0 PB0MD0
PB7C1 PB6C1 PB5C1 PB4C1 PB3C1 PB2C1 PB1C1 PB0C1
PB7C0 PB6C0 PB5C0 PB4C0 PB3C0 PB2C0 PB1C0 PB0C0
PB7DIR PB6DIR PB5DIR PB4DIR PB3DIR PB2DIR PB1DIR PB0DIR
PB7D PB6D PB5D PB4D PB3D PB2D PB1D PB0D
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Chapter 6 Clock Generation Circuit
6.4.3 Functioning PA2 (CLKIN) as the External clock input
Set PA2MD1 bit (bit2 of PAMOD1 register) to “1” as the tertiary function of PA2.
Reg. name PAMOD1 register (Address: 0F255H)
Bit 7 6 5 4 3 2 1 0
Bit name
Data
Reg. name PAMOD0 register (Address: 0F254H)
Bit 7 6 5 4 3 2 1 0
Bit name
Data
Set PA2C1 bit (bit2 of PACON1 register) to “0” and set PA2C0 bit(bit2 of PACON0 register) to “0”, and set PA2DIR
bit(bit2 of PADIR register) to “1”for specifying the PA2 as input.
Reg. name PACON1 register (Address: 0F253H)
Bit 7 6 5 4 3 2 1 0
Bit name
Data
Reg. name PACON0 register (Address: 0F252H)
Bit 7 6 5 4 3 2 1 0
Bit name
Data
Reg. name PADIR register (Address: 0F251H)
Bit 7 6 5 4 3 2 1 0
Bit name
Data
Data of PA2D bit (bit2 of PAD register) does not affect to the External clock input function, so don’t care the data for the
function.
Reg. name PAD register (Address: 0F250H)
Bit 7 6 5 4 3 2 1 0
Bit name
Data
- : Bit does not exist.
* : Bit not related to the high speed clock function
** : Don’t care the data.
PA2MD1 PA1MD1 PA0MD1
PA2MD0 PA1MD0 PA0MD0
PA2C1 PA1C1 PA0C1
PA2C0 PA1C0 PA0C0
PA2DIR PA1DIR PA0DIR
PA2D PA1D PA0D
1 * *
0 * *
0 * *
0 * *
1 * *
** * *
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Chapter 7
Time Base Counter
ML610Q111/ML610Q112 User’s Manual
LTBR
R
T2HZ
T4HZ
T8HZ
T16HZ
T32HZ
T64HZ
T128HZ
T256HZ
T512HZ
T1KHZ
T2KHZ
T4KHZ
T8KHZ
T16KHZ
T32KHZ
T1HZ
Chapter 7 Time Base Counter
7 Time Base Counter
7.1 Overview
This LSI includes a low-speed time base counter (LTBC) and a high-speed time base counter (HTBC) that generate base
clocks for peripheral circuits. By using the time base counter, it is possible to generate events periodically.
For input clocks, see Chapter 6, “Clock Generation Circuit”. For inter r up t permission, interrupt request flags, etc.,
described in this chapter, see Chapter 5, “Interrupts”.
7.1.1 Features
• LTBC generates T32KHZ to T1HZ signals by dividing the low-speed clock (LSCLK) frequency.
• HTBC generates the d ivide d cloc k by divid ing the high-speed clock (HSCLK) frequency of HTBCLK (8.192MHz to
512kHz). It is used as the timer’s clock or the PWM’s clocks.
• Capable of generating 128Hz , 32Hz , 16Hz , and 2Hz interrupts.
7.1.2 Configuration
Figure 7-1 and Figure 7-2 show the configurati on of a low-speed time base counter and a high-speed time base counter,
respectively.
LSCLK
(32.768kHz)
RESET
LTBR Write
7-bit Counter
R
8-bit Counter
8
Data bus
LTBR: Low-speed time base counter register
Figure 7-1 Configuration of Low-Speed Time Base Counter (LTBC)
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Chapter 7 Time Base Counter
HSCLK
(8.192MHz)
RESET
Data bus
HTBDR: High-speed time base counter frequency divide register
HTBDR
1/n-Counter
R
HTBCLK
8.192MHz to 512kHz
Figure 7-2 Configuration of High-Speed Time Base Counter
Note:
The frequency of HSCLK is changed by setting of SYSC1 bit and SYSC0 bit in the frequency control register 0 (FCON0).
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value
0F00AH
Low-speed time base counter register
LTBR
R/W 8 00H
frequency divide register
Chapter 7 Time Base Counter
7.2 Description of Registers
7.2.1 List of Registers
Address Name Symbol (Byte) Symbol (Word) R/W Size
0F00BH
High-speed time base counter
HTBDR R/W 8 00H
Initial
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R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
Chapter 7 Time Base Counter
7.2.2 Low-Speed Time Base Counter (LTBR)
Address: 0F00AH
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
LTBR T1HZ T2HZ T4HZ T8HZ T16HZ T32HZ T64HZ T128HZ
LTBR is a special function register (SFR) to read the T128HZ-T1HZ outputs of the low-speed time base counter.
The T128HZ-T1HZ outputs are set to “0” when write operation is performed for LTBR. However, write data is invalid.
Note:
- A TBC interrupt (128Hz interrupt, 32Hz interrupt, 16Hz interrupt, or 2Hz interrupt) may occur depending on the LTBR
write timing. When you reset LTBR, please set it according to the following procedures.
1. Disable interrupt by using DI instruction (reset the master interrupt enable flag (MIE) to “0”).
2. Reset LTBR by writing any value to LTBR.
3. Write “0” to each bit Q128H, Q32H, Q16H and Q2H of the interrupt request flag 6 and 7 (IRQ6 and IRQ7).
4. Enable interrupt by using EI instruction (set MIE to “1”).
- The T128Hz-T1HZ output are the signal that the first half of each signal period becomes "0", and the latter half becomes
"1". For example, the T2HZ output becomes "0" by writing to LTBR and becomes "1" 0.5 seconds later. And it becomes
"0" after one second (one period). The T128HZ, T32HZ, T16HZ and T2HZ outputs which are assigned as interrupt
generate an interrupt by the falling edge ("1" → "0") of the signal.
For the details of the output waveform of T128Hz-T1Hz, see Figure 7-4, “Interrupt Timing and Reset Timing by Writing to
LTBR”.
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R/W
R/W
R/W
R/W
R/W
Initial value
0 0 0 0 0 0 0
0
Divide ratio
Frequency of HTBCLK (*1)
0 0 0
1 × 1/15
546 kHz
0 0 1
0 × 1/14
586 kHz
0 1 0
0 × 1/12
682 kHz
0 1 1
0 × 1/10
820 kHz
1 0 0
0 × 1/8
1024 kHz
1 0 1
0 × 1/6
1366 kHz
1 1 0
0 × 1/4
2048 kHz
1 1 1
0 × 1/2
4096 kHz
Chapter 7 Time Base Counter
7.2.3 High-Speed Time Base Counter Divide Register (HTBDR)
Address: 0F00BH
Access: R/W
Access size: 8 bits
Initial value: 00H
7 6 5 4 3 2 1 0
HTBDR HTD3 HTD2 HTD1 HTD0
HTBDR is a special function register (SFR) to set the divide ratio of the 4-bit, 1/n counter.
[Description of Bits]
• HTD3 to HTD0 (bits 3-0)
The HTD3-HTD0 bits are used to set the frequency divide ratio of the 4-bit, 1/n counter. The frequency divide ratio s
selectable include 1/1 to 1/16.
HTD3 HTD2 HTD1 HTD0
Description
0 0 0 0 × 1/16 (initial value) 512 kHz
0 0 1 1 × 1/13 630 kHz
0 1 0 1 × 1/11 744 kHz
0 1 1 1 × 1/9 910 kHz
1 0 0 1 × 1/7 1170 kHz
1 0 1 1 × 1/5 1638 kHz
1 1 0 1 × 1/3 2730 kHz
1 1 1 1 × 1/1 8192 kHz
*1: Indicates the frequency when the high-speed oscillation clock (HSCLK) is 8192 kHz.
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