Correction of Mic2 and Line2 location. Note on RAM speed.
EXT_BAT max. 3.47 V. Chapter 7.2.2 Riser Card note corrected.
B
Jan. 8th 2014
MLA
Added BIOS features: Force Boot Setup and PC Speaker /Beep.
Minor bugs. Removed 5V t olera nc e for some GPIO’s. J11 and
RAM list updated. Block diagram improved.
0
Jun. 29th 2012
MLA
Preliminary version
Document details
Document revis ion history.
C Jan. 19th 2015 MLA
A Aug. 22nd 2013 MLA
J30 descriptions corrected. 3.3V now 5% tolerance. CPU List
updated. BIOS part added. System Resources tables corrected.
Copyright Notice:
Copyright 2011, KONTRON Technology A/S, ALL RIGHTS RESERVED.
No part of this document may be reproduced or transmitted in any form or by any means, electronically
or mechanically, for any purpose, without the express written permission of KONTRON Technolo g y A/S.
Trademark Acknow ledgemen t:
Brand and product names are trademarks or registered trademarks of their respective owners.
Disclaimer:
KONTRON Technology A/S reserves the right to make changes, without notice, to any product,
including circuits and/or software described or contained in this manual in order to improve design
and/or performance.
Specifications listed in this manual are subject to change without notice. KONTRON Technology
assumes no responsibility or liability for the use of the described product(s), conveys no license or title
under any patent, copyright, or mask work rights to these products, and makes no representations or
warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified. Applications that are described in this manual are for illustration purposes only.
KONTRON Technology A/S makes no representation or warranty that such application will be suitable
for the specified use without further testing or modification.
Life Support Polic y
KONTRON Technology’s PRODUCTS ARE NOT FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL OF THE GENERAL
MANAGER OF KONTRON Technology A/S.
As used herein:
Life support devices or systems are devices or systems which, (a) are intended for surgical implant into
body, or (b) support or sustain life and whose failure to perform, when properly used in accordance with
instructions for use provided in the labelling, can be reasonably expected to result in significant injury to
the user.
A critical component is any component of a life support device or system whose failure to perform can
be reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness.
KTQ77/Flex Users Guide
KTD-N0848-C Page 3
Document details
KONTRON Technology Technical Support & Services
If you have questions about installing or using your KONTRON Technology Product, check this User’s
Manual first – you will find answers to most questions here. To obtain support, please contact your local
Distributor or Field Application Engineer (FAE).
Before Contacting Support: Please be prepared to provide as much information as possible:
• CPU Board
1. Type.
2. Part Number (find PN on label)
3. Serial Number if available (find SN on label)
• Configuration
1. CPU Type, Clock speed
2. DRAM Type and Size.
3. BIOS Revision (Find the Version Info in the BIOS Setup).
4. BIOS Settings different than Default Settings (Refer to the BIOS Setup Section).
• System
1. O/S Make and Version.
2. Driver Version numbers (Graphics, Network, and Audio).
3. Attached Hardware: Harddisks, CD-rom, LCD Panels etc.
Warranty
KONTRON Technology warrants its products to be free from defects in material and workmanship
during the warrant y period. If a pr oduct proves to be defective in material or workmanship during the
warranty period, KONTRON Technology will, at its sole option, repair or replace the product with a
similar product.
Replacement Product or parts may include remanufactured or refurbished parts or components.
The warranty does not cover:
1. Damage, deterioration or malfunction resulting from:
A. Accident, misuse, neg lect, fire, water, lightning, or oth er acts of nature, una uthorized produc t
modification, or failure to follow instructions supplied with the product.
B. Repair or attempted repair by anyone not authorized by KONTRON Technology.
C. Causes external to the product, such as electric power fluctuations or failure.
D. Normal wear and tear.
E. Any other causes which does not relate to a product defect.
2. Removal, installation, and set -up service charges.
Exclusion of damages:
KONTRON TECHNOLOGY LIABILIT Y IS LIMITED TO THE COST OF REPAIR OR REPLACEMENT
OF THE PRODUCT. KONTRON TECHNOLOGY SHALL NOT BE LIABLE FOR:
1. DAMAGE TO OTHER PROPERTY CAUSED BY ANY DEFECTS IN THE PRODUCT,
DAMAGES BASED UPON INCONVE NIENCE, LOS S OF USE OF TH E PRODUCT, LOSS OF
TIME, LOSS OF PROFITS, LOSS OF BUSINESS OPPORTUNITY, LOSS OF GOODWILL,
INTERFERENCE WITH BUSINESS RELATIONSHIPS, OR OTHER COMMERCIAL LOSS,
EVEN IF ADVISED OF THEIR POSSIBILITY OF SUCH DAMAGES.
2. ANY OTHER DAMAGES, WHETHER INCIDENTAL, CONSEQUENTIAL OR OTHERWISE.
3. ANY CLAIM AGAINST THE CUSTOMER BY ANY OTHER PARTY.
10.1 Main .............................................................................................................................................. 67
This manual describes the KTQ77/Flex boar d m ade by KONT RO N T echnolog y A/S. T he board will also
be denoted KTQ77 in this manual.
nd
The KTQ77 board is based on the Q7 7 chipset, support 2
and 4Core processors and also Pentium and Celeron processors. See “Processor Support Table for
more specific details.
Use of this Users Guide implies a basic knowledge of PC-AT hard- and software. This manual is
focused on describing the KTQ77 board’s speci al features and is not inte nded to be a standard PC -AT
textbook.
New users are recom mended to study the short inst allation procedure stated in the f ollowing chapter
before switching-on the power.
Note. LPT and LVDS are optionally for future variants.
All configuration and setup of the CPU board is either done automaticall y or manually by the user via
the BIOS setup menus. Only exception is the “Load Default BIOS Settings” Jumper.
and 3rd generation Intel® i7 -, i5 -, i3 2Core
KTQ77/Flex Users Guide
KTD-N0848-C Page 9
Warning: Turn off PSU (Power Supply Unit) completely (no mains power connected to the
!
!
Warning: When mounting the board to chassis etc. please notice that the board contains
without reasonable care. A damaged component can result in malfunction or no function at all.
Installation procedure
Note: To clear all CMOS settings, including Password protection, move the Clear CMOS jumper in the
Secure CMOS is disabled.
1 Installation procedure
1.1 Installing the board
To get the board running, follow these steps. If the board shipped from KONTRON has already
components like DRAM, CPU and cooler mounted, then relevant steps below, can be skipped.
1. Turn off the PSU (Power Supply Unit)
2. Insert the DRAM(s) (UDIMM 240pin)
Be careful to push it in the slot(s) b efore locking th e tabs. For a list of approved DRAM contact your
Distributor or FAE. See also chapter “System Memory Support”.
3. Install the processor
The CPU is ke yed and will onl y mount in t he CPU sock et in one way. Use finger to open/ close t he
CPU socket. Refer to supported processor overview for details.
4. Cooler Installation
Use heat paste or adhesive pads between CPU and cooler and connect the Fan electrically to the
FAN_CPU connector.
5. Connecting Interfaces
Insert all external cables for hard disk , keyboard etc. A m onitor must be connected i n order to be
able change CMOS settings.
6. Connect and turn on PSU
Connect PSU to the board by the ATX/BTXPWR and the 4-pin ATX+12V connectors.
7. Power Button
The PWRBTN_IN must be toggled to start the Power supply; this is done by shorting pins 16
(PWRBTN_IN) and pin 18 (GND) on the FRONTPNL connector (see Connector description). A
“normally open” switch can be connected via the FRONTPNL connector.
8. BIOS Setup
Enter the BIOS setup by pressing the <Del> key during boot up.
Enter Exit Menu and Load Optimal Defaults.
Refer to the “BIOS Configuration / Setup“ section of this manual for details on BIOS setup .
Clear CMOS position (with or without power) for ~10 sec. This will Load Failsafe Defaults and make sure
9. Mounting the board to chassis
When fixing the Motherb oard on a chassis it is recomm ended using screws with integrated washer and
having diameter of ~7mm.
Note: Do not use washers with teeth, as they can damage the PCB and may cause short circuits.
PSU) or leave the Power Connectors unconnected while configuring the board. Otherwise
components (DRAM, LAN cards etc.) might get damaged. Make sure PSU has 3.3V monitoring
watchdog (standard ATX PSU feature), running the board without 3.3V will damage the board
within minutes.
components on both sides of the PCB which can easily be damaged if board is handled
KTQ77/Flex Users Guide
KTD-N0848-C Page 10
ADVARSEL
When an interface/connector has a VCC (or other power) pin, which is directly connected to a power
Installation procedure
1.2 Requirement according to IEC60950
Users of KTQ77 family boards should take care when designing chassis interface connectors in order to
fulfil the IEC60950 standard:
plane like the VCC plane:
To protect the external power lines of the peripheral devices , the customer has to take care about:
• That the wires have suitable rating to withstand the maximum available power.
• That the enclosure of the peripheral device fulfils the fire protecting requirements of IEC60950.
Lithium Battery precautions:
CAUTION!
Danger of explosion if battery is incorrectly
replaced.
Replace only with same or equivalent type
recommended by manufacturer.
Dispose of used batteries according
to the manufacturer’s instructions.
ADVARSEL!
Lithiumbatteri – Eksplosionsfare ved fejlagtig
håndtering.
Udskiftning må kun ske med batteri
af samme fabrikat og type.
Levér det brugte batteri tilbage til leverandøren.
VARNING
Explosionsfara vid felaktigt batteribyte.
Använd samma batterityp eller en ekvivalent
typ som rekommenderas av apparattillverkaren.
Kassera använt batteri enligt fabrikantens
instruktion.
VORSICHT!
Explosionsgefahr bei unsachgemäßem
Austausch der Batterie.
Ersatz nur durch den selben oder einen vom
Hersteller empfohlenen gleichwertigen Typ.
Entsorgung gebrauchter Ba tterie n nach
Angaben des Herstellers.
Eksplosjonsfare ved feilaktig skifte av batteri.
Benytt samme batteritype eller en tilsvarende
type anbefalt av apparatfabrikanten.
Brukte batterier kasseres i henhold til
fabrikantens
instruksjoner.
VAROITUS
Paristo voi räjähtää, jos se on virheellisesti
asennettu.
Vaihda paristo ainoastaan laltevalmistajan
suosittelemaan
tyyppiin. Hävitä käytetty paristo valmistajan
ohjeiden
mukaisesti.
KTQ77/Flex Users Guide
KTD-N0848-C Page 11
Form factor
KTQ77/Flex: Flex-ATX (190,5 mm by 228,6 mm)
Processor
Support the following Intel® Core™ processors via Socket H2 (LGA1155), ZIF Soc ket
Memory
• 4x DDR3 UDIMM 240pin socket
Chipset
Intel Q77 PCH (Platform Controller Hub)
Security
• Intel® Integrated TPM 1.2 support
Management
• Intel® AMT (Active Management Technology) 8.0
Audio
Audio, 7.1 Channel High Definition Audio Codec using the VIA 1708B codec
System Specification
2 System Specification
2.1 Component main da ta
The table below summarizes the features of the KTQ77/Flex embedded motherboard.
• Intel® Core™ i7, 2nd and 3rd Generation
• Intel® Core™ i5, 2nd and 3rd Generation
• Intel® Core™ i3, 2nd and 3rd Generation
• 1333/1600MHz system bus and 3/6/8MB internal cache.
• Up to 95W (Thermal Guideline)
• PCIe x16 (PEG) Gen3.0
• Support single and dual ranks DDR3 1066/1333/1600MT/s
(PC3-8500/PC3-10600/PC3-12800)
•Support system memory from 1GB and up to 4x 8GB
Note: Less than 4GB displayed in System Properties using 32bit OS
(Shared Video Memory/PCI resources is subtracted)
• ECC not supported
• Intel ® VT-d (Virtualisation Technology for Directed I/O)
• Intel ® TXT (Trusted Execution Technology)
• Intel ® vPRO
• Intel ® AMT (Active Management Technology) version 8.0
• Intel ® AT (Anti-Theft Technology)
• Intel ® HD Audio Technology
• Intel ® RST (Rapid Storage Technology)
• Intel ® RRT (Rapid Recover Technology)
• SATA (Serial ATA) 6Gb/s and 3Gb/s.
• USB 4x rev. 3.0/2.0 + 10x rev. 2.0
• PCIe x4 (in x16 slot) Gen2.0
• ACPI 3.0b compliant
• Triple Display support (Triple Graphic Pipes)
• Blue-ray HD video playbac k
• Line-out
• Line-in
• Surround output: SIDE, LFE, CEN, BACK and FRONT
• Microphone: MIC1 and MIC2
• CDROM in
• SPDIF (electrical Interface only)
• On-board speaker (Electromagnetic Sound Generator like Hycom HY-05LF)
KTQ77/Flex Users Guide
KTD-N0848-C Page 12
Video
Intel ® HD Graphics 4000 or
I/O Control
Via ITE IT8516E Embedded Controller and Winbond W83627DHG I/O Controller
Peripheral
• 2x USB 2.0 ports on I/O area
LAN
• 1x 10/100/1000Mbits/s LAN (ETHER1) using Intel® Lewisville 82579LM Gigabit
Expansion
•2x PCI slot(s) (PCI Local Bus Specification Revision 3.0, 33MHz)
System Specification
Intel ® HD Graphics 3000 or
Intel ® HD Graphics 2500 or
Intel ® HD Graphics 2000 or
Intel ® HD Graphics, depending on actual CPU.
Analogue VGA and digital display ports (2x DP) via the Mobile Intel ® Q77 Chipset.
• VGA (analogue panel)
• 2x DP (DisplayPort), comply with DisplayPort 1.2 specification.
• LVDS panel support (optional) up to 24 bit, 2 pixels/clock and 1920x1200.
• HDMI panel support via DP to HDMI Adapter Converter.
• Second VGA panel support via DP to VGA Adapter Converter
• Second DVI panel support via DP to DVI Adapter Converter
• Triple independent pipes for Mirror and/or independent display support
(both via LPC Bus interface)
interfaces
Support
Capabilities
• 4x USB 3.0 ports on I/O area
• 8x USB 2.0 ports on internal pinrows
• 4x Serial ports (RS232) on internal pinro ws
• 2x Serial ATA-600 IDE interfaces (blue)
• 4x Serial ATA-300 IDE interfaces (black)
• 1x Serial ATA-300 IDE interfaces (white), sh ared w ith mSATA
• RAID 0/1/5/10 support
• mSATA via mSATA connector, shared with SATA (white)
• PS/2 keyboard and mouse ports via pinrow
PHY connected to Q77 supporting AMT 8.0
•2x 10/100/1000Mbits/s LAN (ETHER2/ETHER3)using Intel® Hartwell 82574L PCI
Express controllers
• PXE Netboot supported.
• Wake On LAN (WOL) supported
• PCI-Express slots:
o 1 slot PCIe x16 Gen3.0
o 1 slot PCIe x4 (in a x16 slot) Gen2 (EFT samples support only PCIe x1)
o 1 slot miniPCI-Express
• SMBus, compatib le with A CCE S BUS and I2C BU S, (via Feature connector)
• SPI bus routed to SPI connector
• DDC Bus routed to DP connector when DP Adapters are connected
• 5 x digital input, (via Feature connector)
• 13 x GPIOs (General Purpose I/Os), (via Feature connector)
• DAC, ADC, PWM and TIMER (Multiplexed), (via Feature connector)
• WAKE UP / Interrupt Inputs (Multiplexed), (via Feature connec tor )
• 3 Wire Bus for GPIO Expansion (up to 152 GPIOs), (via Feature connector)
• 8 bit Timer output, (via Feature connector)
KTQ77/Flex Users Guide
KTD-N0848-C Page 13
Hardware
• Smart Fan control system, support Thermal® and Speed® cruise for FAN_CPU
Power
ATX/BTX (w. ATX+12V) PSU for full PCI/PCIe load.
Battery
BIOS
• Kontron Technology / AMI BIOS (EFI c ore ver sio n)
• System Powergood Signal, (via Feature connector)
Exchangeable 3.0V Lithium battery for on-board Real Time Clock and CMOS RAM.
Manufacturer Panasonic / Part-number CR-2032L/BN, CR2032N/BN or CR-2032L/BE.
Approximate 5 years retention.
Current draw is 5,7µA when PSU is disconnected and 0 µA in S0 – S5.
CAUTION: Danger of explosion if the battery is incorrectly replaced. Replace
only with the same or equivalent type recommended by the manufacturer.
Dispose of used batteries according to th e manufacturer’s instructions.
• Support for ACPI 3.0 ( Advanced Configuration and Power Interface), Plug & Play
o Suspend (S1 mode)
o Suspend To Ram (S3 mode)
o Suspend To Disk (S4 mode)
Only Japanese brand Solid capacitors rated for 100 ºC used on board
System Specification
Conditions
Operating:
0°C – 60°C operating temperature (forced cooling). It is the customer’s
responsibility to provide sufficient airflow around each of the components to keep
them within allowed temperature range.
10% - 90% relative humidity (non-condensing)
Storage:
-20°C – 70°C; lower limit of storage temperature is defined by specification
restriction of on-board CR2032 battery. Board with battery has been verified for
storage temperature down to -40°C by Kontron.
All Peripheral interfaces intended for connection to external equipment are ESD/
EMI protected.
EN 61000-4-2:2000 ESD Immunity
EN55022:1998 class B Generic Emission Standard.
Safety:
IEC 60950-1: 2005, 2nd Edition
UL 60950-1
CSA C22.2 No. 60950-1
Product Category: Information Technology Equipment Including Electrical
Business Equipment
Product Category CCN: NWGQ2, NWGQ8
File number: E194252
Theoretical MTBF:
216227 / 100903 hours @ 40ºC / 60ºC for the KTQ77/Flex
Restriction of Hazardous Substances (RoHS):
All boards in the KTQ77 family are RoHS compliant.
Capacitor utilization:
No Tantalum capacitors on board
KTQ77/Flex Users Guide
KTD-N0848-C Page 15
System Specification
2.2 System overview
The block diagram below shows the architecture and main components of the KTQ77. The key
component on the board is the Intel
®
Q77 (Panther Point) Express Chipset.
More detailed block diagram on next page.
KTQ77/Flex Users Guide
KTD-N0848-C Page 16
System Specification
Dual Channel DDR3
4 x DIMM
PCIe x16 Graphics
Ivy Bridge or
2x DisplayPort
VGA
PCIe x4 Slot
Intel 82574L 10/100/GBe
14x USB
6x SATA
SDVO to LVDS (option)
VIA Codec
SPI
SPI
TPM
Intel Lewisville PHY
Intel 82574L 10/100/GBe
mSATA
PCIe Mini Card
IO controller
IO controller
PCI slot
PCI slot
COM3/4
COM1/2
FAN CPU/SYS
FEATURE
1067/1333/1600
(4x Ge n 3.0 / 2.0)
ITE8516
Sandy Bridge
LGA1155
Q77 PCH
W83627DHG-P(T)
KTQ77/Flex Users Guide
KTD-N0848-C Page 17
Processor
Brand
Clock
[GHz]
Turbo
[GHz]
Cores /
Threads
Bus
[MHz]
Cache
[MB]
CPU
Number
sSpec
no.
TG
[W/ºC]
Note
3.5
3.9
4 / 8
1333/1600
8
3770K
SR0PL
E1
77/67.4
HDG4000
I7 3rd Gen.
3.4
3.9
4 / 8
1333/1600
8
3770
SR0PK
E1
77/67.4
HDG4000
(Ivy Bridge)
3.1
3.9
4 / 8
1333/1600
8
3770S
SR0PN
E1
65/69.1
HDG4000
2.5
3.7
4 / 8
1333/1600
8
3770T
SR0PQ
E1
45/69.8
HDG4000
3.5
3.9
4 / 8
1066/1333
8
2700K
SR0DG
D2
95/72.6
HDG3000
I7 2nd Gen.
3.4
3.8
4 / 8
1066/1333
8
2600
SR00B
D2
95/72.6
HDG2000
(Sandy Bridge)
3.4
3.8
4 / 8
1066/1333
8
2600K
SR00C
D2
95/72.6
HDG3000
2.8
3.8
4 / 8
1066/1333
8
2600S
SR00E
D2
65/69.1
HDG2000
3.4
3.8
4 / 4
1333/1600
6
3570
SR0T7
N0
77/67.4
HDG2500
I5 3rd Gen.
3.4
3.8
4 / 4
1333/1600
6
3570K
SR0PM
E1
77/67.4
HDG4000
(Ivy Bridge)
3.3
3.7
4 / 4
1333/1600
6
3550
SR0P0
E1
77/67.4
HDG2500
3.2
3.6
4 / 4
1333/1600
6
3470
SR0T8
N0
77/67.4
HDG2500
3.1
3.8
4 / 4
1333/1600
6
3570S
SR0T9
N0
65/69.1
HDG2500
3.1
3.5
4 / 4
1333/1600
6
3450
SR0PF
E1
77/67.4
HDG2500
3.1
3.3
4 / 4
1333/1600
6
3350P
SR0WS
E1
69/67.4 -
3.0
3.7
4 / 4
1333/1600
6
3550S
SR0P3
E1
65/69.1
HDG2500
3.0
3.2
4 / 4
1333/1600
6
3330
SR0RQ
E1
77/67.4
HDG2500
2.9
3.6
4 / 4
1333/1600
6
3475S
SR0PP
E1
65/69.1
HDG4000
2.9
3.6
4 / 4
1333/1600
6
3470S
SR0TA
N0
65/69.1
HDG2500
2.9
3.6
2 / 4
1333/1600
3
3470T
SR0RJ
L1
35/65.0
HDG2500 *
2.8
3.5
4 / 4
1333/1600
6
3450S
SR0P2
E1
65/69.1
HDG2500
2.7
3.5
4 / 4
1333/1600
6
3330S
SR0RR
E1
65/
HDG2500
2.3
3.2
4 / 4
1333/1600
6
3570T
SR0P1
E1
45/69.8
HDG2500
3.3
3.7
4 / 4
1066/1333
6
2550K
SR0QH
D2
95/72.6
-
I5 2nd Gen.
3.3
3.7
4 / 4
1066/1333
6
2500K
SR008
D2
95/72.6
HDG3000
(Sandy Bridge)
3.3
3.7
4 / 4
1066/1333
6
2500
SR00T
D2
95/72.6
HDG2000
3.2
3.5
4 / 4
1066/1333
6
2450P
SR0G1
D2
95/72.6 -
3.1
3.4
4 / 4
1066/1333
6
2380P
SR0G2
D2
95/72.6
-
3.1
3.4
4 / 4
1066/1333
6
2400
SR00Q
D2
95/72.6
HDG2000
3.0
3.3
4 / 4
1066/1333
6
2320
SR02L
D2
95/72.6
HDG2000
2.9
3.2
4 / 4
1066/1333
6
2310
SR02K
D2
95/72.6
HDG2000
2.8
3.1
4 / 4
1066/1333
6
2300
SR00D
D2
95/72.6
HDG2000
2.7
3.7
4 / 4
1066/1333
6
2500S
SR009
D2
65/69.1
HDG2000
2.7
3.5
2 / 4
1066/1333
3
2390T
SR065
Q0
35/65.0
HDG2000
2.5
3.3
4 / 4
1066/1333
6
2405S
SR0BB
D2
65/69.1
HDG3000
2.5
3.3
4 / 4
1066/1333
6
2400S
SR00S
D2
65/69.1
HDG2000
2.3
3.3
4 / 4
1066/1333
6
2500T
SR00A
D2
45/69.8
HDG2000
System Specification
2.3 Processor Suppor t Table
The KTQ77 is designed to support the following LGA1155 processors (up to 95W power consumption):
nd
and 3rd generation Intel® Core™ i7 processor
2
nd
2
and 3rd generation Intel® Core™ i5 processor
nd
2
and 3rd generation Intel® Core™ i3 processor
Pentium and Celeron
In the following list you will find all CPU’s suppor t ed b y the chipset in ac cor din g to Inte l.
Embedded CPU’s are indic ated bygreen text, succ essfully tested CPU’s are indicated b y highlighted
text, successfully tested embedded CPU’s are indicated by green and highlighted text and failed
CPU’s are indicated by red text.
Some processors in the l ist are distributed from Kontron, thos e CPU’s are marked by an * (asterisk ).
However please notice that this marking is only guide line and maybe not fully updated.
Step
KTQ77/Flex Users Guide
KTD-N0848-C Page 18
Processor
Brand
Clock
[GHz]
Turbo
[GHz]
Cores /
Threads
Bus
[MHz]
Cache
[MB]
CPU
Number
sSpec
no.
TG
[W/ºC]
Note
3.5 - 2 / 4
1333/1600
3
3250
SR0YX
P0
55/65.3
HDG2500
I3 3rd Gen.
3.4 - 2 / 4
1333/1600
3
3245
SR0YL
L1
55/65.3
HDG4000
(Ivy Bridge)
3.4 - 2 / 4
1333/1600
3
3240
SR0RH
L1
55/65.3
HDG2500
3.3 - 2 / 4
1333/1600
3
3225
SR0RF
L1
55/65.3
HDG4000
(No vPRO)
3.3 - 2 / 4
1333/1600
3
3220
SR0RG
L1
55/65.3
HDG2500
3.2 - 2 / 4
1333/1600
3
3210
SR0YY
P0
55/65.3
HDG2500
3.0 - 2 / 4
1333/1600
3
3250T
SR0YW
P0
35/65.0
HDG2500
2.9 - 2 / 4
1333/1600
3
3240T
SR0RK
L1
35/65.0
HDG2500
2.8 - 2 / 4
1333/1600
3
3220T
SR0RE
L1
35/65.3
HDG2500
3.4 - 2 / 4
1066/1333
3
2130
SR05W
Q0
65/69.1
HDG2000
I3 2nd Gen.
3.3 - 2 / 4
1066/1333
3
2125
SR0AY
J1
65/69.1
HDG3000
(Sandy Bridge)
3.3 - 2 / 4
1066/1333
3
2120
SR05Y
Q0
65/69.1
HDG2000
3.1 - 2 / 4
1066/1333
3
2105
SR0BA
J1
65/69.1
HDG3000
(No vPRO)
3.1 - 2 / 4
1066/1333
3
2100
SR05C
Q0
65/69.1
HDG2000
3.1 - 2 / 4
1066/1333
3
2102
SR05D
Q0
65/69.1
HDG2000
2.6 - 2 / 4
1066/1333
3
2120T
SR060
Q0
35/65.0
HDG2000
2.5 - 2 / 4
1066/1333
3
2100T
SR05Z
Q0
35/65.0
HDG2000
3.1 - 2 / 2
1066/1333
3
G870
SR057
Q0
65/69.1
HDG
3.0 - 2 / 2
1066/1333
3
G860
SR058
Q0
65/69.1
HDG
Pentium
2.9 - 2 / 2
1066/1333
3
G850
SR05Q
Q0
65/69.1
HDG
2.9 - 2 / 2
1066
3
G645
SR0RS
Q0
65/69.1
HDG
2.8 - 2 / 2
1066/1333
3
G840
SR05P
Q0
65/69.1
HDG
2.8 - 2 / 2
1066
3
G640
SR059
Q0
65/69.1
HDG
2.7 - 2 / 2
1066
3
G632
SR05N
Q0
65/69.1
HDG
2.7 - 2 / 2
1066
3
G630
SR05S
Q0
65/69.1
HDG
2.8 - 2 / 2
1066/1333
3
G860T
SR0MF
Q0
35/65.0
HDG
2.6 - 2 / 2
1066
3
G620
SR05R
Q0
65/69.1
HDG
2.6 - 2 / 2
1066
3
G622
- - 65/69.1
HDG
2.5 - 2 / 2
1066
3
G645T
SR0S0
Q0
35/65.0
HDG
2.4 - 2 / 2
1066
3
G640T
SR066
Q0
35/65.0
HDG
2.2 - 2 / 2
1066
3
G620T
SR05T
Q0
35/65.0
HDG
2.3 - 2 / 2
1066
3
G630T
SR05U
Q0
35/65.0
HDG
2.7 - 2 / 2
1333
2
G1620
SR10L
P0
55
HDG *
2.7 - 2 / 2
1066
2
G555
SR0RZ
Q0
65/69.1
HDG
2.6 - 2 / 2
1333
2
G1610
SR10K
P0
55
HDG *
2.6 - 2 / 2
1066
2
G550
SR061
Q0
65/69.1
HDG
2.5 - 2 / 2
1066
2
G540
SR05J
Q0
65/69.1
HDG
Celeron
2.4 - 2 / 2
1066
2
G530
SR05H
Q0
65/69.1
HDG
2.3 - 2 / 2
1333
2
G1610T
SR10M
P0
35/
HDG *
2.2 - 2 / 2
1066
2
G550T
SR05V
Q0
35/65.0
HDG
2.1 - 2 / 2
1066
2
G540T
SR05L
Q0
35/65.0
HDG
2.0 - 2 / 2
1066
2
G530T
SR05K
Q0
35/65.0
HDG
2.0 - 1 / 2
1066/1333
1.5
G470
SR0S7
Q0
35/65.5
HDG
1.8 - 1 / 2
1066
1.5
G460
SR0GR
Q0
35/65.5
HDG
1.6 - 1 / 1
1066
1
G440
SR0BY
Q0
35/65.5
HDG
System Specification
Step
(*) ECC not supported on KTQ77.
Not all CPUs, even of s ame type, support a ll functions ex . i7 3770K, i7 2600K, i5 3570K, 3450, 3450S,
3350P, 3330S, 3330 and i5 2500K, 2300, 2310, 232 0, 2380P, 2450P , 2550K doesn’t sup port vPro while
all other i7 and i5 does.
Intel® Turbo Boost T echnology 2.0 is sup ported by i5 and i7, as indicated in above list of processors,
and is enabling overclocking of all cores, when operated within the limits of thermal design power,
temperature and current.
KTQ77/Flex Users Guide
KTD-N0848-C Page 19
!
Warning: Make sure sufficient airflow is always present around the components located below
or is blocking the airflow around these components, causing reduced lifetime.
It is recommended to use a cooler like the Kontron
Components below the cooler
Note: The temperature of the air blo wn out of the cooler must be les s than 7 0ºC maximum in order not
System Specification
Sufficient cooling must be applied to the CPU in order to remove the effect as listed in above table
(Thermal Guideline). The sufficient cooling is also depending on the maximum (worst-case) ambient
operating temperature and the actual load of processor.
PN 1046-6305 “KTQ77 Cooler”.
The design of this cooler makes sure airflow is
always present around th e components below the
cooler. Even if F an is s et to be of f, it is s till runn ing
a minimum RPM (Rotation Per Minute).
the cooler. Different coolers are available on the market and some is not generating any airflow
Air sucked in to the cooler
Air blown out of the cooler
to overheat components near the C PU. Ho wever m ost CPU’s re quires m ax imum 67.4ºC , so in order n ot
to violate the CPU specification the temperature of the air should be maximum ~65ºC.
KTQ77/Flex Users Guide
KTD-N0848-C Page 20
DIMM Type
Module
Memory
[Mill/s]
Processor
[MHz]
Resulting
[MHz]
Peak transfer
[MB/s]
DDR3 1066
PC3-8500
1066
1066 / 1333
533
8533
DDR3 1333
PC3-10600
1333
1333/1600
666
10666
DDR3 1600
PC3-12800
1600
1333
666
10666
DDR3 1600
PC3-12800
1600
1600
800
12800
DDR3 (SLOT B1)
System Specification
2.4 System Memor y support
The KTQ77/FLEX has four DDR3 UDIMM sockets. The sockets support the following memory features:
From 1GB and up to 4x 8G B.
Note: Less than 4GB displayed in System Properties using 32bit OS
(Shared Video Memory/PCI resources is subtracted)
• SPD timings supported
• ECC not supported
The installed DDR3 DIMM should sup port Ser ial Presenc e Detect ( SPD) da ta str ucture. This allows t he
BIOS to configure the memory controller for optimal performance. If non-SPD memory is used, the
BIOS will attempt to configure the memory settings, but performance and reliability may be impacted.
Memory Operating Frequencies
Regardless of the DIMM type used, the memory frequency will either be equal to or less than the
processor system bus frequency. For example, if DDR3 1600 m emor y is used with a 1333 MHz s ys te m
bus frequency processor, the m emory clock will op erate at 666 MHz. The table below list s the resulting
operating memory frequencies based on the combination of DIMMs and processors.
nd
Generation Core i5 support 1066/1333 MT/s
Notes: Kontron offers the following memory modules:
Please notice that not all speeds are supported by all CPU’s.
In order to support Intel ® AMT (Management Engine) SLOT A0 must always be populated. In case of
using more than a single DIMM it is recommended to populate A0 + B0 first.
name
Data
transfers
system bus
frequency
memory clock
frequency
DDR3 (SLOT B0)
DDR3 (SLOT A1)
DDR3 (SLOT A0)
rate
KTQ77/Flex Users Guide
KTD-N0848-C Page 21
System Specification
2.5 KTQ77 Graphics Subsystem
The KTQ77 equipped wit h Intel 3rd generatio n Core i3, i5 or i7 processor, supports Intel ® HD Graphics
2500/4000 depending on specific processor and KTQ77 equipped with Intel 2
processor, s upports Intel ® HD Graphics 2000 (only i5-2400 supported). In the following o nly GFX for
rd
generation core processors are described.
3
All KTQ77 versions support analogue VG A and digital displ ay ports (2x DP) via the Intel ® Q77 Chipset.
Optionally LVDS support.
The DP interface supp orts the Displa yPort 1.2 specificatio n. The PCH supports High-bandwidth Digital
Content Protection for high definition content playback over di gital interfaces. T he PCH also integrates
audio codecs for audio support over DP interfaces.
Up to three displays (any three display outputs) can be activated at the same time and be used to
implement dual independent display support and/or mirror display support. PCIe and PCI graphics cards
can be used to replace on-board graphics or in combination with on-board graphi c s .
nd
generation Core i5
2.5.1 Intel® HD Graphics 4000/2500
Features of the Intel HD Graphics 4000/2500 build into the i3, i5 and i7 processors , includes:
•High quality graphics engine supporting
o DirectX11 and OpenGL 4.0 compliant
o Shader Model 5.0 support
o Intel ® Clear Video HD Technology
o Intel ® Quick Sync Video Technology
o Intel ® Flexible Display Interface (Intel ® FDI)
o Core frequency of 650 - 1150 (Turbo) MHz
o Memory Bandwidth up to 21.3 GB/s
o 6 3D Execution Units (HD Graphics 2500)
o 16 3D Execution Units(HD Graphics 4000)
o 1.62 GP/s and 2.7 GP/S pixel rate (DP outputs)
o Hardware Acceleration CVT HD and QSV
o Dynamic Video Memory Technology (DVMT) support up to 1720 MB
•LVDS panel Support (optional), 18/24 bit colours in up to WUXGA (1920x1200) @60 Hz and
SPWG (VESA) colour coding. OpenLDI (JEIDA) colour c oding is 18 bit with or without D it heri ng.
•DP0 and DP1
o 24/30 bit colours in WQXGA (2560x1600 pixels) and HDCP.
o DisplayPort standard 1.2
Use of DP Adapter Converters can implement HDMI
support or second VGA or DVI panel support.
The HDMI interface supports the HDMI 1.4a specification
and includes audio codecs. However lim itat i ons to the
resolution apply:
2048x1536 VGA
1920x1200 HDMI and DVI
DP to VGA DP to HDMI DP to DVI-D
PN 1045-5779 PN 1045-5781 PN 1045-5780
KTQ77/Flex Users Guide
KTD-N0848-C Page 22
Supply
Min
Max
Note
ATX supplies
KTQ77
PSU
Gnd
Current
Tektronix DPO 2024
System Specification
2.6 Power Consumption
In order to ensure safe operation of the board, the ATX12V power supply must monitor the supply
voltage and shut do wn if the supplies are out of ran ge – refer to the hardware manual for the actual
power supply specification. The KTQ77 board is powered through the ATX/BTX connector and
ATX+12V connector. Both connectors must be used in according to the ATX12V PSU standard.
The requirements to the supply voltages are as follows:
VCC3.3 3.135V 3.465V
Vcc 4.75V 5.25V
+12V 11.4V 12.6V
–12V –13.2V –10.8V
-5V -5,50V -4.5V Not required for the KTQ77 board
5VSB 4.75V 5.25V
More detailed Static Power Consumption
On the following pages the power consumption of the KTQ77 Board is measured under:
1- DOS, idle, mean
2- Windows7, Running 3DMARK 2005 & BiT 6, mean
3- S1, mean
4- S3, mean
5- S4, mean
The following items were used in the test setup:
Low Power Setup
Standard system conf iguration equipped with PCI card, Internal graphics , 2x SATA disks, Intel i3
CPU, 2x DIMM 2GB Modules, DP Monitor, Keyboard & Mous e. 1x 1-4G B USB Flash Stick , 1x 1GB
LAN
High Power Setup
Standard system configuration equipped with PCI card, PCIex4, PCIex16, miniPCIe WLAN, 4x
SATA disks, Intel i7 CPU, 4x DIMM 2GB Modules, DP M onitor, Keyboar d & Mouse, 3x 1-4GB US B
Flash Stick, 3x 1GB LAN.
Note: The Power consumption of Display and HD are not included.
Should be ±5% for compliance with the ATX specification
Should be ±5% for compliance with the ATX specification.
Should be minimum 5.00V measured at USB connectors
in order to meet the requirements of USB standard.
Should be ±5% for compliance with the ATX specification
Should be ±10% for compliance with the ATX specification
Should be ±5% for compliance with the ATX specification
Probe
KTQ77/Flex Users Guide
KTD-N0848-C Page 23
DOS Idle, Mean, No external load
Supply
Current draw
Power consumption
+12V
0,37A
3,96W
+12V P4
0,80A
9,60W
+5V
1,22A
6,10W
+3V3
0,25A
0,83W
-12V
< 100mA
5VSB
< 10 mA
Total
20,49W
Windows 7, mean
3DMARK2005 (first scene) & BiT 6
Supply
Current draw
Power consumption
+12V
0,37A
4,44W
+12V P4
1,62A
19,44W
+5V
2,15A
10,75W
+3V3
0,39A
1,29W
-12V
< 100mA
5VSB
< 10 mA
Total
35,92W
S1 Mode, Mean, No external load
Supply
Current draw
Power consumption
+12V
0,30A
3,60W
+12V P4
0,37A
4,44W
+5V
0,85A
4,25W
+3V3
0,28A
0,92W
-12V
< 100mA
5VSB
< 100mA
Total
13,21W
S3 Mode, Mean, No external load
Supply
Current draw
Power consumption
+12V
0
0W
+12V P4
0
0W
+5V
0
0W
+3V3
0
0W
-12V
0
0W
5VSB
< 100mA
<0.5W
Total
<0.5W
S4 Mode, Mean, No external load
Supply
Current draw
Power consumption
+12V
0
0W
+12V P4
0
0W
+5V
0
0W
+3V3
0
0W
-12V
0
0W
5VSB
< 100mA
<0.5W
Total
<0.5W
System Specification
Low Power Setup results:
KTQ77/Flex Users Guide
KTD-N0848-C Page 24
DOS Idle, Mean, No external load
Supply
Current draw
Power consumption
+12V
1,72A
20,64W
+12V P4
0,98A
11,76W
+5V
1,60A
8,00W
+3V3
1,38A
4,55W
-12V
< 500mA
5VSB
< 50 mA
Total
44,55W
Windows 7, mean
3DMARK2005 (first scene) & BiT 6
Supply
Current draw
Power consumption
+12V
1,70A
20,40W
+12V P4
3,60A
43,20W
+5V
2,60A
13,00W
+3V3
1,86A
6,138W
-12V
< 100mA
5VSB
< 10 mA
Total
82,74W
S1 Mode, Mean, No external load
Supply
Current draw
Power consumption
+12V
1,40A
16,80W
+12V P4
0,52A
6,24W
+5V
1,10A
5,50W
+3V3
1,26A
4,16W
-12V
< 100mA
5VSB
< 10 mA
Total
32,70W
S3 Mode, Mean, No external load
Supply
Current draw
Power consumption
+12V
0
0W
+12V P4
0
0W
+5V
0
0W
+3V3
0
0W
-12V
0
0W
5VSB
< 100mA
<0.5W
Total
<0.5W
S4 Mode, Mean, No external load
Supply
Current draw
Power consumption
+12V
0
0W
+12V P4
0
0W
+5V
0
0W
+3V3
0
0W
-12V
0
0W
5VSB
< 100mA
<0.5W
Total
<0.5W
System Specification
High Power Setup results:
KTQ77/Flex Users Guide
KTD-N0848-C Page 25
Connector Location
Feature
COM1
VGA
PCIex16
ATX/ BTXPWR
Audio
USB12
USB13
Frontpanel
CDROM
Audioheader
COM3
COM2
FAN_SYS
FAN_CPU
ETH1
USB4
COM4
PCI0
ETH2
ETH3
ClrCMOS
Sata5 - Sata0 - Sata1
(see note)
LVDS
(optionally)
PCIex4
SPI recover
SPI
USB1
DP0
USB3
DP1
Notes: Sata0/Sata1support up to 6GB/s and Sata2/Sata3/Sata4/Sata5 support up to 3GB/S.
(*) The LPT connector and the XDP connectors are not mounted in volume production.
XDP-PCH (*)
3.2 KTQ77/Flex - backside
KTQ77/Flex Users Guide
KTD-N0848-C Page 27
Connector Definitions
4 Connector Definitions
The following sections provide pin definitions and detailed description of all on-board connectors.
The connector definitions follow the following notation:
Column
name
Pin Shows the pin-numbers in the connector. The graphical layout of the connector definition
Signal The mnemonic name of the signal at the current pin. The notation “XX#” states that the
Type AI: Analogue Input.
Ioh: Typical current in mA flowing out of an output pin through a grounded load, while the
Pull U/D On-board pull-up or pull-down resistors on input pins or open-collector output pins.
Note Special remarks concerning the signal.
The abbreviation TBD is used for specifications which are not available yet or which are not sufficiently
specified by the component vendors.
Description
tables is made similar to the physical connectors.
signal “XX” is active low.
AO: Analogue Output.
I: Input, TTL compatible if nothing else stated.
IO: Input / Output. TTL compatible if nothing else stated.
IOT: Bi-directional tristate IO pin.
IS: Schmitt-trigger input, TTL compatible.
IOC: Input / open-collector Output, TTL compatible.
IOD: Input / Output, CMOS level Schmitt-triggered. (Open drain output)
NC: Pin not connected.
O: Output, TTL compatible.
OC: Output, open-collector or open-drain, TTL compatible.
OT: Output with tri-state capability, TTL compatible.
LVDS: Low Voltage Differential Signa l.
PWR: Power supply or ground reference pins.
output voltage is > 2.4 V DC (if nothing else stated).
Iol: Typical current in mA flowing into an output pin from a VCC connected load, while the
output voltage is < 0.4 V DC (if nothing else stated).
KTQ77/Flex Users Guide
KTD-N0848-C Page 28
Pull
U/D
Pull
U/D
6
GND
PWR - -
/75R - A0
RED
1 11
NC - - -
7
GND
PWR - -
/75R - A0
GREEN
2 12
DDCDAT
IO
TBD
2K2
8
GND
PWR - -
/75R - A0
BLUE
3 13
HSYNC
O
TBD 9
5V
PWR - - 1 - - - NC
4 14
VSYNC
O
TBD
10 GND
PWR - - - -
PWR
GND
5 15
DDCCLK
IO
TBD
2K2
Pin
Signal
Description
1
RED
Analogue output carrying the red colour values. (75 Ohm cable impedance).
2
GREEN
Analogue output carrying the green colour values. (75 Ohm cable impedanc e).
3
BLUE
Analogue output carrying the blue colour values. (75 Ohm cable impedance).
4
NC
No Connection
5-8
GND
9 5V
This 5V supply is fused by a 1.1A resettable fuse.
10
GND
11
NC
No Connection
12
DDCDAT
Display Data Channel Data. Used as data signal to/from monitors with DDC interface.
13
HSYNC
CRT horizontal synchronization output.
14
VSYNC
CRT vertical synchronization output.
15
DDCCLK
Display Data Channel Clock. Used as clock signal to/from monitors with DDC interface.
IO-Area Connectors
5 IO-Area Connectors
5.1 Display connectors (IO Area)
The KTQ77 family provides one on-board Analogue VGA port, two on-board DP’s (DisplayPort) and
optionally one on-board LVDS panel interf ac e. Two graphic pipes are sup porte d; meaning that up to two
independent displays can be implemented using any two of the above mentioned graphic ports.
.
5.1.1 Analogue VGA (VGA)
Note
Note 1: The +5V supply is fused by a 1.1A resettable fuse
Signal Description - VGA Connector:
Ioh/Iol Type Signal PIN Signal Type Ioh/Iol
Note
KTQ77/Flex Users Guide
KTD-N0848-C Page 29
19 17 15 13 11 9 7 5 3 1
20 18 16 14 12 10 8 6 4 2
Pin
Signal
Description
Type
Note
1
Lane 0 (p)
LVDS
2 GND
PWR
3 Lane 0 (n)
LVDS
4 Lane 1 (p)
LVDS
5 GND
PWR
6 Lane 1 (n)
LVDS
7 Lane 2 (p)
LVDS
8 GND
PWR
9 Lane 2 (n)
LVDS
10
Lane 3 (p)
LVDS
11
GND
PWR
12
Lane 3 (n)
LVDS
Internally pull down (1Mohm ) .
DDC channel on pin 15/17, If HDMI adapter used (3.3V)
14
Config2
(Not used)
O
Internally connected to GND
Aux Channel (+)
or DDC Clk
AUX (+) channel used by DP
DDC Clk used by HDMI
16
GND
PWR
Aux Channel (-)
or DDC Data
AUX (-) channel used by DP
DDC Data used by HDMI
18
Hot Plug
I Internally pull down (100Kohm).
19
Return
PWR
Same as GND
Fused by 1.5A resetable PTC fuse, common for DP0 and
DP1
IO-Area Connectors
5.1.2 DP Connectors (DP0/DP1)
The DP (DisplayPort) connectors are based on standard DP type Foxconn 3VD51203-H7JJ-7H or
similar.
13 Config1
15 Aux Ch (p)
17 Aux Ch (n)
20 3.3V PWR
Aux or DDC
selection
I
Aux channel on pin 15/17 selected as default (when NC)
KTQ77/Flex Users Guide
KTD-N0848-C Page 30
Signal
PIN
Type
Ioh/Iol
Note
MDI0+
MDI0-
MDI1+
MDI2+
MDI2-
MDI1-
MDI3+
MDI3-
8 7 6 5 4 3 2 1
IO-Area Connectors
5.2 Ethernet Connect ors (IO Area)
The KTQ77 boards supports three channels of 1 0/10 0/ 1000 Mb Et her ne t , one (ETH1) is b as ed on Intel®
Lewisville 82579LM Gigabit PHY with AMT 8.0 support and the two other controllers (ETHER2 &
ETHER3) are based on Intel® Hartwell 82574L PCI Express controller.
In order to achieve the specified performance of the Ethernet port, minimum Category 5 twisted pair
cables must be used with 10/100MB and minimum Category 5E, 6 or 6E with 1Gb LAN networks.
The signals for the Ethernet ports are as follows:
Signal Description
MDI[0]+ / MDI[0]- In MDI mode, this is the first pair in 1000Base-T, i.e. the BI_DA+/- pair, and is
the transmit pair in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is the receive
pair in 10Base-T and 100Base-TX.
MDI[1]+ / MDI[1]- In MDI mode, this is the second pair in 1000Base-T, i.e. the BI_DB+/- pair, and
is the receive pair in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is the transmit
pair in 10Base-T and 100Base-TX.
MDI[2]+ / MDI[2]-
In MDI mode, this is the third pair in 1000Base-T, i.e. the BI_DC+/- pair.
In MDI crossover mode, this pair acts as the BI_DD+/- pair.
MDI[3]+ / MDI[3]-
Note: MDI = Media Dependent Interface.
Ethernet connector 1 (ETH1) is mounted together with USB Ports 4 and 5.
Ethernet connector 2 (ETH2) is mounted together with and above Ethernet connector 3 (ETH3).
The pinout of the RJ45 connectors is as follows:
In MDI mode, this is the fourth pair in 1000Base-T, i.e. the BI_DD+/- pair.
In MDI crossover mode, this pair acts as the BI_DC+/- pair.
KTQ77/Flex Users Guide
KTD-N0848-C Page 31
IO-Area Connectors
5.3 USB Connectors (IO Area)
The KTQ77 board contain s two EHCI (Enhanced Host Control ler Interface) and one X HCI (Extensible
Host Controller Interface) . The two EHCI controllers, EHCI1 and EHCI2, supports up to fourteen USB
2.0 ports allowing data transfers up to 480Mb/s. The XHCI controller supports four USB 3.0 ports
allowing data trans fers up to 5Gb/s. The four USB 3.0 ports are shared with four of the US B 2.0 ports
(USB0 – USB3) from the EHCI1.
Legacy Keyboard/Mouse and wakeup from sleep states are supported. Over-current detection on al l
fourteen USB ports is supported. The following USB connectors are available in the IO Area.
USB Port 0 and 1 (via EHCI1/XHCI) are supplied on the combined USB0, USB1 and DP0 connector.
USB Port 2 and 3 (via EHCI1/XH CI) are supplied on the combined USB2, USB3 and DP1 connector.
USB Port 4 and 5 (via EHCI1) are supplied on the combined ETH1, USB4 and USB5 connector.
Note:
For USB2.0 cabling it is required to use only HiSpeed USB cable, specified in USB2.0 standard:
For USB3.0 cabling it is required to use only HiSpeed USB cable, specified in USB3.0 standard:
KTQ77/Flex Users Guide
KTD-N0848-C Page 32
Note
Type
Signal
PIN
Signal
Type
Note
IO
USB1-
USB1+
IO 1
PWR
5V/SB5V
1 2 3 4 GND
PWR
IO
RX1-
5 6 7 8 9
TX1+
IO
IO
RX1+
TX1-
IO
PWR
GND IO
USB0-
USB0+
IO 1
PWR
5V/SB5V
1 2 3 4 GND
PWR
IO
RX0-
5 6 7 8 9
TX0+
IO
IO
RX0+
TX0-
IO
PWR
GND
IO-Area Connectors
5.3.1 USB Connector 0/1 (USB0/1)
USB Ports 0 and 1 are mounted together with DP0 port and supports USB3.0/USB2.0.
Note 1: In order to meet the requirements of USB standard, the 5V input supply must be at least 5.00V.
Signal Description
USB0+ USB0-
RX0+ RX0-
TX0+ TX0-
USB1+ USB1-
RX1+ RX1-
TX1+ TX1-
5V/SB5V
Differential pair works as Data/Address/Command Bus.
5V supply for external devices. SB5V is supplied during powerdown to allow
wakeup on USB device activity. Protected by resettable 1A fuse covering both USB
ports.
KTQ77/Flex Users Guide
KTD-N0848-C Page 33
Note
Type
Signal
PIN
Signal
Type
Note
IO
USB3-
USB3+
IO 1
PWR
5V/SB5V
1 2 3 4 GND
PWR
IO
RX3-
5 6 7 8 9
TX3+
IO
IO
RX3+
TX3-
IO
PWR
GND IO
USB2-
USB2+
IO 1
PWR
5V/SB5V
1 2 3 4 GND
PWR
IO
RX2-
5 6 7 8 9
TX2+
IO
IO
RX2+
TX2-
IO
PWR
GND
Note
Type
Signal
PIN
Signal
Type
Note
1
PWR
5V/SB5V
1 2 3 4 GND
PWR
IO
USB5-
USB5+
IO 1
PWR
5V/SB5V
1 2 3 4 GND
PWR
IO
USB4-
USB4+
IO
IO-Area Connectors
5.3.2 USB Connector 2/3 (USB2/3)
USB Ports 2 and 3 are mounted together with DP1 port and supports USB3.0/USB2.0.
Note 1: In order to meet the requirements of USB standard, the 5V input supply must be at least 5.00V.
Signal Description
USB2+ USB2-
RX2+ RX2-
TX2+ TX2-
USB3+ USB3-
RX3+ RX3-
TX3+ TX3-
5V/SB5V
Differential pair works as Data/Address/Command Bus.
5V supply for external devices. SB5V is supplied during powerdown to allow
wakeup on USB device activity. Protected by resettable 1A fuse covering both USB
ports.
5.3.3 USB Connector 4/5 (USB4/5)
USB Ports 4 and 5 are mounted together with ETH1 port and supports USB2.0.
Note 1: In order to meet the requirements of USB standard, the 5V input supply must be at least 5.00V.
Signal Description
USB4+ USB4USB5+ USB5-
5V/SB5V
Differential pair works as Data/Address/Command Bus.
5V supply for external devices. SB5V is supplied during powerdown to allow wakeup
on USB device activity. Protected by resettable 1A fuse covering both USB ports.
KTQ77/Flex Users Guide
KTD-N0848-C Page 34
Note
Type
Signal
Signal
Type
Note
OA
CEN-OUT
TIP TIP
LINE1-IN-L
IA
OA
LFE-OUT
RING
RING
LINE1-IN-R
IA
PWR
GND
SLEEVE
SLEEVE GND
PWR
OA
REAR-OUT-L
TIP TIP
FRONT-OUT-L
OA
OA
REAR-OUT-R
RING
RING
FRONT-OUT-R
OA
PWR
GND
SLEEVE
SLEEVE GND
PWR
OA
SIDE-OUT-L
TIP TIP MIC1-L
IA
OA
SIDE-OUT-R
RING
RING MIC1-R
IA
PWR
GND
SLEEVE
SLEEVE GND
PWR
Shared with Audio Header
Shared with Audio Header
Shared with Audio Header
Shared with Audio Header
Shared with Audio Header
Shared with Audio Header
Shared with Audio Header
Shared with Audio Header
Shared with Audio Header
Shared with Audio Header
Port
2-channel
4-channel
6-channel
8-channel
Light Blue
Line in
Line in
Line in
Line in
Lime
Line out
Front speaker out
Front speaker out
Front speaker out
Pink
Mic in
Mic in
Mic in
Mic in
Audio header
- - -
Side speaker out
Audio header
-
Rear speaker out
Rear speaker out
Rear speaker out
Audio header
-
-
Center/ Subwoofer
Center/ Subwoofer
IO-Area Connectors
5.4 Audio Connector (IO Area)
The on-board Aud io circuit im plements 7.1+2 Channel High Def inition Audio with UAA (Un iversal Audio
Architecture), featuring five 24-bit stereo DACs and three 20-bit stereo ADCs. The Following Audio
connector is available in IO Area.
Audio Speakers, Line-in and Microphone are available in the stacked audiojack connector
Signal Description Note
FRONT-OUT-L Front Speakers (Speaker Out Left).
FRONT-OUT-R Front Speakers (Speaker Out Right).
REAR-OUT-L
REAR-OUT-R
SIDE-OUT-L Side speakers (Surround Out Left)
SIDE-OUT-R Side speakers (Surround Out Right)
CEN-OUT Center Speaker (Center Out channel).
LFE-OUT Subwoofer Speaker (Low Freq. Effect Out).
MIC1 MIC Input 1
LINE1-IN Line in 1 signals
Rear Speakers (Surround Out Left).
Rear Speakers (Surround Out Right).
KTQ77/Flex Users Guide
KTD-N0848-C Page 35
Signal
Description
Pull
U/D
Pull
U/D
- -
PWR
GND
5 9 RI I -
/5K - O DTR
4 8 CTS I -
/5K - O TxD
3 7 RTS O - /5K - I
RxD
2 6 DSR I -
/5K
/5K - I
DCD
1
IO-Area Connectors
5.5 COM1 Connector (IO Area)
Four RS232 serial ports are available on the KTQ77, COM1 is avai lab le in the IO Area while the oth er
COM ports are available on internal pin header connectors.
The typical definition of the signals in the COM ports is as follows:
TxD Transmitted Data, sends data to the communications link. The signal is set to the marking
state (-12V) on hardware reset when the transmitter is empty or when loop mode operation is
initiated.
RxD Received Data, receives data from the communications link.
DTR Data Terminal Ready, indicates to the modem etc. that the on-board UART is ready to
establish a communication link.
DSR Data Set Ready, indicates that the modem etc. is ready to establish a communications link.
RTS Request To Send, indicates to the modem etc. that the on-board UART is ready to exchange
data.
CTS Clear To Send, indicates that the modem or data set is ready to exchange data.
DCD Data Carrier Detect, indicates that the modem or data set has detected the data carrier.
RI Ring Indicator, indicates that the modem has received a ringing signal from the telephone line.
The pinout of Serial ports COM1 is as follows:
Note
Ioh/Iol Type Signal PIN Signal Type Ioh/Iol
Note
KTQ77/Flex Users Guide
KTD-N0848-C Page 36
Note
Type
Signal
PIN
Signal
Type
Note
PWR
3V3
12
24 GND
PWR
PWR
+12V
11
23 5V
PWR
PWR
+12V
10
22 5V
PWR
PWR
SB5V
9
21 5V
PWR I P_OK
8
20 -5V
PWR 1
PWR
GND
7
19 GND
PWR
PWR
5V
6
18 GND
PWR
PWR
GND
5
17 GND
PWR
PWR
5V
4
16 PSON#
OC
PWR
GND
3
15 GND
PWR
PWR
3V3
2
14 -12V
PWR
PWR
3V3
1
13 3V3
PWR
Note
Type
Signal
PIN
Signal
Type
Note
PWR
GND
2 4
+12V
PWR 1
PWR
GND
1 3
+12V
PWR
1
P_OK is a power good signal and should be asserted high by the power supply to indicate
Internal Connectors
6 Internal Connectors
6.1 Power Connector (ATX/BTXPWR)
The KTQ77 boar ds are designed to be supplied f rom a standard ATX (or BT X) power supply. Use of
BTX supply is not required for operation, but may be required to drive high-power PCIe cards.
ATX/ BTX Power Connector (J45):
Note 1: -5V supply is not used on-board.
See chapter “Power Consumption” regard ing input tolerances o n 3.3V, 5V, SB5V, +1 2 and -12V (also
refer to ATX specification version 2.2).
ATX+12V-4pin Power Connector (J46):
Note 1: Use of the 4-pin ATX+12V Power Connector is required for operation of all KTQ77 board
versions.
Signal Description
P_OK
PS_ON# Active low open drain signal from the board to the power supply to turn on the power supply
that the +5VDC and +3.3VDC outputs are above the undervoltage thresholds of the power
supply. When this signal is asserted high, there should be sufficient energy stored by the
converter to guarantee continuous power operation within specification. Conversely, when
the output voltages fall below the undervoltage threshold, or when mains power has been
removed for a time sufficiently long so that power supply operation is no longer guaranteed,
P_OK should be de-asserted to a low state. The recommended electrical and timing
characteristics of the P_OK (PWR_OK) signal are provided in the ATX12V Power SupplyDesign Guide.
It is strongly recommended to use an ATX or BTX supply in order to implement the
supervision of the 5V and 3V3 supplies. These supplies are not supervised on-board.
outputs. Signal must be pulled high by the power supply.
KTQ77/Flex Users Guide
KTD-N0848-C Page 37
Pull
U/D
1 CONTROL
O - - 2 SENSE
I
-
4K7 3 +12V
PWR
-
- 4 GND
PWR
-
-
Pull
U/D
-
2 SENSE
I
-
4K7 3 +12V
PWR
-
- 4 GND
PWR
-
-
Internal Connectors
6.2 Fan Connectors (FAN_CPU) (J28) and (FAN_SYS) (J29)
The FAN_CPU is used for the connection of the FAN for the CPU.
The FAN_SYS can be used to power, control and monitor a fan for chassis ventilation etc.
The 4pin header is recommended to be used for driving 4-wire type Fan in order to implement FAN
speed control. 3-wire Fan is also possible, but no fan speed control is integrated.
4-pin Mode:
PIN Signal Type Ioh/Iol
Signal Description
CONTROL PWM signal for FAN speed control
SENSE Tacho signal from the fan for supervision. The signals shall be generated by an open
collector transistor or similar. On-board is a pull-up resistor 4K7 to +12V. The signal has to
be pulsed, typically twice per rotation.
12V +12V supply for fan. A maximum of 2000mA can be supplied from this pin.
GND Power Supply GND signal
3-pin Mode:
PIN Signal Type Ioh/Iol
Note
Note
Signal Description
SENSE Tacho signal from the fan for supervision. The signals shall be generated by an open
collector transistor or similar. On-board is a pull-up resistor 4K7 to +12V. The signal has to
be pulsed, typically twice per rotation.
12V +12V supply for fan. A maximum of 2000mA can be supplied from this pin.
GND Power Supply GND signal
KTQ77/Flex Users Guide
KTD-N0848-C Page 38
Pull
U/D
1 KBDCLK
IOD
/14mA
2K7
2 KBDDAT
IOD
/14mA
2K7
3 MSCLK
IOD
/14mA
2K7
4 MSDAT
IOD
/14mA
2K7
5 5V/SB5V
PWR
- -
6
GND
PWR
- -
Internal Connectors
6.3 PS/2 Keyboard and Mouse connector (KBDMSE) (J15)
Attachment of a PS/2 keyboard/mouse can be done through the pinrow connector KBDMSE (J15).
Both interfaces utilize open-drain signalling w ith on-board pull-up.
The PS/2 mouse and keyboard is supplied from SB5V when in standby mode in order to enable
keyboard or mouse ac tivity to bring the system out from power saving states. T he supply is provided
through a 1.1A resettable fuse.
PIN Signal Type Ioh/Iol
Signal Description – Keyboard & and mouse Connector (KBDMSE).
Signal Description
MSCLK Bi-directional clock signal used to strobe data/commands from/to the PS/2 mouse.
MSDAT Bi-directional serial data line used to transfer data from or commands to the PS/2 mouse.
KDBCLK Bi-directional clock signal used to strobe data/commands from/to the PC-AT keyboard.
KBDDAT
Bi-directional serial data line used to transfer data from or commands to the PC-AT
keyboard.
Note
KTQ77/Flex Users Guide
KTD-N0848-C Page 39
Note
Type
Signal
PIN
Signal
Type
Note
Max. 0.5A
PWR
+12V
1 2 +12V
PWR
Max. 0.5A
Max. 0.5A
PWR
+12V
3 4 +12V
PWR
Max. 0.5A
Max. 0.5A
PWR
+12V
5 6 GND
PWR
Max. 0.5A
Max. 0.5A
PWR
+5V
7 8 GND
PWR
Max. 0.5A
Max. 0.5A
PWR
LCDVCC
9 10 LCDVCC
PWR
Max. 0.5A
2K2Ω, 3.3V
OT
DDC CLK
11
12 DDC DATA
OT
2K2Ω, 3.3V
3.3V level
OT
BKLTCTL
13
14 VDD ENABLE
OT
3.3V level
3.3V level
OT
BKLTEN#
15
16 GND
PWR
Max. 0.5A
LVDS
LVDS A0-
17
18 LVDS A0+
LVDS
LVDS
LVDS A1-
19
20 LVDS A1+
LVDS
LVDS
LVDS A2-
21
22 LVDS A2+
LVDS
LVDS
LVDS ACLK-
23
24 LVDS ACLK+
LVDS
LVDS
LVDS A3-
25
26 LVDS A3+
LVDS
Max. 0.5A
PWR
GND
27
28 GND
PWR
Max. 0.5A
LVDS
LVDS B0-
29
30 LVDS B0+
LVDS
LVDS
LVDS B1-
31
32 LVDS B1+
LVDS
LVDS
LVDS B2-
33
34 LVDS B2+
LVDS
LVDS
LVDS BCLK-
35
36 LVDS BCLK+
LVDS
LVDS
LVDS B3-
37
38 LVDS B3+
LVDS
Max. 0.5A
PWR
GND
39
40 GND
PWR
Max. 0.5A
Signal
Description
LVDS A0..A3
LVDS A Channel data
LVDS ACLK
LVDS A Channel clock
LVDS B0..B3
LVDS B Channel data
LVDS BCLK
LVDS B Channel clock
BKLTCTL
Backlight control (1), PWM signal to implement voltage in the range 0-3.3V
BKLTEN#
Backlight Enable signal (active low) (2)
VDD ENABLE
Output Display Enable.
VCC supply to the display. Power-on/off sequencing depending on selected (in BIOS
setup) display type. 5V or 3.3V selected in BIOS setup. Maximum load is 1A.
DDC CLK
DDC Channel Clock
Internal Connectors
Internal Connectors
6.4 Display connectors (Internal)
The KTQ77 family provides optionally internal on-board LVDS panel interface. For IO Area Display
Connectors (VGA and two DP’s), see earlier section.
Two graphic pipes are supported; meaning that up to two independent displays can be im plemented
using any two display connectors in IO Ar ea - and Internal (LVDS) connector (optionally).
Two graphic pipes are supported; meaning that up to two independent displays can be implemented
using any two of display connectors (IO Area - and Internal connectors).
Note: The KTQ77 on-board LVDS con nector supports single/dual channel, 1 8/24bit SPWG panels up
to resolution 1600x1200 or 1920x1080 (1920x1200 with limited frame rate is possible).
Signal Description – LVD S Flat Pan el Con nector :
LCDVCC
Notes: Windows API will be availab le to operate the BKLTCTL signal. Some Inver ters have a limited
voltage range 0- 2.5V for this signal: If voltage is > 2.5V the Inverter might latch up. Some
Inverters generates n oise on the BKLTCTL signal, res ulting in making the LVDS transm ission
failing (corrupted pic ture on the dis play). By adding a 1Kohm resistor in ser ies with this signal,
mounted in the Inverter end of the cable kit, the noise is limited and the picture is stable.
If the Backlight Enable is required to be active high, then check the following BIOS Chipset
setting: Backlight Signal Inver s ion = Enable d.
KTQ77/Flex Users Guide
KTD-N0848-C Page 40
Pull
U/D
1
GND
PWR - - 2
SATA* TX+
3
SATA* TX-
4
GND
PWR - - 5
SATA* RX-
6
SATA* RX+
7
GND
PWR - -
Signal
Description
Host receiver differential signal pair
Internal Connectors
6.5 SATA (Serial ATA) Disk interface (J22 – J27)
The KTQ77 boards have an integrated SATA Host controller (integrated in the PCH) that supports
independent DMA operation on six ports. One device can be installed on each port for a maximum of six
SATA devices. A point-to-point interface (SATA cable) is used for host to device connections. Data
transfer rates of up to 6.0G b/s ( typically 600MB/s) on SATA0 and SATA1 (blue connectors) and 3.0Gb/s
(typically 300MB/s) on SATA2, SAT A3, SATA4 and SATA5 (black connectors ). In case mSAT A is used
then the SATA2 is disabled.
The SATA controller supports:
2 to 6-drive RAID 0 (data striping)
2-drive RAID 1 (data mirroring)
3 to 6-drive RAID 5 (block-level stripin g w ith p ar ity).
4-drive RAID 10 (data striping and mirroring)
2 to 6-drive matrix RAID (different parts of a single drive can be assigned to different RAID
devices).
AHCI (Advanced Host Controller Interface)
NCQ (Native Command Queuing). NCQ is for faster data access.
Hot Swap
Intel® Rapid Recover Technology
2 – 256TB volume (Data volumes only)
Capacity expansion
TRIM in Windows 7 (in AHCI and RAID m ode for drives not part of a RAID volum e). (TRIM is f or
SSD data garbage handling).
The RAID (R edundant Array of Independent Dri ves) functionality is based on a firmware system with
support for RAID modes 0 1, 5 and 10.
SATA connector pinning:
The pinout of SATA ports SATA0 (J27), SATA1 (J26), SATA2 (J25), SAT A3 (J24), SATA4 (J23) and
SATA5 (J22) is as follows:
PIN Signal Type Ioh/Iol
The signals used for the primary SATA hard disk interface are the following:
SATA* RX+
SATA* RX-
SATA* TX+
SATA* TX-
“*” specifies 0, 1, 2, 3, 4, 5 depending on SATA port.
Host transmitter differential signal pair
Note
KTQ77/Flex Users Guide
KTD-N0848-C Page 41
Note
Type
Signal
PIN
Signal
Type
Note
1
PWR
5V/SB5V
1 2 5V/SB5V
PWR 1
IO
USB8-
3 4 USB9-
IO
IO
USB8+
5 6 USB9+
IO
PWR
GND
7 8 GND
PWR
NC
KEY
9 10 NC
NC
Signal
Description
Internal Connectors
Connector Definitions
6.6 USB Connectors (USB)
The KTQ77 board c ontains two EHCI (Enhanced H ost Contro ller Interf ace) host controllers ( EHCI1 and
EHCI2) that support up to fourteen USB 2.0 ports allowing data transfers up to 480Mb/s. Legacy
Keyboard/Mouse and wakeup from sleep states are supported. Over-current detection on al l fourteen
USB ports is supported.
Note that four USB 3.0 ports are shared with four of the USB 2.0 ports (USB0 – USB3) from the EHCI1.
The following USB ports are available on Internal Pinrows:
USB Port 6 and 7 (v ia EHC I1) are supplied on the USB6/7 internal pinrow FRONTPNL connector.
USB Port 8 and 9 (v ia EH CI2) are supplied on the USB8/9 internal pinrow connector.
USB Port 10 and 11 (via EHCI2) are supplied on the USB10/11 internal pinrow connector.
USB Port 12 and 13 (via EHCI2) are supplied on the USB12/13 internal pinrow connector.
Note: It is required to use only HiSpeed USB cable, specified in USB2.0 standard:
6.6.1 USB Connector 6/7
See Frontpanel Connector (FRONTPNL) description.
6.6.2 USB Connector 8/9 (USB8/9) (J18)
USB Ports 8 and 9 are supplied on the internal USB8/9 pinrow connector J18.
USB8+ USB8USB9+ USB9-
5V/SB5V
Differential pair works as Data/Address/Command Bus.
5V supply for external devices. SB5V is supplied during powerdown to allow
wakeup on USB device activity. Protected by resettable 1A fuse covering both USB
ports.
KTQ77/Flex Users Guide
KTD-N0848-C Page 42
Note
Type
Signal
PIN
Signal
Type
Note
1
PWR
5V/SB5V
1 2 5V/SB5V
PWR 1
IO
USB10-
3 4 USB11-
IO
IO
USB10+
5 6 USB11+
IO
PWR
GND
7 8 GND
PWR
NC
KEY
9 10 NC
NC
Note
Type
Signal
PIN
Signal
Type
Note
1
PWR
5V/SB5V
1 2 5V/SB5V
PWR 1
IO
USB12-
3 4 USB13-
IO
IO
USB12+
5 6 USB13+
IO
PWR
GND
7 8 GND
PWR
NC
KEY
9 10 NC
NC
Signal
Description
Internal Connectors
6.6.3 USB Connector 10/11 (USB10/11) (J17)
USB Ports 10 and 11 are supplied on the internal USB10/11 pinrow connector J17.
Signal Description
USB10+ USB10USB11+ USB11-
5V/SB5V
Differential pair works as Data/Address/Command Bus.
5V supply for external devices. SB5V is supplied during powerdown to allow
wakeup on USB device activity. Protected by resettable 1A fuse covering both USB
ports.
6.6.4 USB Connector 12/13 (USB12/13) (J16)
USB Ports 12 and 13 are supplied on the internal USB12/13 pinrow connector J16.
USB12+ USB12USB13+ USB13-
5V/SB5V
Note 1: In order to meet the requirements of USB standard, the 5V input supply must be at least 5.00V.
Differential pair works as Data/Address/Command Bus.
5V supply for external devices. SB5V is supplied during powerdown to allow
wakeup on USB device activity. Protected by resettable 1A fuse covering both USB
ports.
KTQ77/Flex Users Guide
KTD-N0848-C Page 43
Note
Ioh/Iol
Type
Signal
PIN
Signal
Type
Ioh/Iol
Note
- I
DCD
1 2 DSR I - - I
RxD
3 4 RTS O O
TxD
5 6 CTS I - O
DTR
7 8 RI I - - PWR
GND
9 10 5V
PWR - 1
Internal Connectors
6.7 Serial COM2 – COM4 Ports (J19, J20, J21)
Three RS232 serial ports are available on the KTQ77 via pin-row connector. (COM 1 is in the IO area
and is based on standard DB9 connector, see other section for more info).
The typical definition of the signals in the COM ports is as follows:
Signal Description
Transmitted Data, sends data to the communications link. The signal is set to the marking
TxD
RxD Received Data, receives data from the communications link.
DTR
DSR Data Set Ready, indicates that the modem etc. is ready to establish a communications link.
RTS
CTS Clear To Send, indicates that the modem or data set is ready to exchange data.
DCD Data Carrier Detect, indicates that the modem or data set has detected the data carrier.
The pinout of Serial ports COM2 (J20), COM3 (J19) and COM4 (J21) is as follows:
state (-12V) on hardware reset when the transmitter is empty or when loop mode operation is
initiated.
Data Terminal Ready, indicates to the modem etc. that the on-board UART is ready to
establish a communication link.
Request To Send, indicates to the modem etc. that the on-board UART is ready to exchange
data.
RI Ring Indicator, indicates that the modem has received a ringing signal from the telephone line.
Note 1: The COM2, COM3 and COM4 5V supply is fused with common 1.1A resettable fuse.
DB9 adapter cables (PN 821016 200mm long and 821017 100mm long) are availa ble for implementing
standard COM ports on chassis.
KTQ77/Flex Users Guide
KTD-N0848-C Page 44
PIN
Signal
Type
Note
1 CD_Left
IA 1 2 CD_GND
IA 3 CD_GND
IA 4 CD_Right
IA
1
Internal Connectors
6.8 Audio Connectors
The on-board Aud io circuit im plements 7.1+2 Channel High Def inition Audio with UAA (Un iversal Audio
Architecture), featuring five 24-bit stereo DACs and three 20-bit stereo ADCs.
The following Audio connectors are available as internal connectors.
6.8.1 CDROM Audio Input (CDROM) (J44)
CD-ROM audio input may be connected to this connector or it can be used as secondar y line-in signal.
Note 1: The definition of which pins are used for the Left and Right channels is not a worldwide
accepted standard. Some CDROM cable kits expect reverse pin order.
Signal Description
CD_Left
CD_Right
CD_GND Analogue GND for Left and Right CD.
Left and right CD audio input lines or secondary Line-in.
(This analogue GND is not shorted to the general digital GND on the board).
6.8.2 Line2 and Mic2
Line2 and Mic2 are accessible via Front Panel Connector, see Front Panel connector description.
KTQ77/Flex Users Guide
KTD-N0848-C Page 45
Note
Type
Signal
PIN
Signal
Type
Note
1
AO
LFE-OUT
1 2 CEN-OUT
AO 1
PWR
AAGND
3 4 AAGND
PWR 1
AO
FRONT-OUT-L
5 6 FRONT-OUT-R
AO 1
PWR
AAGND
7 8 AAGND
PWR 1
AO
REAR-OUT-L
9 10 REAR-OUT-R
AO 1 1
AO
SIDE-OUT-L
11
12 SIDE-OUT-R
AO 1
PWR
AAGND
13
14 AAGND
PWR 1
AI
MIC1-L
15
16 MIC1-R
AI 1
PWR
AAGND
17
18 AAGND
PWR 1 LINE1-L
19
20 LINE1-R
1
NC
NC
21
22 AAGND
PWR
PWR
GND
23
24 NC
NC O SPDIF-OUT
25
26 GND
PWR
Internal Connectors
6.8.1 Audio Header Connector (AUDIO_HEAD) (J47)
Note 1: Shared with Audio Stack connector
Signal Description
FRONT-OUT-L Front Speakers (Speaker Out Left).
FRONT-OUT-R Front Speakers (Speaker Out Right).
REAR-OUT-L
REAR-OUT-R Rear Speakers (Surround Out Right).
SIDE-OUT-L
SIDE-OUT-R
CEN-OUT Center Speaker (Center Out channel).
LFE-OUT
NC No connection
MIC1
LINE1 Line 1 signals
F-SPDIF-OUT S/PDIF Output
AAGND Audio Analogue ground
Rear Speakers (Surround Out Left).
Side speakers (Surround Out Left)
Side speakers (Surround Out Right)
Subwoofer Speaker (Low Freq. Effect Out).
MIC Input 1
KTQ77/Flex Users Guide
KTD-N0848-C Page 46
Pull
U/D
Ioh/
Iol
Ioh/
Iol
Pull
U/D
- -
PWR
USB6/7_5V
1 2 USB6/7_5V
PWR - - - - USB6-
3 4 USB7-
- - - - USB6+
5 6 USB7+
- - - -
PWR
GND
7 8 GND
PWR - - - -
NC
NC
9 10 LINE2-L
- - - -
PWR
+5V
11
12 +5V
PWR - - - /7mA
O
SATA_LED#
13
14 SUS_LED
O
7mA - - - PWR
GND
15
16 PWRBTN_IN#
I 1K1
4K7 - I
RSTIN#
17
18 GND
PWR - - - -
PWR
SB3V3
19
20 LINE2-R
- - - -
PWR
AGND
21
22 AGND
PWR - - - -
AI
MIC2-L
23
24 MIC2-R
AI - -
5V supply for external devices. SB5V is supplied during power down to allow
Internal Connectors
6.9 Front Panel Connec tor (FRONTPNL) (J36)
Note
Signal Description
USB10/11_5V
USB1+
USB1-
wakeup on USB device ac t i vit y. Protec t ed by resettable 1.1A fus e c over ing both USB
ports.
Universal Serial Bus Port 1 Differentials: Bus Data/Address/Command Bus.
Type Signal PIN Signal Type
Note
USB3+
USB3-
+5V
SATA_LED#
SUS_LED Suspend Mode LED (active high signal). Output 3.3V via 470Ω.
PWRBTN_IN#
RSTIN#
LINE2
MIC2 MIC2 is second stereo microphone input.
SB3V3
AGND
Note: In order to meet the requirements of USB standard, the 5V input supply must be at least 5.00V.
Universal Serial Bus Port 3 Differentials: Bus Data/Address/Command Bus.
Maximum load is 1A or 2A per pin if us ing IDC c on nector flat cable or crim p terminals
respectively.
SATA Activi t y LED , active low signa l (via 470Ω). Recommended is using Low Power
LED like HLM P4700 with anode connec ted to +5V (pin 11). W hen red color LED is
used, possible weak glowing could be noticed when the LED suppos ed to be off. In
order to eliminate th is problem a resistor 3K3 can be connected in parallel with the
LED or a diode can be connected in series with the LED.
Power Button In. Toggle this signal low to start the ATX / BTX PSU and boot the
board.
Reset Input. When pull ed lo w f or a m inimum 16ms, the reset proc ess wil l be initiated.
The reset process continues even though the Reset Input is kept low.
Line2 is second stereo Line signals
Standby 3.3V voltage
Analogue Ground for Audio
KTQ77/Flex Users Guide
KTD-N0848-C Page 47
Pull
U/D
Pull
U/D
2
2M/ - I
CASE_OPEN#
1 2 SMBC
/4mA
10K/ 1 - 25/25mA O S5#
3 4 SMBD
/4mA
10K/ 1 - 25/25mA
O
PWR_OK
5 6 EXT_BAT
PWR - - - O FAN3OUT
7 8 FAN3IN
I - - - -
PWR
SB3V3
9 10 SB5V
PWR - - -
IOT
GPIO0
11
12 GPIO1
IOT - -
IOT
GPIO2
13
14 GPIO3
IOT - -
IOT
GPIO4
15
16 GPIO5
IOT - -
IOT
GPIO6
17
18 GPIO7
IOT - - -
PWR
GND
19
20 GND
PWR - - - I GPIO8
21
22 GPIO9 I - - I
GPIO10
23
24 GPIO11
I - - I GPIO12
25
26 GPIO13
IOT - -
IOT
GPIO14
27
28 GPIO15
IOT - -
IOT
GPIO16
29
30 GPIO17
IOT - - -
PWR
GND
31
32 GND
PWR - - - 8/8mA
O
EGCLK
33
34 EGCS#
O
8/8mA
- - 8/8mA EGAD
35
36 TMA0 O - PWR
+12V
37
38 GND
PWR - - - O FAN4OUT
39
40 FAN4IN
I - - - -
PWR
GND
41
42 GND
PWR - - - -
PWR
GND
43
44 S3#
O
25/25mA
-
CASE OPEN, used to det ec t if the s ystem c ase has been ope ned. T his sign al’s s tatus
is readable, so it may be used like a GPI when the Intruder switch is not required.
PoWeR OK, signal is h igh if no power failures ar e detected. (T his is not the same as
the P_OK signal generated by ATX PSU).
(EXTernal BATtery) o ption for c onnecting + t erm inal of an ex tern al prim a r y cell ba tter y
charging and can be used with or without the on-board battery instal led.
General Purpose Inputs / Output. These Signals may be controlled or monitored
through the use of the KT-API-V2 (Application Programming Interface).
Internal Connectors
6.10 Feature Connector (FEATURE) (J30)
Note
Notes: 1. Pull-up to +3V3Dual (+3V3 or SB3V3). 2. Pull-up to on-board Battery.
Signal Description
Ioh/Iol Type Signal PIN Signal Type Ioh/Iol
Note
CASE_OPEN#
SMBC SMBus Clock signal
SMBD SMBus Data signal
S3#
S5# S5 sleep mode, acti ve lo w output, optionally used to deactivate external system.
PWR_OK
EXT_BAT
FAN3OUT FAN 3 speed control OUTput, 3.3V PWM signal can be used as Fan control voltage.
FAN3IN FAN3 Input. 0V to +3V3 amplitude Fan 3 tachometer input.
FAN4OUT FAN 4 speed control OUTput, 3.3V PWM signal can be used as Fan control voltage.
FAN4IN FAN4 Input. 0V to +3V3 amplitude Fan 3 tachometer input.
SB3V3 Max. load is 0.75A (1.5A < 1 sec.)
SB5V StandBy +5V supply.
GPIO0..17
EGCLK Extend GPIO Clock signal
EGAD Extend GPIO Address Data signal
EGCS# Extend GPIO Chip Select signal, active low
TMA0 Timer Output
+12V Max. load is 0.75A (1.5A < 1 sec.)
S3 sleep mode, active low output, optionally used to deactivate external system.
(2.5 - 3.47 V) (– term inal connec ted to GN D). T he exter nal batter y is protec ted against
KTQ77/Flex Users Guide
KTD-N0848-C Page 48
GPIO0
DAC0/GPJ0
AO/IOS
GPIO1
DAC1/GPJ1
AO/IOS
GPIO2
DAC2/GPJ2
AO/IOS
GPIO3
DAC3/GPJ3
AO/IOS
GPIO4
PWM2/GPA2
O8/IOS
GPIO5
PWM3/GPA3
O8/IOS
GPIO6
PWM4/GPA4
O8/IOS
GPIO7
PWM5/GPA5
O8/IOS
GPIO8
ADC0/GPI0
AI/IS
GPIO9
ADC1/GPI1
AI/IS
GPIO10
ADC2/GPI2
AI/IS
GPIO11
ADC3/GPI3
AI/IS
GPIO12
ADC4/WUI28/GPI4
AI/IS/IS
GPIO13
RI1#/WUI0/GPD0
IS/IS/IOS
GPIO14
RI2#/WUI1/GPD1
IS/IS/IOS
GPIO15
TMRI0/WUI2/GPC4
IS/IS/IOS
GPIO16
TMRI1/WUI3/GPC6
IS/IS/IOS
GPIO17
L80HLAT/BAO/WUI24/GPE0
O4/O4/IS/IOS
Internal Connectors
GPIO in more details.
The GPIO’s are contro lled vi a the ITE IT 8516F Em bedded Contr oll er. Eac h GPIO has 100pF t o ground,
clamping Diode to 3V3 and has m ultiplexed functionali ty. Some pins ca n be DAC (Digital t o Analogue
Converter output), PWM (Pulse Width Modulated signal output), ADC (Analogue to Digital Converter
input), TMRI (Tim er Counter Input), WUI (Wake Up Input), RI (Ring Indicator Input) or some special
function.
Signal IT8516F pin name Type Description
KTQ77/Flex Users Guide
KTD-N0848-C Page 49
Warning: Don’t leave the jumper in position 1-2, otherwise if power is disconnected,
the battery will fully deplete within a few weeks.
J11
pin1-2
pin2-3
X
-
Load Default BIOS Settings
-
X
Default position
-
-
No Function
Internal Connectors
!
Jumper (in Load Default BIOS Settings position)
J11 pin 3
J12
6.11 ”Load Default BIOS Settings” Jumpe r (J11)
The “Load Default BIOS Settings” Jumper (J11) can be used to recover from incorrect BIOS settings. As
an example, incorrect BIOS settings coursing no display to turn on can be erased by the Jumper.
The Jumper has 3 positions: Pin 1-2, Pin2-3 (default position) and not mounted.
To Load Default BIOS Settings:
1. Turn off power completely (no SB5V).
2. Move the Jumper to pin 1-2 for ~10 seconds.
3. Move the Jumper back to position 2-3 (default position).
4. Turn on power (use the Power On Button if required to boot).
5. Motherboard might automatically reboot a few times. Wait until booting is completed.
6.12 ClrRTC (J12)
Description
The ClrRTC (J12) connector is not used. Do not install any jumper in case J12 pin row is available.
KTQ77/Flex Users Guide
KTD-N0848-C Page 50
Warning: If the jumper (J41) is mounted and you make BIOS Upgrade etc. then the BIOS
Internal Connectors
!
6.13 SPI Recover Jumper (J41)
The SPI Recover Jumper is used to select BIOS Rec overy SPI Flash instea d of the BIOS Default SPI
Flash.
Normally Jumper is not installed and board boots on the BIOS Default SPI Flash.
Only in case the Default BIOS gets corrupted and board do not boot:
Then turn off power
Install Jumper (J41)
Try rebooting
After rebooting, rem ove the Jumper before D efault BIOS is recov ered by reloading BIOS ( for instance
by using latest BIOS upgrade package from web product page).
Verify that Default BIOS has been recovered by making a successful reboot.
Recovery SPI Flash will be Upgraded and not the BIOS Default SPI Flash.
This means that in case something goes wrong (power interruption or incorrect BIOS package
used etc.) when Upgrading BIOS, then the BIOS Recovery SPI Flash might get corrupted.
KTQ77/Flex Users Guide
KTD-N0848-C Page 51
Note
Pull U/D
Ioh/Iol
Type
Signal
PIN
Signal
Type
Ioh/Iol
Pull U/D
Note
- CLK
1 2 SB3V3
PWR - - - I CS0#
3 4 ADDIN
IO /10K
10K/
- NC
5 6 NC
- - -
10K/
IO
MOSI
7 8 ISOLATE#
IO /10K
- IO
MISO
9
10
GND
PWR - -
CLK
Serial Clock
Internal Connectors
6.14 SPI Connector (SPI) (J40)
The SPI Connector is nor mally not used. If however a SPI BIOS is connected via the SPI Con nector
then the board will try to boot on it.
Signal Description
SB3V3
CS0# CS0# Chip Select 0, active low.
ADDIN ADDIN input signal must be NC.
MOSI Master Output, Slave Input
ISOLATE#
MISO Master Input, Slave Output
3.3V Standby Voltage power line. Normally output power, but when Motherboard is
turned off then the on-board SPI Flash can be 3.3V power sourced via this pin.
The ISOLATE# input, act ive low, is normally NC, but must be connected to GN D when
loading SPI flash. Power Supply to the Mo therboard must be turned off when loading
SPI flash. The pull up resistor is connected via diode to 5VSB.
KTQ77/Flex Users Guide
KTD-N0848-C Page 52
1
OBSFN_A0
2
OBSFN_A1
3
GND
PWR
-
4
NC
NC
-
5
NC
NC
-
6
GND
PWR
-
7
NC
NC
-
8
NC
NC
-
9
GND
PWR
-
10
HOOK0
11
HOOK1
12
HOOK2
13
HOOK3
14
HOOK4
15
HOOK5
16
+5V
PWR
-
17
HOOK6
18
HOOK7
500R
(500R by 2x1K in parallel)
19
GND
PWR
-
20
TDO
/51R
21
TRST#
/51R
22
TDI
/51R
23
TMS
/51R
24
NC
NC
-
25
GND
PWR
-
26
TCK0
/51R
Internal Connectors
6.15 XDP-CPU (Debug Port for CPU) (J14)
The XDP-CPU (Intel Debug Port for CPU) connector is not mounted an d not suppor ted. XDP connector
layout (pads) is l ocated on the back side of PCB and i s prepared for the Molex 52435-2671 (or 52435-
2672).
Pin Signal Description Type Pull Up/Down Note
KTQ77/Flex Users Guide
KTD-N0848-C Page 53
-
-
3
GND
PWR
-
4
NC
NC
-
5
NC
NC
-
6
GND
PWR
-
7
NC
NC
-
8
NC
NC
-
9
GND
PWR
-
10
HOOK0
RSMRST#
Connected to HOOK6
11
HOOK1
PWRBTN#
12
HOOK2
NC
-
13
HOOK3
NC
-
14
HOOK4
NC
-
15
HOOK5
NC
-
16
+5V
PWR
-
17
HOOK6
Connected to HOOK1
18
HOOK7
RESET#
500R
(500R by 2x1K in parallel)
19
GND
PWR
-
20
TDO
210R/100R
21
TRST#
22
TDI
210R/100R
23
TMS
210R/100R
24
NC
NC
-
25
GND
PWR
-
26
TCK0
/51R
Internal Connectors
6.16 XDP-PCH (Debug Port for Chipset) (J13)
The XDP-PCH (Intel Debug Por t for Chipset) connector is n ot mounted and not support ed. XDP-PCH
connector layout (pads) is prepared for the Molex 52435-2671 (or 52435-2672).
Pin Signal Description Type Pull Up/Down
1 NCNC
2 NCNC
Note
KTQ77/Flex Users Guide
KTD-N0848-C Page 54
Note
Type
Signal
PIN
Signal
Type
Note
+12V
B1
A1
NC
+12V
B2
A2
+12V
+12V
B3
A3
+12V
GND
B4
A4
GND
SMB_CLK
B5
A5
NC
SMB_DATA
B6
A6
NC
GND
B7
A7
NC
+3V3
B8
A8
NC
NC
B9
A9
+3V3
SB3V3
B10
A10
+3V3
WAKE#
B11
A11
RST#
NC
B12
A12
GND
GND
B13
A13
PCIE_x16 CLK
PEG_TXP[0]
B14
A14
PCIE_x16 CLK#
PEG_TXN[0]
B15
A15
GND
GND
B16
A16
PEG_RXP[0]
CLKREQ
B17
A17
PEG_RXN[0]
GND
B18
A18
GND
PEG_TXP[1]
B19
A19
NC
PEG_TXN[1]
B20
A20
GND
GND
B21
A21
PEG_RXP[1]
GND
B22
A22
PEG_RXN[1]
PEG_TXP[2]
B23
A23
GND
PEG_TXN[2]
B24
A24
GND
GND
B25
A25
PEG_RXP[2]
GND
B26
A26
PEG_RXN[2]
PEG_TXP[3]
B27
A27
GND
PEG_TXN[3]
B28
A28
GND
GND
B29
A29
PEG_RXP[3]
NC
B30
A30
PEG_RXN[3]
CLKREQ
B31
A31
GND
GND
B32
A32
NC
PEG_TXP[4]
B33
A33
NC
PEG_TXN[4]
B34
A34
GND
GND
B35
A35
PEG_RXP[4]
Slot Connectors
7 Slot Connectors (PCIe, mSATA, miniPCIe, PCI)
7.1 PCIe Connectors
All members of the KTQ77 family supports one (x 16) (16-lane) PCI Expr ess port, one x4 PCI Expres s
port (in a x16 PCI Express connector) and two miniPCI Express ports.
The 16-lane (x16) PCI Express (PCIe 2.0 an d PCIe 3.0) port c an be used for external PCI Ex press
cards inclusive graphics card. It is located nearest the CPU. Maximum theoretic al bandwidth using 16
lanes is 16 GB/s.
The two miniPCIe (PCIe 2.0) is located on the backside of the board.
The 4-lane (x4) PCI Express (PCIe 2.0) can be used for any PCIex1, PCIex2 or PCI ex4 cards inclus ive
“Riser PCIex1 to PCI Dual flexible card“. (EFT samples support only PCIe x1).
7.1.1 PCI-Express x16 Connector (PCIe x16)
KTQ77/Flex Users Guide
KTD-N0848-C Page 55
GND
B36
A36
PEG_RXN[4]
PEG_TXP[5]
B37
A37
GND
PEG_TXN[5]
B38
A38
GND
GND
B39
A39
PEG_RXP[5]
GND
B40
A40
PEG_RXN[5]
PEG_TXP[6]
B41
A41
GND
PEG_TXN[6]
B42
A42
GND
GND
B43
A43
PEG_RXP[6]
GND
B44
A44
PEG_RXN[6]
PEG_TXP[7]
B45
A45
GND
PEG_TXN[7]
B46
A46
GND
GND
B47
A47
PEG_RXP[7]
CLKREQ
B48
A48
PEG_RXN[7]
GND
B49
A49
GND
PEG_TXP[8]
B50
A50
NC
PEG_TXN[8]
B51
A51
GND
GND
B52
A52
PEG_RXP[8]
GND
B53
A53
PEG_RXN[8]
PEG_TXP[9]
B54
A54
GND
PEG_TXN[9]
B55
A55
GND
GND
B56
A56
PEG_RXP[9]
GND
B57
A57
PEG_RXN[9]
PEG_TXP[10]
B58
A58
GND
PEG_TXN[10]
B59
A59
GND
GND
B60
A60
PEG_RXP[10]
GND
B61
A61
PEG_RXN[10]
PEG_TXP[11]
B62
A62
GND
PEG_TXN[11]
B63
A63
GND
GND
B64
A64
PEG_RXP[11]
GND
B65
A65
PEG_RXN[11]
PEG_TXP[12]
B66
A66
GND
PEG_TXN[12]
B67
A67
GND
GND
B68
A68
PEG_RXP[12]
GND
B69
A69
PEG_RXN[12]
PEG_TXP[13]
B70
A70
GND
PEG_TXN[13]
B71
A71
GND
GND
B72
A72
PEG_RXP[13]
GND
B73
A73
PEG_RXN[13]
PEG_TXP[14]
B74
A74
GND
PEG_TXN[14]
B75
A75
GND
GND
B76
A76
PEG_RXP[14]
GND
B77
A77
PEG_RXN[14]
PEG_TXP[15]
B78
A78
GND
PEG_TXN[15]
B79
A79
GND
GND
B80
A80
PEG_RXP[15]
CLKREQ
B81
A81
PEG_RXN[15]
NC
B82
A82
GND
Slot Connectors
KTQ77/Flex Users Guide
KTD-N0848-C Page 56
Note
Type
Signal
PIN
Signal
Type
Note
WAKE#
1
2
+3V3
PWR
NC
NC
3
4
GND
PWR
NC
NC
5
6
+1.5V
PWR 1
CLKREQ#
7
8
NC
NC
PWR
GND
9
10
NC
NC PCIE_mini CLK#
11
12
NC
NC PCIE_mini CLK
13
14
NC
NC
PWR
GND
15
16
NC
NC
NC
NC
17
18
GND
PWR
NC
NC
19
20
W_Disable#
2
PWR
GND
21
22
RST#
PCIE_RXN
23
24
+3V3 Dual
PWR
PCIE_RXP
25
26
GND
PWR
PWR
GND
27
28
+1.5V
PWR
PWR
GND
29
30
SMB_CLK
PCIE_TXN
31
32
SMB_DATA
PCIE_TXP
33
34
GND
PWR
PWR
GND
35
36
NC
NC
PWR
GND
37
38
NC
NC
PWR
+3V3 Dual
39
40
GND
PWR
PWR
+3V3 Dual
41
42
NC
NC
PWR
GND
43
44
NC
NC
CLK_MPCIE
45
46
NC
NC DATA_MPCIE
47
48
+1.5V
PWR RST_MPCIE#
49
50
GND
PWR 3 SEL_MSATA
51
52
+3V3 Dual
PWR
Slot Connectors
7.1.2 mSATA (J43)
The mSATA support mSATA SSD cards (up to full size). mPCI Express is not
supported. When mSATA card is installed then SATA2 (J25) (White connector) is
disabled.
Note 1: 10K ohm pull-up to 3V3.
Note 2: 2K2 ohm pull-up to 3V3 Dual.
Note 3: 100K ohm pull-up to 1V8 (S0 mode)
KTQ77/Flex Users Guide
KTD-N0848-C Page 57
Note
Type
Signal
PIN
Signal
Type
Note
WAKE#
1
2
+3V3
PWR
NC
NC
3
4
GND
PWR
NC
NC
5
6
+1.5V
PWR 1
CLKREQ#
7
8
NC
NC
PWR
GND
9
10
NC
NC PCIE_mini CLK#
11
12
NC
NC PCIE_mini CLK
13
14
NC
NC
PWR
GND
15
16
NC
NC
NC
NC
17
18
GND
PWR
NC
NC
19
20
W_Disable#
2
PWR
GND
21
22
RST#
PCIE_RXN
23
24
+3V3 Dual
PWR
PCIE_RXP
25
26
GND
PWR
PWR
GND
27
28
+1.5V
PWR
PWR
GND
29
30
SMB_CLK
PCIE_TXN
31
32
SMB_DATA
PCIE_TXP
33
34
GND
PWR
PWR
GND
35
36
NC
NC
NC
NC
37
38
NC
NC
NC
NC
39
40
GND
PWR
NC
NC
41
42
NC
NC
NC
NC
43
44
NC
NC
NC
NC
45
46
NC
NC
NC
NC
47
48
+1.5V
PWR
NC
NC
49
50
GND
PWR
NC
NC
51
52
+3V3
PWR
Slot Connectors
7.1.3 miniPCI-Express mPCIe (J42)
The miniPCI Express p or t mPCIe supports mPCIe cards only. (mSATA not supported)
Note 1: 10K ohm pull-up to 3V3 Dual.
Note 2: 2K2 ohm pull-up to 3V3 Dual.
KTQ77/Flex Users Guide
KTD-N0848-C Page 58
Note
Type
Signal
PIN
Signal
Type
Note
+12V
B1
A1
NC
+12V
B2
A2
+12V
+12V
B3
A3
+12V
GND
B4
A4
GND
SMB_CLK
B5
A5
NC
SMB_DATA
B6
A6
NC
GND
B7
A7
NC
+3V3
B8
A8
NC
NC
B9
A9
+3V3
SB3V3
B10
A10
+3V3
WAKE#
B11
A11
RST#
NC
B12
A12
GND
GND
B13
A13
PCIE_x16 CLK
PEG_TXP[0]
B14
A14
PCIE_x16 CLK#
PEG_TXN[0]
B15
A15
GND
GND
B16
A16
PEG_RXP[0]
1
CLKREQ
B17
A17
PEG_RXN[0]
GND
B18
A18
GND
PEG_TXP[1]
B19
A19
NC
PEG_TXN[1]
B20
A20
GND
GND
B21
A21
PEG_RXP[1]
GND
B22
A22
PEG_RXN[1]
PEG_TXP[2]
B23
A23
GND
PEG_TXN[2]
B24
A24
GND
GND
B25
A25
PEG_RXP[2]
GND
B26
A26
PEG_RXN[2]
PEG_TXP[3]
B27
A27
GND
PEG_TXN[3]
B28
A28
GND
GND
B29
A29
PEG_RXP[3]
NC
B30
A30
PEG_RXN[3]
NC
B31
A31
GND
GND
B32
A32
NC
Slot Connectors
7.1.4 PCI-Express x4 Connector (PCIe x4) (J33)
The KTQ77 supports one PCIex4 in a PCIex16 slot. All GND pins in the PCIEx16 connector are
connected to GND, but all signal pins from pin 33 and above are all unconnected.
Clock provides timing for all transactions on PCI and is an input to every PCI device. All other PCI
signals, except RST#, INTA#, INTB#, INTC#, and INTD#, are sampled on the risingedge of CLK and
all other timing parameters are defined with respect to this edge. PCI operates at 33MHz.
Power Management Event interrupt signal. Wake up signal.
Reset is used to bring PCI-specific registers, sequencers, and signals to a consistent state. What
except for reset states of required PCI configuration registers. Anytime RST# is asserted, all PCI
output signals must be driven to their benign state. In general, this means they must be
(they cannot be driven low or high during reset). To prevent AD, C/BE#, and PAR signals from
floating during reset, the central resource may drive these lines during reset (bus parking) but only to
RST# may be asynchronous to CLK when asserted or deasserted. Although asynchronous,
free edge. Except for configuration accesses, only
devices that are required to boot the system will respond after reset.
ADDRESS AND DATA
Address and Data are multiplexed on the same PCI pins. A bus transaction consists of an address
address phase is the clock cycle in which FRAME# is asserted. During the address phase
AD[31::00] contain a physical address (32 bits). For I/O, this is a byte address; for configuration and
ain the least significant byte
(lsb) and AD[31::24] contain the most significant byte (msb). Write data is stable and valid when
IRDY# is asserted and read data is stable and valid when TRDY# is asserted. Data is transferred
during those clocks where both IRDY# and TRDY# are asserted.
Bus Command and Byte Enables are multi plexed on the same PCI pins. During the address phase of
a transaction, C/BE[3::0]# define the bus command. During the data phase C/BE[3::0]# are used as
e Enables are valid for the entire data phase and determine which byte lanes
carry meaningful data. C/BE[0]# applies to byte 0 (lsb) and C/BE[3]# applies to byte 3 (msb).
Parity is even parity across AD[31::00] and C/BE[3::0]#. Parity generation is required by all PCI
agents. PAR is stable and valid one clock after the address phase. For data phases, PAR is stable
and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a
t remains valid until one c lock after the completion of the current
data phase. (PAR has the same timing as AD[31::00], but it is delayed by one clock.) The master
drives PAR for address and write data phases; the target drives PAR for read data phases.
INTERFACE CONTROL PINS
Cycle Frame is driven by the current master to indicate the beginning and duration of an access.
FRAME# is asserted to indicate a bus transaction is beginning. While FRAME# is asserted, data
deasserted, the transaction is in the final data phase or has
completed.
Initiator Ready indicates the initiating agent’s (bus master’s) ability to complete the current data
any clock both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates that valid
data is present on AD[31::00]. During a read, it indicates the master is prepared to accept data. W ait
cycles are insert ed until bo th IRDY# and TRDY# are asserted together.
Target Ready indicates the target agent’s (selected device’s) ability to complete the current data
phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed on
TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that valid
data is present on AD[31::00]. During a write, it indicates the target is prepared to accept data. Wait
cycles are inserted until both IRDY# and TRDY# are asserted together.
Stop indicates the current target is requesting the master to stop the c urrent transaction.
Lock indicates an atomic operation that may require multiple transactions to complete. W hen LOCK#
an address that is not currently locked. A
grant to start a transaction on PCI does not guarantee control of LOCK#. Control of LOCK# is
obtained under its own protocol in conjunction with GNT#. It is possible for different agents to use
master retains ownership of LOCK#. If a device implements Executable Memory, it
should also implement LOCK# and guarantee complete access exclusion in that memory. A target of
bridges that have system memory behind them should implement LOCK# as a target from the PCI
bus point of view and optionally as a master.
Initialization Device Select is used as a chip select during configuration read and write transactions.
Device Select, when actively driven, indicates the driving device has decoded its address as the
target of the current access. As an input, DEVSEL# indicates whether any device on the bus has
been selected.
Slot Connectors
7.2.1 Signal Description – PCI Slot Connector
CLK
PME#
RST#
effect RST# has on a device beyond the PCI sequencer is beyond the scope of this spe cification,
asynchronously tri-stated. SERR# (open drain) is floated. REQ# and GNT# must both be tri-stated
a logic low level–they may not be driven high.
deassertion is guaranteed to be a clean, bounce-
AD[31::00]
C/BE[3::0]#
PAR
FRAME#
IRDY#
phase followed by one or more data phases. PCI supports both read and write bursts.
The
memory, it is a DWORD address. During data phases AD[07::00] cont
Byte Enables. The Byt
read transaction. Once PAR is valid, i
transfers continue. W hen FRA ME# is
phase of the transaction. IRDY# is used in conjunction with TRDY#. A data phase is completed on
TRDY#
any clock both
STOP#
LOCK#
IDSEL
DEVSEL#
is asserted, non-exclusive transactions may proceed to
PCI while a single
an access that supports LOCK# must provide exclusion to a minimum of 16 bytes (aligned). Host
KTQ77/Flex Users Guide
KTD-N0848-C Page 61
ARBITRATION PINS (BUS MASTERS ONLY)
Request indicates to the arbiter that this agent desires use of the bus. This is a point to point signal.
Every master has its own REQ# which must be tri-stated while RST# is asserted.
Grant indicates to the agent that access to the bus has been granted. This is a point to point signal.
contain a valid request. The arbiter can only perform arbitration after RST# is deasserted. A master
a universal I/O buffer.
ERROR REPORTING PINS.
The error reporting pins are required by all devices and maybe asserted when enabled
Parity Error is only for the reporting of data parity errors during all PCI transactions except a Special
state and must be driven active by the agent receiving data
two clocks following the data when a data parity error is detec ted. The minimum duration of PERR# is
se that a data parity error is detected. (If sequential data phas es each
have a data parity error, the PERR# signal will be asserted for more than a single clock.) PERR#
are no special conditions when a data parity error may be lost or when reporting of an error may be
delayed. An agent cannot report a PERR# until it has claimed the access by asserting DEVSEL# (for
a target) and completed a data phase or is the master of the current transaction.
System Error is for reporting address parity errors, data parity errors on the Special Cycle command,
e interrupt (NMI) to be generated, a different reporting mechanism is required. SERR# is
pure open drain and is actively driven for a single PCI cloc k by the agent reporting the error. The
and hold times of all bused
signals. However, the restoring of SERR# to the deasserted state is accomplished by a weak pullup
up may take two to three clock periods to fully restore SERR#.
The agent that reports SERR#s to the operating system does so anytime SERR# is sampled
asserted.
INTERRUPT PINS (OPTIONAL).
sensitive,” asserted low (negative true), using open drain output
drivers. The assertion and deassertion of INTx# is asynchronous to CLK. A device asserts its INTx# line when
t remains asserted until the device
driver clears the pending request. When the request is cleared, the device deasserts its INTx# signal. PCI defines
For a single function device, only INTA# may be used while the other three interrupt lines have no meaning.
Interrupt A is used to request an interrupt.
Interrupt B is used to request an interrupt and only has meaning on a multi-function device.
Interrupt C is used to request an interrupt and only has meaning on a multi-function device.
Interrupt D is used to request an interrupt and only has meaning on a multi-function device.
Board type
Slot
REQ
GNT
IDSEL
INTA
INTB
INTC
INTD
KTQ77/Flex
0
REQ0
GNT0
17
INTA
INTB
INTC
INTD
1
REQ1
GNT1
18
INTF
INTG
INTH
INTE
Slot Connectors
REQ#
GNT#
PERR#
SERR#
Every master has its own GNT# which must be ignored while RST# is asserted.
While RST# is asserted, the arbiter must ignore all REQ# lines since they are tri-stated and do not
must ignore its GNT# while RST# is asserted. REQ# and GNT# are tri-state signals due to power
sequencing requirements when 3.3V or 5.0V only add-in boards are used with add-in boards that use
Cycle. The PERR# pin is sustained trione clock for each data pha
must be driven high for one clock before being tri-stated as with all sustained tri-state signals. There
or any other system error where the result will be catastrophic. If an agent does not want a nonmaskabl
assertion of SERR# is synchronous to the clock and meets the setup
(same value as used for s/t/s) which is provided by the system designer and not by the 61signaling
agent or central resource. This pull-
Interrupts on PCI are optional and defined as “level
requesting attention from its device driver. Once the INTx# signal is asserted, i
one interrupt line for a single function device and up to four interrupt lines for a multi-function device or connec tor.
INTA#
INTB#
INTC#
INTD#
7.2.2 KTQ77 PCI IRQ & INT routing
When using the 820982 “PCI Riser - Flex - 2slot w. arbiter” the lower slot has IDSEL / IRQs routed
straight through and the top slot has the routing: IDSEL=AD22, INT_PIRQ#D, INT_PIRQ#A,
INT_PIRQ#B, INT_PIRQ#C. 820982 PCI Riser shall be plugged into Slot 0 and jumper in AD30.
KTQ77/Flex Users Guide
KTD-N0848-C Page 62
On-board Connectors
Mating Connectors / Cables
Manufacturer
Type no.
Manufacturer
Type no.
FAN_CPU
Foxconn
HF2704E-M1
AMP
1375820-4 (4-pole)
FAN_SYS
AMP
1470947-1
AMP
1375820-3 (3-pole)
Molex
22-23-2061
Molex
22-01-2065
Kontron
KT 1046-3381
Foxconn
HF1104E
Molex
50-57-9404
Molex
70543-0038
Hon Hai
LD1807V-S52T
Molex
67489-8005
Kontron
KT 821035 (cable kit)
ATXEWR
Molex
44206-0002
Molex
5557-24R
ATX+12V-4pin
Lotes
ABA-POW-003-K02
Molex
39-01-2045
EDP
Tyco
5-2069716-3
Tyco
2023344-3
Don Connex
C44-40BSB1-G
Don Connex
A32-40-C-G-B-1
Kontron
KT 910000005
Kontron
KT 821515 (cable kit)
Kontron
KT 821155 (cable kit)
Wuerth
61201020621
Molex
90635-1103
Kontron
KT 821016 (cable kit)
Kontron
KT 821017 (cable kit)
USB68/9,
10/11, 12/13
USB6/7 (*)
(FRONTPNL)
-
Kontron
KT 821401 (cable kit)
Molex
87831-2620
Molex
51110-2651
Kontron
KT 821043 (cable kit)
Pinrex
512-90-24GBB3
Molex
90635-1243
Kontron
KT 821042 (cable kit)
Foxconn
HS5422F
Don Connex
A05c-44-B-G-A-1-G
Onboard/mating connector
8 On-board - & mating connector types
The Mating connectors / Cables are co nnectors or cable kits which are fitting th e On-board connec tor.
The highlighted cable kits are included in the “KTQ77 Cable & Driver Kit” PN 826599, in different
quantities depending on type of connector. For example there are 4x 821017 COM cables and 6x
821035 SATA cables.
Connector
KBDMSE
CDROM
SATA
LVDS
COM1,2, 3, 4
Pinrex 512-90-10GBB2 Kontron
AUDIO_HEAD
FRONTPNL
FEATURE
* USB6/USB7 is located in FRONTPNL connector. Depending on application KT 821401 can be used.
Note: Only one connector will be m entioned for each type of on-board connector even t hough several
types with same fit, form and function are approved and could be used as alternative. Please also notice
that standard connectors like DVI, DP, PCIe, miniPCIe, PCI, Audio Jack, Ethernet and USB is not
included in the list.
Blue text for settings that can be changed. White text for actual setting to be changed via the control keys
BIOS - Main
10 BIOS
The BIOS Setup is used to view and configure BIOS settings for the board. The BIOS Setup is
accessed by pressing the <Del> -key after the Power-On Self-Test (POST) memory test begins and
before the operating system boot begins.
The BIOS settings will be loaded a utom atical ly whe n load ing “ Restore Def ault” s ee “Sav e & Exi t” m enu.
In this Users Guide the default settings are indicated by bold. Please notice that “Restore User
Defaults” might have different set of default values.
10.1 Main
BIOS Vendor
Core Version
Compliancy
BIOS Version
Build Date and Time
EC Firmware Version
Board Information
Product Name
PCB ID
Serial #
Part #
Boot Count
System Language
System Date
System Time
Access Level
American Megatrends
4.6.5.4
UEFI 2.3.1; PI 1.2
29
01/07/2014 13:58:49
V0.19 03/31/13
KTQ77/FLEX
01
01145890
64710002
92
[English]
[Wed 01/08/2014]
[14:29:25]
Administrator
language.
↑↓ : Select Item
Enter: Select
+/- : Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save & Exit
ESC: Exit
(Black text for settings that cannot be changed via control keys)
The following table describes the changeable settings:
support Completion Timeout
programmability, modify the
Completion Timeout value is
allowed.
Default: 50us to 50ms.
Shorter:
supported by hardware.
Longer: software will use longer
timeout ranges.
↑↓ : Select Item
Enter: Select
+/- : Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save & Exit
ESC: Exit
KTQ77/Flex Users Guide
KTD-N0848-C Page 73
BIOS - Advanced
Function Selection Description
In device Functions that support Completion
Completion Timeout
ARI Forwarding
AtomicOp Requester Enable
AtomicOp Egress Blocking
IDO Request Enable
IDO Completion Enable
LTR Mechanism Enable
End-End TLP Prefix Blocking
Target Link Speed
Clock Power Management
Compliance SOS
Hardware Autonomous Width
Hardware Autonomous Speed
Default
Shorter
Longer
Disabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Auto
Force to 2.5 GT/s
Force to 5.0 GT/s
Disabled
Enabled
Disabled
Enabled
Enabled
Disabled
Enabled
Disabled
Timeout programmability, modify the
Completion Timeout range value is allowed.
Default: 50us to 50ms.
Shorter: shorter ranges supported by HW.
Longer: longer ranges implemented by SW.
If supported by HW and Enabled, the
Downstream Port disables its traditional
Device Number field being 0 enforcement
when turning a Type1 Configuration Req ues t
into a Type0 Configuration Request, permitting
access to Extended Functions in an ARI
Device immediately below the port.
If supported by HW and Enabled, initiate
AtomicOp Requests only if Bus Master Enable
bit is in the Command Register Set.
If supported by HW and Enabled, outbound
AtomicOp Requests via Egress Ports will be
blocked.
If supported by HW and Enabled, permit
setting the number of ID-Based Ordering
(IDO) bit (Attribute[2]) requests to be initiated.
If supported by HW and Enabled, permit
setting the number of ID-Based Ordering
(IDO) bit (Attribute[2]) requests to be initiated.
If supported by HW and Enabled, enable the
Latency Tolerance Reporting (LTR)
Mechanism.
If supported by HW and Enabled, block
forwarding of TLPs containing End-End TLP
Prefixes.
If supported by HW and set to ´Force to 2.5
GT/s´ for Downstream Ports, this sets an
upper limit on link operational speed by
restricting the values advertised by the
Upstream component in its training
sequences. When ´Auto´ is selected HW
initialized data will be used.
If supported by HW and Enabled, device is
permitted to use CLKREQ# signal for power
management of Link clock in accordance to
protocol defined in appropriate form factor
specification.
If supported by HW and Enabled, force
LTSSM to send SKP Ordered Sets between
sequences when sending Compliance Pattern
or Modified Compliance Pattern.
If supported by HW and Disabled, disab le the
HW ability to change link width except width
size reduction for the purpose of correcting
unstable link operation.
If supported by HW and Disabled, disable the
HW ability to change link speed except speed
rate reduction for the purpose of correcting
unstable link operation.
Linux (OS optimized for HyperThreading Technology) and
Disabled for other OS (OS not
optimized for
Hyper-Threading Technology).
When Disabled only one thread
per enabled core is enabled.
↑↓ : Select Item
Enter: Select
+/- : Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save & Exit
ESC: Exit
Hyper-threading
(Note1)
Active Processor Cores
Limit CPUID Maximum
Execute Disable Bit
Intel Virtualization
Technology
Note1: Not present if using CPU not supporting this feature.
Disabled
Enabled
All
1
Disabled
Disabled
Enabled
Disabled
Enabled
Enabled for Windows XP and Linux (OS
optimized for Hyper-Threading Technology) and
Disabled for other OS (OS not optimized for
Hyper-Threading Technology). When Disabled
only one thread per enabled core is enabled.
Number of cores to enable in each processor
package.
Disabled for Windows XP
XD can prevent certain classes of malicious
buffer overflow attacks when combined with
supporting OS (Windows Server 2003 SP1,
Windows XP SP2, SuSE Linux 9.2, RedHat
Enterprise 3 Update 3.)
When enabled, a VMM can utilize the additional
hardware capabilities prov i ded b y Vanderp oo l
Technology.
KTQ77/Flex Users Guide
KTD-N0848-C Page 77
BIOS - Advanced
Notes:
Intel HT Technology (Hyper Threading Technology) is a performance feature which allows one core on
the processor to appear like 2 cores to the operating system. This doubles the execution resources
available to the O/S, which potentially increases the performance of your overall system.
Intel VT-x Technology (Virtualization Technology) Previously codenamed "Vanderpool", VT-x represents
Intel's technology for virtualization on the x86 platform. In order to support “Virtualization Technology”
the CPU must support VT-x and the BIOS setting “Intel Virtualization Technology” must be enabled.
Intel SMX Technology (Safer Mode Extensions Technology) is a part of the Trusted Execution
Technology.
Enable or disable RAID5 feature.
Enable or disable Intel Rapid Recovery
Technology.
If enabled, then the OROM UI is shown.
Otherwise, no OROM banner or information will
be displayed if all disks and RAID volumes are
Normal.
If enabled, indicates that the HDD password
unlock in the OS is enabled.
If enabled, indicates that the LED/SGPIO
hardware is attached and ping to locate feature
is enabled on the OS.
If enabled, then only IRRT volumes can span
internal and eSATA drives. If disabled, then any
RAID volume can span internal and eSATA
drives.
Enable or disable Smart Response Technology
If enabled, indicates the delay of the OROM UI
Splash Screen in normal status.
KTQ77/Flex Users Guide
KTD-N0848-C Page 81
Enabled
Enabled
Hot Plug
External SATA
Spin Up Device
Hot Plug
External SATA
Spin Up Device
Enabled
Hot Plug
External SATA
Spin Up Device
Hot Plug
External SATA
Spin Up Device
BIOS - Advanced
Remaining SATA Config uratio n menu description:
Function Selection Description
Port 0
Hot Plug
External SATA
SATA Device Type
Spin Up Device
Port 1
Hot Plug (see same function above) (see same function above)
External SATA (see same function above) (see same function above)
SATA Device Type (see same function above) (see same function above)
Spin Up Device (see same function above) (see same function above)
Port 2
Disabled
Disabled
Enabled
Disabled
Enabled
Hard Disk Drive
Solid State Drive
Disabled
Enabled
Disabled
Disabled
Enabled
Enable or Disable SATA Port.
Designates this port as Hot Pluggable.
External SATA Support.
Identify the SATA port is connected to Solid
State Drive or Hard Disk Drive.
On an edge detect from 0 to 1, the PCH
starts a COMRESET initialization sequence
to the device.
Enable or Disable SATA Port.
Enable or Disable SATA Port.
Port 3
Port4
Port5
(see same function above) (see same function above)
(see same function above) (see same function above)
(see same function above) (see same function above)
Disabled
Enabled
(see same function above) (see same function above)
(see same function above) (see same function above)
(see same function above) (see same function above)
Disabled
(see same function above) (see same function above)
(see same function above) (see same function above)
(see same function above) (see same function above)
Disabled
Enabled
(see same function above) (see same function above)
(see same function above) (see same function above)
(see same function above) (see same function above)
Intel TXT support only can be enabled/disabled if SMX is enabled. VT and VT-d support must also be enabled prior to TXT.
Secure Mode Extensions (SMX) Enabled
Intel TXT support[Disabled]
TXT (LT) support.
↑↓ : Select Item
Enter: Select
+/- : Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save & Exit
ESC: Exit
SMX (Intel Secure Mode Extension) instr ucti ons are enab led if supported by the CPU, so no BIOS
settings are present.
VT (Intel Virtualization Technology) is enabled/disabled in the menu: Advanc ed > CPU Configuration.
VT-d can be enabled/disabled in the menu: Chipset > System Agent (SA) Co nfi gu ration .
BIOS Hotkey Pressed MEBx Selection ScreenHide Un-Configure ME ConfirmationMEBx Debug Message OutputUn-Configure MEAMT Wait TimerDisable ME ASF Active Remote Assistance Process USB Configure PET Progress AMT CIRA Timeout
Management Technology BIOS
Extension.
Note: iAMT H/W is always
enabled.
This option just controls the
BIOS Extension execution.
If enabled, this requires
additional firmware in the SPI
device.
↑↓ : Select Item
Enter: Select
+/- : Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save & Exit
ESC: Exit
Function Selection Description
Intel AMT
BIOS Hotkey Pressed
(Note1)
MEBx Selection Screen
(Note1)
Hide Un-Configure ME
Confirmation (Note1)
MEBx Debug Message
Output (Note1)
Un-Configure ME (Note1)
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Enable/Disable Intel ® Active Man agement
Technology BIOS Extensio n.
Note: iAMT H/W is always enabled.
This option just controls the BIOS Exte ns ion
execution.
If enabled, this requires additional firmware in
the SPI device.
OEMFlag Bit 1:
Enable/Disabled BIOS hotk e y press .
OEMFlag Bit 2:
Enable/Disabled BIOS MEBx Select ion Scr een .
OEMFlag Bit 6:
Hide Un-Configure ME without pass wor d
Confirmation Prompt
OEMFlag Bit 14:
Enable MEBx Debug Message Output.
OEMFlag Bit 15:
Un-Configure ME without pass word.
KTQ77/Flex Users Guide
KTD-N0848-C Page 86
Function
Selection
Description
Enabled
BIOS - Advanced
AMT Wait Timer (Note1) 0 - 65535 (Note4)
Disable ME (Note1)
ASF (Note1)
Active Remote Assistance
Process (Note1)
USB Configure (Note1)
PET Progress (Note1)
AMT CIRA Timeout
(Note1)
(Note5)
Watchdog (Note2)
OS Timer (Note3) 0 - 65535 (Note4) Set OS watchdog timer.
Note1: Only if Intel AMT = Enabled.
Note2: This Watchdog function is unsupported.
Recomm endation, us e Watchdog function present in Hardware Health Configuration menu.
Note3: Only if Watchdog = Enabled.
Note4: To enter number use digit keys and/or +/- keys.
Note5: Only if Active Remote Assistance Process = Enabled.
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
0 – 255 (Note4)
Disabled
Enabled
Set timer to wait before sending
ASF_GET_BOOT_OPTIONS.
Set ME to Soft Temporary Disabled.
Enable/Disabled Alert Specification Format.
Trigger CIRA boot.
Enable/Disable USB Configure function.
Users can Enable/Disable PET Events progress
to receive PET events or not.
OEM defined timeout for MPS connection to be
established.
0 – use the default timeout value of 60
Note:
Automatic acoustic m anag ement (AAM) is a method for reduc in g acous tic emanations in AT Attachm ent
(ATA) mass storage dev ices, such as ATA hard disk drives and ATAPI optical disc drives . AAM is an
optional feature set f or ATA/ATAPI devices; when a device sup ports AAM, the acoustic managem ent
parameters are adjustable through a software or firmware user interface.
The ATA/ATAPI sub-command for setting the level of AAM operati on is an 8-bit value from 0 to 255.
Most modern drives ship with the vendor-defined value of 0x00 in the acoustic managem ent setting.
This often translates to the max -performance value of 254 stated in the standard . Values between 1 28
and 254 (0x80 - 0xFE) ena ble th e f eatur e an d s elect most-quiet to most-per f ormance s etti ngs al ong th at
range. Though hard drive manufacturers may support the whole range of values, the settings are
allowed to be banded so many values could provide the same acoustic performance.
Enabled
Disabled
Option to Enable or Disable Automatic Acoustic
Management.
USB transfer time-out
Device reset time-out
Device power-up delay
[Enabled]
[Enabled]
[Enabled]
[Disabled]
[Enabled]
[20 sec]
[20 sec]
[Auto]
AUTO option disables legacy
support if no USB devices are
connected. DISABLE option
will keep USB devices available
only for EFI applications.
↑↓ : Select Item
Enter: Select
+/- : Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save & Exit
ESC: Exit
KTQ77/Flex Users Guide
KTD-N0848-C Page 89
1 sec
20 sec
BIOS - Advanced
Function Selection Description
Enables Legacy USB support.
Legacy USB Support
USB3.0 Support
XHCI Hand-off
EHCI Hand-off
USB Mass Storage Driver
Support
Enabled
Disabled
Auto
Enabled
Disabled
Enabled
Disabled
Disabled
Enabled
Enabled
Disabled
AUTO option disables legacy support if no
USB devices are connected. DISABLE
option will keep USB devices available only
for EFI applications.
Enable/Disable USB3.0 (XHCI) Controller
support.
This is a workaround for OSes without XHCI
hand-off support.
The XHCI ownership change should be
claimed by XHCI driver.
This is a workaround for OSes without EHCI
hand-off support. The EHCI ownership
change should be claimed by EHCI driver.
Enable/disable USB Mass Stor a ge Driv er
Support.
USB transfer time-out
Device reset time-out
Device power-up dela y
5 sec
10 sec
10 sec
20 sec
30 sec
40 sec
Auto
Manual
The time-out value for Control, Bulk, and
Interrupt transfers.
USB mass storage device Start Unit
command time-out.
Maximum time the device will take before it
properly reports itself to the Host Controller.
‘Auto’ uses default value: for a Root port it is
100 ms, for a Hub port the delay is taken
from Hub descriptor.
System Temperature
System Temperature Ext
CPU Temperature
System Fan Speed
System Temperature Ext Type
Fan Cruise Control
Fan Settings Fan Min limit Fan Max limit
CPU Fan Speed
Fan Cruise Control
Fan Settings Fan Min limit Fan Max limit
Watchdog Function
PC Speaker/Beep
: 30ºC/86ºF
: 24ºC/75ºF
: 49.10ºC/120ºF
: 1543 RPM
[ OneWire @ GPIO16]
[Thermal]
35
0
100
: 1374 RPM
[Thermal]
50
0
100
0
[Enabled]
Thermal: does regulate fan
speed according to specified
temperature.
Speed: does regulate according
to specified RPM.
↑↓ : Select Item
Enter: Select
+/- : Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save & Exit
ESC: Exit
KTQ77/Flex Users Guide
KTD-N0848-C Page 98
Minimum PWM %, can be used to make sure
limit.
Maximum PWM %, can be used to limit the fan
BIOS - Advanced
Function Selection Description
System Temperature Ext
Type
(note1)
Fan Cruise Control
(System Fan)
Fan Settings
(System Fan)
Fan Min limit
(System Fan) (note5) 0 (note6)
Fan Max limit
(System Fan) (note5)
Fan Cruise Control
(CPU Fan)
Fan Settings
(CPU Fan)
Disabled
LM75 @ 0x90
OneWire @ GPIO16
Disabled
Thermal (note2)
Speed
30 – 90 (note2,note3)
1000 – 9999 (note4)
100
(note6)
Disabled
Thermal
Speed
30 – 90 (note3)
1000 – 9999 (note4)
Use external connected sensor instead of
onboard.
Disabled = Full speed.
Thermal: Regulate according to specified ºC.
Speed: Regulate according to specified RPM.
Specify limit temperature in ºC or limit RPM
(depending on Thermal or Speed selection)
Minimum PWM %, can be used to make sure
fan is always active. Make sure Min limit < Max
limit.
Maximum PWM %, can be used to limit the fan
noise. Make sure Min limit < Max limit.
Disabled = Full speed.
Thermal: Regulate according to specified ºC.
Speed: Regulate according to specified RPM.
Specify limit temperature in ºC or limit RPM
(depending on Thermal or Speed selection)
Fan Min limit
(CPU Fan) (note7) 0 (note6)
Fan Max limit
(CPU Fan) (note7)
Watchdog Function 0 - 255 (note8)
PC Speaker/Beep
Note1: Only visible if external temperature sensor like PN1053-4925 “Cable Temperature Sensor - 44P,
400 mm” is connected.
Note2: Only visible if external temperature sensor is connected and if System Temperature Ext Type is
not Disabled.
Note3: ºC (if Fan Cruise Control = Thermal) use either digit keys to enter value or +/- keys to
increase/decrease value. Don’t use mix of digit keys and +/- keys.
Note4: RPM (if Fan Cruise Control = Speed) use either digit keys to enter value or +/- keys to
increase/decrease value by 100. Don’t use mix of digit keys and +/- keys.
Note5: Only visible if external temperature sensor is connected and if System Fan Cruise Control is
Thermal.
Note6: Use number keys to enter value.
Note7: Only visible if CPU Fan Cruise Control is Thermal.
Note8: Seconds, use digit keys to enter value. Value 0 means Watchdog is disabled. Refer to “KT-API-
V2 User Manual” to control the Watchdog via API or refer to “KT-API-V2 User Manual DLL” ho w to
control Watchdog via Windows DLL.
100
(note6)
Disabled
Enabled
fan is always active. Make sure Min limit < Max
noise. Make sure Min limit < Max limit.
0 = Disabled.
Enter the service interval in seconds before
system will reset.
Refer to manual how to reload the timer.
Control the default beeps during boot of the
system. This setting will also control the beep
during enumeration and (un)plug of USB.