Added info on System Overview. Added support of Windows 7.
New BIOS option “Replace GFX subid”. Added note on XP Video
Driver (OS setup). Added Power consumption for BGA versions.
F
Sep. 9th 2010
MLA
Added KT690/mITX BGA. Minor corrections.
Feature connector corrections and added note on pin 3 and 4.
corrected. Added warning to Installation Guide (turn off PSU).
Correction to LAN connector pinning. Batter y alternat i ve add ed.
Devices. Corrected Video Display Devices.
Added FDD cable info. Corrections to Floppy connector. CPU
List updated. Added Clock Distribution.
Battery lifetime info added. Minor corrections, additions and
layout improvements.
A
Jul. 23rd, 2008
PJA
Updated
0
Dec. 11th, 2007
PJA
First preliminary manual version.
Document revision history.
J Jun. 1st 2012 MLA
I Aug. 29th 2011 MLA
G Jan. 19th 2011 MLA
E Apr. 22nd 2010 MLA
D May. 14th 2009 MLA
C Sep. 16th 2008 MLA
B Aug. 11th 2008 MLA
Copyright Notice:
Copyright 2008, KONTRON Technology A/S, ALL RIGHTS RESERVED.
No part of this document may be reproduced or transmitted in any form or by any means, electronically or
mechanically, for any purpose, without the express written permission of KONTRON T ec hnology A/S.
Trademark Acknowledgem ent:
Brand and product names are trademarks or registered trademarks of their respective owners.
Disclaimer:
KONTRON Technology A/S reserves the right to make changes, without notice, to any product, including
circuits and/or software described or contained in this manual in order to improve design and/or
performance.
Specifications listed in this manual are subject to change without notice. KONTRON Technology assumes no
responsibility or liability for the use of the described product(s), conveys no license or title under any patent,
copyright, or mask work rights to these products, and makes no representations or warranties that these
products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Applications that are described in this manual are for illustration purposes only. KONTRON Technology A/S
makes no representation or warranty that such application will be suitable for the specified use without
further testing or modification.
Added “mounting the board to chassis”. Memory size has been
Added BIOS setting: Default init boot order. Correted Force Boot
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Life Support Policy
KONTRON Technology’s PRODUCTS ARE NOT FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL OF THE GENERAL
MANAGER OF KONTRON Technology A/S.
As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into
body, or (b) support or sustain life and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in significant injury to
the user.
2. A critical component is any component of a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness.
KONTRON Technology Technical Support and Services
If you have questions about installing or using your KONTRON Technology Product, check this User’s
Manual first – you will find answers to most questions here. To obtain support, please contact your local
Distributor or Field Application Engineer (FAE).
Before Contacting Support: Please be prepared to provide as much information as possible:
CPU Board
1. Type.
2. Part-number.
3. Serial Number.
Configuration
1. CPU Type, Clock speed.
2. DRAM Type and Size.
3. BIOS Revision (Find the Version Info in the BIOS Setup).
4. BIOS Settings different than Default Settings (Refer to the BIOS Setu p Section).
System
1. O/S Make and Version.
2. Driver Version numbers (Graphics, Network, and Audio).
3. Attached Hardware: Harddisks, CD-rom, LCD Panels etc.
Serial Ports .................................................................................................................................... 47 4.11
Main Menu ......................................................................................................................................... 67 8.2
Advanced Menu ................................................................................................................................ 68 8.3
Advanced settings – CPU Configuration .................................................................................... 68
8.3.1
8.3.2 Advanced settings – IDE Configuration ...................................................................................... 69
8.3.3 Advanced settings – LAN Configuration ..................................................................................... 72
PCIPnP Menu .................................................................................................................................... 79 8.4
Boot Menu ......................................................................................................................................... 80 8.5
Security Menu ................................................................................................................................... 83 8.6
Chipset Menu .................................................................................................................................... 84 8.7
Advanced Chipset Settings – North Bridge Chipset Configuration ............................................ 84
8.7.3 Advanced Chipset Settings - AMD 690G Configur ati on ............................................................. 86
Power ................................................................................................................................................ 89 8.8
Exit Menu .......................................................................................................................................... 90 8.9
AMI BIOS BEEP CODES ......................................................................................................................... 91
9.
10. OS SETUP ............................................................................................................................................. 92
This manual describes the KT690/mITX, KT690/mITX-FW and KT690/mITX (BGA) boards made by
KONTRON Technology A/S. The boards will also be denoted KT690 family if no differentiation is required.
The KT690/mITX , KT690/mITX-FW are to be used with the Mobile AMD Sempron™ and AMD Turion™ 64
X2 Mobile Processors for S1 socket and the KT690/mITX (BGA) is available in two versions with premounted BGA processor: Single Core 210U and Dual Core L325.
Use of this manual implies a basic knowledge of PC-AT hard- and software. This manual is focused on
describing the KT690 Board’s special features and is not intended to be a standard PC-AT textbook.
New users are recomm ended to study the short installatio n procedure stated in chapt er 3 before switchingon the power.
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!
Warnings: Turn off PSU (Power Supply Unit) com pletely (no mains power connected to the
directly on a metal plate etc. (battery 3V connected to ground via IO Connector housing).
CPU Pin 1 marking
Screwdriver actuated
CPU FAN
connector
Clip holder
Clip holder
Clip
2. I nst allation procedure
Installing the board 2.1
To get the board running, follow these steps. In some cases the board shipped from KONTRON has
premounted CPU (incl. KT690/mITX (BGA)), cooler and DDR2 DRAM. In this case step 1-3 can be skipped.
PSU) or leave the Power Connectors unconnected while configuring the board. Otherwise
components (RAM, LAN cards etc.) might get damaged.
Do not use PSU without 3.3V monitoring watchdog (standard feature in ATX PSU).
Running the board without 3.3V connected will damage the board after a few minutes.
Be careful not to sh ort circuit the lithium battery for instance b y placing the board upside down
1. Install the processor (KT690/mITX and KT690/mITX-FW only)
The CPU is keyed and w i ll only mount in the CPU sock et in one w a y. Use a 6mm flatheaded screwdr iver
to open/ close the CPU socket. The Mobile AMD Sempron™ and AMD Turion™ 64 X2 Mobile
Processors for S1 socket are supported, refer to supported processor overview for details.
locking mechanism
2. Cooler Installation (KT690/mITX and KT690/mITX-FW only)
Mount the cooler using the clip holders mounted on the board. Connect the Fan electric ally to the CPU
FAN connector.
3. Insert the DDR2 SODIMM 200pin DRAM module(s)
Push down the module from the top side until the tabs lock. For a list of approved DDR2 SODIMM modules
contact your Distributor or FAE.
DDR2 SODIMM 200pin DRAM modules (PC3200, PC4200, PC5300) are supported.
(continues)
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Warning: When mounting the board to chassis etc. please notice that the board contains
without reasonable care. A damaged component can result in malfunction or no function at all.
!
Note: To clear a ll C MO S se ttings , inc lu ding P ass wor d p rotect ion, m ove th e Clr-CMOS jumper (with or
minute, but be careful to orientate the battery correctly when reinserted.
4. Connecting Interfaces
Insert all external cables for hard disk, keyboard etc. A CRT monitor must be connected in order to
change CMOS settings to flat panel support.
5. Connect Power supply
Connect power su pply to the board by th e AT X/ BTXPWR and 4-pin ATX connectors. For board to operate
connection of both the ATX/BTX and 4-pin ATX (12V) connectors are required.
6. Turn on the power on the ATX/ BTX power supply
7. Power Button
The PWRBTN_IN must be toggled to start the Power supply; this is done by shorting pins 16
(PWRBTN_IN) and pin 18 (GND) on the FRONTPNL connector (see Connector description). A “normally
open” switch can be connected via the FRONTPNL connector.
8. BIOS Setup
Enter the BIO S s e tu p by pressing the <Del> key dur ing boot up. Refer t o t he “BIOS Configuration / Setup“
section of this manual for details on BIOS setup.
Enter Advanced Menu / CPU Configuration / Intel SpeedStep Tech. and set this option to “Maximum
Performance”.
without power) for a pproximately 1 minute. Alternatively turn of f power and remove the battery for 1
9. Mounting the board to chassis
When fixing the Motherboard on a chassis it is recommended using screws with integrated washer and
having diameter of ~7mm.
Note: Don’t use washers with teeth, as they can damage the PCB mounting hole resulting in short circuit.
components on both sides of the PCB which can easily be damaged if board is handled
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When an interface/connector has a VCC (or other power) pin, which is directly connected to a power
Requirement according to EN60950 2.2
Users of KT690 boards should take care when designing chassis interface connectors in order to fulfill the
EN60950 standard:
plane like the VCC plane:
To protect the external power lines of peripheral devices the customer has to take care about:
•That the wires have the right diameter to withstand the maximum available power.
•That the enclosure of the peripheral device fulfils the fire protecting requirements of IEC/EN 60950.
Lithium Battery precautions:
CAUTION!
Danger of explosion if battery is incorrectly
replaced.
Replace only with same or equivalent type
recommended by manufacturer.
Dispose of used batteries according
to the manufacturer’s instructions.
ADVARSEL!
Lithiumbatteri – Eksplosionsfare ved fejlagtig
håndtering.
Udskiftning må kun ske med batteri
af samme fabrikat og type.
Levér det brugte batteri tilbage til leverandøren.
VARNING
Explosionsfara vid felaktigt batteribyte.
Använd samma batterityp eller en ekvivalent
typ som rekommenderas av apparattillverkaren.
Kassera använt batteri enligt fabrikantens
instruktion.
VORSICHT!
Explosionsgefahr bei unsachgemäßem Austausch
der Batterie.
Ersatz nur durch den selben oder einen vom
Hersteller empfohlenen gleichwertigen Typ.
Entsorgung gebrauchter Ba tterie n nach
Angaben des Herstellers.
ADVARSEL
Eksplosjonsfare ved feilaktig skifte av batteri.
Benytt samme batteritype eller en tilsvarende
type anbefalt av apparatfabrikanten.
Brukte batterier kasseres i henhold til fabrikantens
instruksjoner.
VAROITUS
Paristo voi räjähtää, jos se on virheellisesti
asennettu.
Vaihda paristo ainoastaan laltevalmistajan
suosittelemaan
tyyppiin. Hävitä käytetty paristo valmistajan
ohjeiden
mukaisesti.
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Form factor
KT690/mITX, KT690/mITX-FW and KT690/mITX (BGA): mini ITX (170.18 x 170.18mm)
Processor
• Support for Mobile AMD Se mpron™, AMD Turion™ 64 and AMD Turion™ 64 X2
Memory
• Dual Channel DDR2 memory architecture
Chipset
AMD Chipset consisting of:
Video
• Integrated ATI Radeon™ X1200 graphics core
3. S ystem specification
Component main data 3.1
The table below summarises the features of the KT690/mITX, KT690/mITX-FW and KT690/mITX (BGA)
embedded motherboards.
Mobile Processors for S1 socket. (KT690/mITX and KT690/mITX-FW only).
o 35W maximum TDP
o 6.4GB/s HyperTransport™ link, 800 MHz, 16bit/16bit
o Hypertransport™ 1.0 Tunnel (I/O Bus) speed of 800MHz
o Internal L1 cache of 128KB (Single core CPUs) / 128KB x2 (Dual core CPUs)
o Internal L2 cache of 128/256/512KB (Single core CPUs) / 512KB x2 (Dual
core CPUs)
o Processor technology of 65nm / 90nm
•Support for AMD Sempron
o 15W maximum TDP
o Up to 6.4GB/s peak HyperTransport™ link, 800 MHz, 16bit/16bit
o Internal L1 data cache 64KB + L1 instruktion cache 64KB
o Internal L2 cache of 256KB
o Processor technology of 65nm
• Support for AMD Athlon
o 18W maximum TDP
o Up to 6.4GB/s peak HyperTransport™ link, 800 MHz, 16bit/16bit
o Internal L1 data cache 2x 64KB + L1 instruktion cache 2x 64KB
o Internal L2 cache of 2x 512KB
o Processor technology of 65nm
•DDR2 memory controller and bus interface
TM
BGA Single Core 210U (KT690/mITX (BGA) only).
TM
Neo X2 BGA Dual Core L325 KT690/mITX (BGA) only.
• 2 pcs DDR2 SODIMM 200pin DRAM sockets onboard.
• Support DDR 400/533/667MHz unbuffered memory (PC2-3200/PC2-4200/PC2-5300)
• Support system memory from 1x 256MB and up to 2 x16GB (PT only up to 2x4GB
has been verified).
• ECC not supported
• AMD M690T northbridge ( graphics tunnel)
• ATI SB600 southbridge (I/O hub)
o CRT Out connector
o DVI-D connector (Digital only)
o Onboard LVDS connector
o TV-Out connector (only configuration “KT690/mITX w TV out”)
o TV-Out pin connector (only configuration “KT690/mITX-FW w TV-out”)
Audio, 7.1 and 7.2 Channel High Definition Audio Codec using the Realtek ALC888 codec
I/O Control
Winbond W83627DHG LPC Bus I/O Controller
Peripheral
• Six USB 2.0 ports on I/O area
LAN
• 2x 10/100/1000Mbits/s LAN using
BIOS
• Kontron Technology / AMI BIOS (core version 8.00)
Expansion
• PCI Bus routed to PCI slot(s) (PCI Local Bus Specification Revision 2.3)
Hardware
• Smart Fan control system, support Thermal® and Speed® cruise for three onboard
• Line-out and Line-in
• Surround output: SIDE, LFE, CEN, BACK and FRONT
• Microphone: MIC1, MIC2
• CDROM in
• SPDIF Interface
Onboard speaker
interfaces
Support
• Four USB 2.0 ports on internal pinrows
• Two Serial ports (RS232)
• One Parallel port, SPP/EPP/ECP
• One Floppy port
• Four Serial ATA-300 IDE AHCI interfaces
• One PATA 66/100/133 interface with support for 2 devices
• CF (Compact Flash) interface (KT690/mITX only) supporting CF type I and II.
(UDMA2 max.). Note that only one PATA device is supported when CF is used and
only by use of 40-wire cable (not 80-wire cable). Optionally use SATA devices.
All Peripheral interfaces intended for connection to external equipment are ESD/ EMI
protected.
EN 61000-4-2:2000 ESD Immunity
EN55022:1998 class B Generic Emission Standard.
Safety:
UL 60950-1:2003, First Edition
CSA C22.2 No. 60950-1-03 1st Ed. April 1, 2003
Product Category: Information Technology Equipment Including Electrical Business
Equipment
Product Category CCN: NWGQ2, NWGQ8
File number: E194252
Theoretical MTBF:
234,251 hours or 26.7 years @ 40ºC ambient air temperature
135,169 hours or 15.4 years @ 60 ºC ambient air temperature
Restriction of Hazardeous Substances (RoHS):
All boards in the KT690 family are RoHS compliant.
Capacitor utilization:
No Tantal capacitors on board
Only Japanese brand Aluminium and solid electrolytic capacitors rated for 100ºC used
on board
Exchangeable 3.0V Lithium battery for onboard Real Time Clock and CMOS RAM.
Manufacturer Panasonic / Part-number CR2032NL/LE, CR-2032L/BE or CR-2032L/BN
Expected minimum 5 years retention varies depending on temperature, actual
application on/off rate and variation within chipset and other components.
Approximately current draw is 3µA (no PSU connected).
CAUTION: Danger of explosion if the battery is incorrectly replaced. Replace
only with the same or equivalent type recommended by the manufacturer.
Dispose of used batteries according to th e manufacturer’s instructions.
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CF
socket
IEEE-
1394
TVOut
KT690/mITX EOL
+ - -
Realtek RTL8111B
- - KT690/mITX w TV-out EOL
+ - +
Realtek RTL8111B
- - KT690/mITX-FW w TV-out EOL
-
x 2
+ (*)
Realtek RTL8111B
- - KT690/mITX (BGA) 210U
+ - -
Intel 82574L
210U
PN 1037-0921
KT690/mITX (BGA) L325
+ - -
Intel 82574L
L325
PN 1037-0921
KT690 System overview 3.2
The block diagram below shows the architecture and main components of the KT690 boards.
(See available configurations below)
(See available configurations below)
Available configurations are :
KT690 configuration
* = pin header
LAN CPU Cooler
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Clock
[MHz]
Thermal
[Watt]
Mobile AMD
Sempron™
Mobile AMD
Sempron™
Mobile AMD
Sempron™
Mobile AMD
Sempron™
Mobile AMD
Sempron™
Mobile AMD
Sempron™
AMD Turion™ 64 X2
Mobile Technology
AMD Turion™ 64 X2
Mobile Technology
AMD Turion™ 64 X2
Mobile Technology
AMD Turion™ 64 X2
Mobile Technology
AMD Turion™ 64 X2
Mobile Technology
AMD Turion™ 64 X2
Mobile Technology
AMD Turion™ 64 X2
Mobile Technology
AMD Turion™ 64 X2
Mobile Technology
Clock
[MHz]
Thermal
[Watt]
AMD AthlonTM Neo X2
L325
1500 2 18W
Yes
Processor support table. 3.3
The KT690/mITX and KT690/mITX-FW is designed to support the following socket S1 processors:
Processor Brand Model
2100+ 1000 1 8W Yes SMF2100HAX3DQE
3500+ 1800 1 25W Yes SMS3500HAX4CME
3600+ 2000 1 25W No SMS3600HAX3DN
3700+ 2000 1 25W Yes SMS3700HAX4DQE
3800+ 2200 1 31W No SMD3800HAX3CM
4000+ 2200 1 31W No SMD4000HAX4DN
TL52 1600 2 35W Yes TMDTL52HAX5CTE
TL56 1800 2 35W Yes TMDTL56HAX5DME
TL58 1900 2 31W No TMDTL58HAX5DC
TL60 2000 2 31W No TMDTL60HAX5DC
Speed
Cores
Guideline
Embedded Order Number
TL62 2100 2 35W Yes TMDTL62HAX5DME
TL64 2200 2 35W No TMDTL64HAX5DC
TL66 2300 2 35W No TMDTL66HAX5DM
TL68 2400 2 35W No TMDTL68HAX5DM
The KT690/mITX (BGA) is available with pre-mounted processors of the following types:
Processor Brand Model
AMD SempronTM 210U 1500 1 15W Yes
Speed
Cores
Guideline
Embedded
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Mode
DDR2 SLOT 1
DDR2 SLOT 2
System Memory 3.4
The motherboard provides two 200-pin DDR2 Small Outline Dual Inline Memory Module (SO-DIMM) sockets.
Each slot can be populated with up to 16 GB of unbuffered DDR2 SO-DIMM modules resulting in a
maximum of 32 GB system memory. (PT only up to 2x 4GB has been verified). Memory speeds up to DDR2667 (PC2-5300) are supported.
3.4.1 Memory Configuration
Dual Channel configuration (128 bit) is enabled by populating both memory channels (DDR2 SLOT 1 and
DDR2 SLOT 1). Populating only one memory slot results in 64-bit Single Channel m ode.
Single Channel (64 bit)
Dual Channel (128 bit)
Populated -
- Populated
Populated Populated
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KT690 Fan / Heatsinks 3.5
PN 1022-1521 - Passive S1 cooler 35mm
Supports 210U CPU with up to 55ºC ambient.
PN 1043-2893 Cooler Passive BGA AMD S1 35mm
Supports CPUs with Thermal Design Power (TDP) up to 9W @ 60ºC ambient.
Customer must ensure proper airflow in system
PN 823139 - AMD S1 cooler and
PN 1037-0921 Cooler A ctive BGA AMD S1 35mm
Supports CPUs with Thermal Design Power (TDP) up to:
30W @ 60ºC am bient and
35W @ 50ºC ambient.
Customer must ensure proper airflow in system.
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KT690 Power State Map 3.6
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Supply
Min
Max
Note
Vcc3
3.14V
3.46V
Should be ±5% for compliance with the ATX specification
Vcc
4.75V
5.25V
Should be ±5% for compliance with the ATX specification
+12V
11.4V
12.6V
Should be ±5% for compliance with the ATX specification
–12V
–13.2V
–10.8V
Should be ±10% for compliance with the ATX specification
-5V
-5,50V
-4.5V
Not required for the KT690/mITX board
5VSB
4.75V
–5.25V
Should be ±5% for compliance with the ATX specification
ATX supplies
KT690/mITX
PSU
Gnd
Current
Probe
Tektronix TDS 7404
Power Consumption 3.7
In order to ensure safe operation of the board, the ATX power supply must monitor the supply voltage and
shut down if the supplies are out of range – refer to the hardware manual for actual power specification.
The KT690/mITX and KT690/mITX-FW board is powered through the ATX connector and the additional 12V
separate supply for CPU as specified in the ATX specification; besides this the power supplied to the board
must be within the ATX specification.
The requirements to the supply voltages are as follows:
Static Power Consumption
The power consumption of the KT690/mITX and KT690/mITX-FW Board is measured under:
1- WindowsXP, Running 3DMARK & CPU BURN , mean
2- WindowsXP, Running 3DMARK & CPU BURN , peak
3- S1, mean
4- S3, mean
5- Inrush, peak
Test setup
The following items were used in the test setup:
1. KT690/mITX board
2. 12V active cooler
3. PS/2 keyboard & mouse, CRT, HD, ATX PSU
4. Tektronix TDS 7404, P6345 probes
5. Fluke Current Probe 80i-10 0S AC /D C
Note: The Power consumption of CRT, HD and Fan is not included.
KT690/mITX BGA w/ Single Core 1.5GHz 210U + 2x2GB DDR2
Windows XP, 3DMARK2001 & CPUBURN, mean
Windows XP, 3DMARK2001 & CPUBURN, peak
S1, mean
S3, mean
S5, mean
Inrush, peak
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KT690 Clock Distribution 3.8
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name
4. Connector Definitions
The following sections provide pin definitions and detailed description of all on-board connectors.
The connector definitions follow the following notation:
Column
Pin Shows the pin-numbers in the connector. The graphical layout of the connector definition
Signal The mnemonic name of the signal at the current pin. The notation “XX#” states that the signal
Type AI: Analog Input.
Ioh: Typical current in mA flowing out of an output pin through a grounded load, while the
Pull U/D On-board pull-up or pull-down resistors on input pins or open-collector output pins.
Note Special remarks concerning the signal.
The abbreviation TBD is used for specifications which are not available yet or which are not sufficiently
specified by the component vendors.
Description
tables is made similar to the physical connectors.
“XX” is active low.
AO: Analog Output.
I: Input, TTL compatible if nothing else stated.
IO: Input / Output. TTL compatible if nothing else stated.
IOT: Bi-directional tristate IO pin.
IS: Schmitt-trigger input, TTL compatible.
IOC: Input / open-collector Output, TTL compatible.
NC: Pin not connected.
O: Output, TTL compatible.
OC: Output, open-collector or open-drain, TTL compatible.
OT: Output with tri-state capability, TTL compatible.
LVDS: Low Voltage Differential Signal.
PWR: Power supply or ground reference pins.
output voltage is > 2.4 V DC (if nothing else stated).
Iol: Typical current in mA flowing into an output pin from a VCC connected load, while the
output voltage is < 0.4 V DC (if nothing else stated).
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CRT
DVI-D
MSE
KBD
AUDIO
STACK
ETHER2
USB5
CDROM
USB2
USB0
ETHER1
USB8
SATA1 SATA3
SATA0 SATA2
ATX/ BTXPWR
Clr-CMOS
PCI Slot 1
PCIe x8
FAN_SYS
KBDMSE
FRONTPNL
AUDIO
HEAD
FLOPPY
DDR2 SLOT 2
DDR2 SLOT 1
FAN_CPU
ATX+12V
COM1
TPM
LVDS
BTN
RESET
TV-OUT*
PATA
FEATURE
COM2
PRINTER
USB6
USB7
COMPACT FLASH
Connector layout 4.1
4.1.1 KT690/mITX
Topside, KT690/mITX:
* Mounted optionally
Front, KT690/mITX
KT690 Family
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AUDIO
STACK
ETHER2
USB5
ETHER1
USB8
TV-OUT*
CRT
DVI-D
MSE
KBD
USB2
USB0
Mini-PCI
Backside, KT690/mITX:
KT690 Family
USB4
USB9
* Mounted optionally
express
slot
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CRT
DVI-D
MSE
KBD
AUDIO
STACK
ETHER2
USB5
USB2
USB0
ETHER1
USB8
SATA1 SATA3
SATA0 SATA2
ATX/ BTXPWR
Clr-CMOS
PCI Slot 1
PCIe x8
FAN_SYS
KBDMSE
FRONTPNL
AUDIO
HEAD
FLOPPY
DDR2 SLOT 2
DDR2 SLOT 1
FAN_CPU
ATX+12V
COM1
TPM
LVDS
BTN
RESET
TV-OUT
PATA
FEATURE
COM2
PRINTER
USB6
USB7
IEEE1394_1
IEEE1394_2
CDROM
4.1.2 KT690/mITX-FW
Topside, KT690/mITX-FW:
KT690 Family
USB4
USB9
KTD-00738-J
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Date 2012-06-01
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TPM
PRINTER
CRT
DVI-D
MSE
KBD
AUDIO
STACK
ETHER2
USB5
USB2
USB0
ETHER1
USB8
SATA1 SATA3
SATA0 SATA2
ATX/ BTXPWR
Clr-CMOS
PCI Slot 1
PCIe x8
FAN_SYS
KBDMSE
FRONTPNL
AUDIO
HEAD
FLOPPY
DDR2 SLOT 2
DDR2 SLOT 1
FAN_CPU
ATX+12V
COM1
LVDS
BTN
RESET
TV-OUT
PATA
FEATURE
COM2
USB6
USB7
CF socket
CDROM
4.1.3 KT690/mITX (BGA)
Topside, KT690/mITX (BGA):
4.2
KT690 Family
USB4
USB9
KT690 Family
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Date 2012-06-01
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30
Note
Pull
U/D
Ioh/Iol
Type
Signal
PIN
Signal
Type
Ioh/Iol
Pull
U/D
Note
- -
PWR
3V3
12
24
GND
PWR - -
PWR
+12V
11
23
5V
PWR
PWR
+12V
10
22
5V
PWR
- -
PWR
SB5V
9
21
5V
PWR - - - - I P_OK
8
20
-5V
PWR - - 1 - -
PWR
GND
7
19
GND
PWR - - - -
PWR
5V
6
18
GND
PWR - - - -
PWR
GND
5
17
GND
PWR - - - -
PWR
5V
4
16
PSON#
OC - - - -
PWR
GND
3
15
GND
PWR - - - -
PWR
3V3
2
14
-12V
PWR - - - -
PWR
3V3
1
13
3V3
PWR - -
Note
Pull
U/D
Ioh/Iol
Type
Signal
PIN
Signal
Type
Ioh/Iol
Pull
U/D
Note
1 - -
PWR
GND
1 3 +12V
PWR - -
1
1
PWR
GND
2 4 +12V
PWR
1
Signal
Description
P_OK is a power good signal and should be asserted high by the power supply to indicate
Power Connector (ATXPWR)
The KT690 boards are designed to be supplied from a standard ATX or BTX power supply.
ATX/ BTX Power Connector:
Note 1: -5V supply is not used onboard.
Note 2: Use of BTX supply not required for operation, but may be required to drive high-power PCI Express
x16 Add cards.
ATX+12V Power Connector:
Note 1: Use of the 4-pin ATX+12V Power Connector is required for operation of the KT690 boards.
See chapter “Power Consumption” regarding input tolerances on 3.3V, 5V, SB5V, +12 and -12V (also refer
to ATX specification version 2.2).
Control signal description:
P_OK
that the +5VDC and +3.3VDC outputs are above the undervoltage thresholds of the power
supply. When this signal is asserted high, there should be sufficient energy stored by the
converter to guarantee continuous power operation within specification. Conversely, when the
output voltages fall below the undervoltage threshold, or when mains power has been
removed for a time sufficiently long so that power supply operation is no longer guaranteed,
P_OK should be de-asserted to a low state. The recommended electrical and timing
characteristics of the P_OK (PWR_OK) signal are provided in the ATX1 2V Power SupplyDesign Guide.
It is strongly recommended to use an ATX or BTX supply with the KT690 boards, in order to
implement the supervision of the 5V and 3V3 supplies. These supplies are not supervised
onboard the KT690 boards.
PS_ON# Active low open drain signal from the board to the power supply to turn on the power supply
outputs. Signal must be pulled high by the power supply.
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Note
Pull
U/D Ioh/Iol
Type
Signal
PIN
Signal
Type
Ioh/Iol
Pull
U/D Note - - - NC
6 5
MSCLK
IOC
TBD
2K7 - - PWR
5V/SB5V
4 3
GND
PWR - - - - - NC
2 1
MSDAT
IOC
TBD
2K7 - NC
6 5
KBDCLK
IOC
TBD
2K7 - - PWR
5V/SB5V
4 3
GND
PWR - - - - - NC
2 1
KBDDAT
IOC
TBD
2K7
Signal
Type
Ioh/Iol
Pull
U/D
Note
1
KBDCLK
IOC
TBD
4K7
2 KBDDAT
IOC
TBD
4K7
3 MSCLK
IOC
TBD
4K7
4
MSDAT
IOC
TBD
4K7
5 5V/SB5V
PWR - - 6
GND
PWR - -
MSDAT
Bi-directional serial data line used to transfer data from or commands to the PS/2 mouse.
Keyboard and PS/2 mouse connectors 4.3
Attachment of a keyboard or PS/2 mouse adapter can be done through the stacked PS/2 mouse and
keyboard connector (MSE & KBD).
Both interfaces utilize open-drain signaling with on-board pull-up.
The PS/2 mouse and keyboard is supplied from SB5V when in standby mode in order to enable keyboard or
mouse activity to bring the system out from power saving states. The supply is provided through a 1.1A
resetable fuse.
4.3.1 Stacked MINI-DIN keyboard and mouse Connector (MSE & KBD)
Signal Description – Keyboard & and mouse Connector (MSE & KBD), see below.
4.3.2 Keyboard and mouse pin-row Connector (KBDMSE)
PIN
Signal Description – Keyboard & and mouse Connector (KBDMSE).
Signal Description
MSCLK Bi-directional clock signal used to strobe data/commands from/to the PS/2 mouse.
KDBCLK Bi-directional clock signal used to strobe data/commands from/to the PC-AT keyboard.
KBDDAT Bi-directional serial data line used to transfer data from or commands to the PC-AT keyboard.
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Display Connectors 4.4
The KT690 board provides:
1. Analog CRT interface (IO Bracket)
2. Digital DVI (DVI-D) (IO Bracket)
3. LVDS connector (internal connector)
4. TV-Out (IO Bracket) (“KT690/mITX w. TV-out” only)
5. TV-Out (Internal pin header) (“KT690/mITX-FW w. TV-out” only)
The KT690 board does not support ADD2 / SDVO cards on the PCI Express x16 connector.
The KT690 integrates the ATI Radeon™ X1250 Graphics Core with support for Dual Clone display and Dual
independent display.
The supported combinations are listed in the below matrix:
DDCCLK Display Data Channel Clock. Used as clock signal to/from monitors with DDC interface.
DDCDAT Display Data Channel Data. Used as data signal to/from monitors with DDC interface.
RED Analog output carrying the red color signal to the CRT. For 75 Ohm cable impedance.
GREEN Analog output carrying the green color signal to the CRT. For 75 Ohm cable impedance.
BLUE Analog output carrying the blue color signal to the CRT. For 75 Ohm cable impedance.
DIG-GND Ground reference for HSYNC and VSYNC.
ANA-GND Ground reference for RED, GREEN, and BLUE.
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Pin No.
Signal
Description
Type
Pull Up
4.4.2 DVI Connector (DVI-D, digital only)
Female socket, front view
Note: DVI analogue signals are not supported
Signal Description - DVI Connector:
1 TMDS Data 2- Digital Red – (Link 1) LVDS OUT
2 TMDS Data 2+ Digital Red + (Link 1) LVDS OUT
3 TMDS Data 2/4 Shield PWR
4 N.C. -
5 N.C. -
6 DDC Clock DDC Clock IO 2K2
7 DDC Data DDC Data IO 2K2
8 N.C. -
9 TMDS Data 1- Digital Green – (Link 1) LVDS OUT
10 TMDS Data 1+ Digital Green + (Link 1) LVDS OUT
11 TMDS Data 1/3 Shield PWR
12 N.C. -
13 N.C. -
14 +5V (55mA) Power for monitor when in standby PWR
15 GND PWR
16 Hot Plug Detect Hot Plug Detect I
17 TMDS Data 0- Digital Blue – (Link 1) / Digital sync LVDS OUT
18 TMDS Data 0+ Digital Blue + (Link 1) / Digital sync LVDS OUT
19 TMDS Data 0/5 Shield PWR
20 N.C. -
21 N.C. -
22 TMDS Clock Shield PWR
23 TMDS Clock+ Digital clock + (Link 1) LVDS OUT
24 TMDS Clock- Digital clock - (Link 1) LVDS OUT
C1 - C5 N.C. -
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Note
Type
Signal
Pin
Signal
Type
Note
Max. 0.5A
PWR
+12V
1 2 +12V
PWR
Max. 0.5A
Max. 0.5A
PWR
+12V
3 4 +12V
PWR
Max. 0.5A
Max. 0.5A
PWR
+12V
5
6
GND
PWR
Max. 0.5A
Max. 0.5A
PWR
+5V
7
8
GND
PWR
Max. 0.5A
Max. 0.5A
PWR
LCDVCC
9
10
LCDVCC
PWR
Max. 0.5A
2K2Ω, 3.3V
OT
DDC CLK
11
12
DDC DATA
OT
2K2Ω, 3.3V
3.3V level
OT
BKLTCTL
13
14
VDD ENABLE
OT
3.3V level
3.3V level
OT
BKLTEN#
15
16
GND
PWR
Max. 0.5A
LVDS
LVDS A0-
17
18
LVDS A0+
LVDS
LVDS
LVDS A1-
19
20
LVDS A1+
LVDS
LVDS
LVDS A2-
21
22
LVDS A2+
LVDS
LVDS
LVDS ACLK-
23
24
LVDS ACLK+
LVDS
LVDS
LVDS A3-
25
26
LVDS A3+
LVDS
Max. 0.5A
PWR
GND
27
28
GND
PWR
Max. 0.5A
LVDS
LVDS B0-
29
30
LVDS B0+
LVDS
LVDS
LVDS B1-
31
32
LVDS B1+
LVDS
LVDS
LVDS B2-
33
34
LVDS B2+
LVDS
LVDS
LVDS BCLK-
35
36
LVDS BCLK+
LVDS
LVDS
LVDS B3-
37
38
LVDS B3+
LVDS
Max. 0.5A
PWR
GND
39
40
GND
PWR
Max. 0.5A
4.4.3 LVDS Flat Panel Connector (LVDS)
Note 1: The KT690 board support dual channel, 24bit OpenLDI/ SPWG panels on the LVDS interface
Signal Description – LVDS Flat Panel Con nect or:
Signal Description
LVDS A0..A3 LVDS A Channel data
LVDS ACLK LVDS A Channel clock
LVDS B0..B3 LVDS B Channel data
LVDS BCLK LVDS B Channel clock
BKLTCTL Backlight control (1), PWM signal to implement voltage in the range 0-3.3V
BKLTEN#Backlight Enable signal (active low) (2)
VDD ENABLE Output Display Enable.
LCDVCC VCC supply to the flat panel. This supply includes power-on/off sequencing.
The flat panel supply may be either 5V DC or 3.3V DC depending on the CMOS
configuration. Maximum load is 1A at both voltag es.
DDC CLK DDC Channel Clock
DDC DATA DDC Channel Data
Note 1) Windows API will be available to operate the BKLTCTL signal. Some Inverters has a limited voltage
range 0- 2.5V for this signal: If voltage is > 2.5V the Inverter might latch up. Some Inverters
generates noise to the BKLTCTL signal resulting in making the lvds transmision fail (corrupted
picture on the display). By adding 1K Ohm resistor in series with this signal and mounted in the
Inverter end of the cable kit the noise is limited and picture is stabil.
Note 2) If the Backlight Enable is required to be active high then make the BIOS Chipset setting: Backlight
Signal Inversion = Ena ble d.
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Note
Pull
U/D Ioh/Iol
Type
Signal
Signal
Type
Ioh/Iol
Pull
U/D Note
GND
TVDACC
4 7 3
TVDACB
GND
2 6 5 1 GND
GND
TVDACA
Signal
Description
Note
Pull
U/D
Ioh/Iol
Type Signal
Signal
Type
Ioh/Iol
Pull
U/D
Note
TVDACC
1 2 TVDACB
SMBC
3 4 TVDACA
SMBD
5 6 -12V
+5V
7 8 +12V
GND
9
10
GND
4.4.4 TV-Out (Optional)
The KT690/mITX boards include TV-Out connector with support for Component, S-Video and Composite
Output interfaces and NTSC/ PAL output format.
The KT690 board includes Macrovision support.
IMPORTANT: If the TV-Out option is available then you must make agreement with Macrovision
(http://www.macrovision.com/
licence fee which depends on the application.
KT690/mITX TV-Out connector:
) about licence fee. Only Macrovision (not Kontron) can determine the actual
PIN
TVDACA TVDAC Channel A output supports:
Composite: CVBS signal
Component: Chrominance (Pb) analog signal
TVDACB TVDAC Channel B output supports:
S-Video: Luminance analog signal
Component: Luminance (Y) analog signal
TVDACC TVDAC Channel C output supports:
S-Video: Chrominance analog signal
Component: Chrominance (Pr) analog signal
KT690/mITX-FW TV-Out connector:
PIN
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Date 2012-06-01
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Note
Type
Signal
PIN
Signal
Type
Note
+12V
B1
A1
NC
+12V
B2
A2
+12V
+12V
B3
A3
+12V
GND
B4
A4
GND
SMB_CLK
B5
A5
NC
SMB_DATA
B6
A6
NC
GND
B7
A7
NC
+3V3
B8
A8
NC
NC
B9
A9
+3V3
SB3V3
B10
A10
+3V3
WAKE#
B11
A11
RST#
NC
B12
A12
GND
GND
B13
A13
PCIE_x16 CLK
PEG_TXP[0]
B14
A14
PCIE_x16 CLK#
PEG_TXN[0]
B15
A15
GND
GND
B16
A16
PEG_RXP[0]
I2C_CLK
B17
A17
PEG_RXN[0]
GND
B18
A18
GND
PEG_TXP[1]
B19
A19
NC
PEG_TXN[1]
B20
A20
GND
GND
B21
A21
PEG_RXP[1]
GND
B22
A22
PEG_RXN[1]
PEG_TXP[2]
B23
A23
GND
PEG_TXN[2]
B24
A24
GND
GND
B25
A25
PEG_RXP[2]
GND
B26
A26
PEG_RXN[2]
PEG_TXP[3]
B27
A27
GND
PEG_TXN[3]
B28
A28
GND
GND
B29
A29
PEG_RXP[3]
NC
B30
A30
PEG_RXN[3]
DDC_DATA
B31
A31
GND
GND
B32
A32
NC
PEG_TXP[4]
B33
A33
NC
PEG_TXN[4]
B34
A34
GND
GND
B35
A35
PEG_RXP[4]
GND
B36
A36
PEG_RXN[4]
PEG_TXP[5]
B37
A37
GND
PEG_TXN[5]
B38
A38
GND
GND
B39
A39
PEG_RXP[5]
GND
B40
A40
PEG_RXN[5]
PEG_TXP[6]
B41
A41
GND
PEG_TXN[6]
B42
A42
GND
GND
B43
A43
PEG_RXP[6]
GND
B44
A44
PEG_RXN[6]
PEG_TXP[7]
B45
A45
GND
PEG_TXN[7]
B46
A46
GND
GND
B47
A47
PEG_RXP[7]
PCI-Express Connectors 4.5
The KT690 board contains one 8-lane (x8) PCI Express port on a PCI Express x16 connector . The PCI
Express port is compliant to the PCI Express Specification revision 1.1a.
The x8 port operates at a frequency of 2.5 Gb/s on each lane; the port supports a maximum theoretical
bandwidth of 20 Gb/s in each direction.
The 8-lane (x8) PCI Express port supports:
1. An external graphics device utilizing all 8 lanes
2. A single x1, x2 or x4 general purpose PCI Express link
The PCI Express port does not support SDVO and ADD2 cards.
4.5.1 PCI-Express x8
The KT690 boards supports one 8-lane (x8) PCI Express port for external PCI Express based graphics
boards.
(continues)
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PRSNT#2
B48
A48
PEG_RXN[7]
GND
B49
A49
GND
NC
B50
A50
NC
NC
B51
A51
GND
GND
B52
A52
NC
GND
B53
A53
NC
NC
B54
A54
GND
NC
B55
A55
GND
GND
B56
A56
NC
GND
B57
A57
NC
NC
B58
A58
GND
NC
B59
A59
GND
GND
B60
A60
NC
GND
B61
A61
NC
NC
B62
A62
GND
NC
B63
A63
GND
GND
B64
A64
NC
GND
B65
A65
NC
NC
B66
A66
GND
NC
B67
A67
GND
GND
B68
A68
NC
GND
B69
A69
NC
NC
B70
A70
GND
NC
B71
A71
GND
GND
B72
A72
NC
GND
B73
A73
NC
NC
B74
A74
GND
NC
B75
A75
GND
GND
B76
A76
NC
GND
B77
A77
NC
NC
B78
A78
GND
NC
B79
A79
GND
GND
B80
A80
NC
NC
B81
A81
NC
NC
B82
A82
GND
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Note
Type
Signal
PIN
Signal
Type
Note
WAKE#
1
2
+3V3
NC
3
4
GND
NC
5
6
+1.5V
NC
7
8
NC
GND
9
10
NC
PCIE_mini CLK#
11
12
NC
PCIE_mini CLK
13
14
NC
GND
15
16
NC
NC
17
18
GND
NC
19
20
W_Disable
GND
21
22
RST#
PCIE_RXN
23
24
+3V3
PCIE_RXP
25
26
GND
GND
27
28
+1.5V
GND
29
30
SMB_CLK
PCIE_TXN
31
32
SMB_DATA
PCIE_TXP
33
34
GND
GND
35
36
NC
NC
37
38
NC
NC
39
40
GND
NC
41
42
NC
NC
43
44
NC
NC
45
46
NC
NC
47
48
+1.5V
NC
49
50
GND
NC
51
52
+3V3
4.5.2 miniPCI-Express connector
The KT690 board supports one miniPCI Express port compliant to the Mini PCI
Specification, Revision 1.0.
This allows for implementation for small form factor PCI cards also referred to as Mini PCI Cards.
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Parallel ATA harddisk interface 4.6
One parallel ATA harddisk controllers is available on the board – a primary controller. Standard 3½”
harddisks or CD-ROM drives may be attached to the primary controller by means of the 40 pin IDC
connector, PATA.
The parallel ATA harddisk controller is shared between the PATA connector and the CF connector.
If the CF connector is not used then two devices (a primary and a secondary device) are supported on the
PATA interface.
The harddisk controllers support Bus master IDE, ultra DMA 33/66/100/133 MHz and standard operation
modes. For support of ultra DMA 66/100/133 MHz, a 80-wire cable is required.
If the CF connector is used then only one PATA device is supported and only by use of 40-wire cable (not
80-wire cable). Optionally use SATA device(s).
The signals used for the harddisk interface are the following:
Signal Description
DAA2..0 Address lines, used to address the I/O registers in the IDE hard disk.
HDCSA1..0# Hard Disk Chip-Select. HDCS0# selects the primary hard disk.
DA15..8 High part of data bus.
DA7..0 Low part of data bus.
IORA# I/O Read.
IOWA# I/O Write.
IORDYA# This signal may be driven by the hard disk to extend the current I/O cycle.
RESETA# Reset signal to the hard disk.
HDIRQA Interrupt line from hard disk.
CBLIDA This input signal (CaBLe ID) is used to detect the type of attached cable: 80-wire cable
when low input and 40-wire cable when 5V via 10Kohm (pull-up resistor).
DDREQA Disk DMA Request might be driven by the IDE hard disk to request bus master access to
the PCI bus. The signal is used in conjunction with the PCI bus master IDE function and is
not associated with any PC-AT bus compatible DMA channel.
DDACKA# Disk DMA Acknowledge. Active low signal grants IDE bus master access to the PCI bus.
HDACTA# Signal from hard disk indicating hard disk activity. The signal level depends on the hard
disk type, normally active low. The signals from primary and secondary controller are
routed together through diodes and passed to the connector FEATURE.
All of the above signals are compliant to [4].
The pinout of the connectors are defined in the following sections.
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Pull
U/D
Pull
U/D
- TBD
O
RESET_P#
1 2 GND
PWR - - - TBD
IO
DA7
3 4 DA8
IO
TBD - -
TBD
IO
DA6
5 6 DA9
IO
TBD - -
TBD
IO
DA5
7 8 DA10
IO
TBD - -
TBD
IO
DA4
9
10
DA11
IO
TBD -
- TBD
IO
DA3
11
12
DA12
IO
TBD - -
TBD
IO
DA2
13
14
DA13
IO
TBD -
- TBD
IO
DA1
15
16
DA14
IO
TBD - -
TBD
IO
DA0
17
18
DA15
IO
TBD - - - PWR
GND
19
20
KEY
- - - - - I DDRQA
21
22
GND
PWR - - - TBD O IOWA#
23
24
GND
PWR - - - TBD O IORA#
25
26
GND
PWR - -
4K7 - I
IORDYA
27
28
GND
PWR - - - - O DDACKA#
29
30
GND
PWR - -
10K - I
HDIRQA
31
32
NC
- - - - TBD O DAA1
33
34
CBLIDA#
I - - TBD O DAA0
35
36
DAA2
O
TBD -
- TBD
O
HDCSA0#
37
38
HDCSA1#
O
TBD - - - I
HDACTA#
39
40
GND
PWR - -
4.6.1 IDE Hard Disk Connector (PATA)
This connector can be used for connection of two primary IDE drives.
Note
Ioh/Iol Type Signal PIN Signal Type Ioh/Iol
Note
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Note
Pull
U/D
Ioh/Iol
Type Signal
Signal
Type
Ioh/Iol
Pull
U/D Note
2 - - - NC
26 1 GND
PWR - -
1
- TBD
IO
DA11
27 2 DB3
IO
TBD - -
TBD
IO
DA12
28 3 DB4
IO
TBD -
- TBD
IO
DA13
29 4 DB5
IO
TBD - -
TBD
IO
DA14
30 5 DB6
IO
TBD - -
TBD
IO
DA15
31 6 DB7
IO
TBD - -
TBD
O
HDCSA1#
32 7 HDCSA0#
O
TBD - - - -
NC
33 8 GND
PWR - - - TBD O IORA#
34 9 GND
PWR - - - TBD O IOWA#
35
10
GND
PWR - - - -
PWR
5V
36
11
GND
PWR - -
8K2 - I
HDIRQA
37
12
GND
PWR - - - -
PWR
5V
38
13
5V
PWR - - - -
PWR
GND
39
14
GND
PWR - -
- - - NC
40
15
GND
PWR - - - TBD
O
RESET_C#
41
16
GND
PWR - -
4K7 - I
IORDYA
42
17
GND
PWR - -
- - I DDRQA
43
18
DAA2
O - - - - O DDACKA#
44
19
DAA1
O - - - - I HDACTA#
45
20
DAA0
O - - - - I CBLIDA#
46
21
DB0
IO
TBD - -
TBD
IO
DB8
47
22
DB1
IO
TBD - -
TBD
IO
DB9
48
23
DB2
IO
TBD - -
TBD
IO
DB10
49
24
NC 1 - - PWR
GND
50
25
NC - - - 2
4.6.2 CF Connector (CF)
This connector is mounted on the topside of the KT690/mITX (CF is not available on KT690/mITX-FW).
The CF socket support DMA/UDMA modules up to UDMA2.
NOTE: If the CF connector is used then only one PATA device is supported and only by use of 40-wire cable
(not 80-wire cable). Optionally use SATA device(s). Normally CF is Master and then possible PATA device
must be Slave.
PIN
Note 1: Pin is longer than average length of the other pins.
Note 2: Pin is shorter than average length of the other pins.
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Signal
Type
Ioh/Iol
Pull
U/D
Note
Key 1
GND
PWR - - 2
SATA* TX+
3
SATA* TX-
4
GND
PWR - - 5
SATA* RX-
6
SATA* RX+
7
GND
PWR - -
Signal
Description
Host receiver differential signal pair
Serial ATA harddisk interface 4.7
The KT690 boards have an integrated SATA Host controller that supports independent operation on four
ports and data transfer rates of up to 3.0Gb/s (300MB/s). The SATA controller supports AHCI mode and has
integrated RAID functionality with support for RAID modes 0, 1 and 10.
The board provides four Serial ATA (SATA) connectors, which support one device per connector.
The SB600 Southbridge Serial ATA controller offers four independent Seri al AT A ports with a theoretical
maximum transfer rate of 3 Gbits/sec per port.
A point-to-point interface is used for host to device connections, unlike Parallel ATA IDE which supports a
master/slave configuration and two devices per channel.
For compatibility, the underlying Serial ATA functionality is transparent to the operating system. The Serial
ATA controller can operate in both legacy and native modes. In legacy mode, standard IDE I/O and IRQ
resources are assigned (IRQ 14 and 15). In Native mode, standard PCI Conventional bus resource steering
is used. Native mode is the preferred mode for configurations using the Windows XP and Windows 2000
operating systems.
The KT690 supports the following RAID (Redundant Array of Independent Drives) levels:
• RAID 0 - data striping
• RAID 1 - data mirroring
• RAID 0+1 (or RAID 10) - data striping and mirroring
Limitations depending on Target Operating System apply.
4.7.1 SATA Hard Disk Connector (SATA0, SATA1, SATA2, SATA3)
SATA:
PIN
The signals used for the primary Serial ATA harddisk interface are the following:
SATA* RX+
SATA* RX-
SATA* TX+
SATA* TX-
“*” specifies 0, 1, 2, and 3 depe nd ing on SAT A por t.
All of the above signals are compliant to [4].
Host transmitter differential signal pair
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Note
Pull
U/D
Ioh/Iol
Type Signal
Signal
Type
Ioh/Iol
Pull
U/D
Note
TPA1+
1 2 TPA1-
GND
3 4 GND
TPB1+
5 6 TPB1-
1 +12V
7 8 +12V
1 KEY
9
10
GND
Signal
Description
Differential signal pair A
Firewire/ IEEE-1394 connectors. 4.8
The KT690/mITX-FW board supports two IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s,
200Mbits/s, and 400M bits/s .
Note: Firewire interface is not available on the KT690/mITX board.
4.8.1 IEEE1394 Connector ( IEEE 1 394 _1 and IEEE1394_2)
The pinout of the Firewire / IEEE1394 connectors are as follows:
PIN
Note 1: The 12V supply for the IEEE1394 devices is on-board fused with a 1.5A reset-able fuse.
TPA1+
TPA1–
TPB1+
TPB1–
+12V +12V supply
Differential signal pair B
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Note
Pull
U/D Ioh/Iol
Type Signal
Signal
Type
Ioh/Iol
Pull
U/D Note
2K2
(24)/24
OC(O)
STB#
1 2 AFD#
OC(O)
(24)/24
2K2
2K2
24/24
IO
PD0
3 4 ERR# I -
2K2
2K2
24/24
IO
PD1
5 6 INIT#
OC(O)
(24)/24
2K2
2K2
24/24
IO
PD2
7 8 SLIN#
OC(O)
(24)/24
2K2
2K2
24/24
IO
PD3
9
10
GND
PWR - -
2K2
24/24
IO
PD4
11
12
GND
PWR - -
2K2
24/24
IO
PD5
13
14
GND
PWR - -
2K2
24/24
IO
PD6
15
16
GND
PWR - -
2K2
24/24
IO
PD7
17
18
GND
PWR - -
2K2 - I
ACK#
19
20
GND
PWR - -
2K2 - I
BUSY
21
22
GND
PWR - -
2K2 - I
PE
23
24
GND
PWR - -
2K2 - I
SLCT
25
26
GND
PWR - -
Printer Port Connector (PRINTER). 4.9
The signal definition in standard printer port mode is as follows:
PIN
The interpretation of the signals in standard Centronics mode (SPP) with a printer attached is as follows:
Signal Description
PD7..0 Parallel data bus from PC board to printer. The data lines are able to operate in PS/2
compatible bi-directional mode.
SLIN# Signal to select the printer sent from CPU board to printer.
SLCT Signal from printer to indicate that the printer is selected.
STB# This signal indicates to the printer that data at PD7..0 are valid.
BUSY Signal from printer indicating that the printer cannot accept further data.
ACK# Signal from printer indicating that the printer has received the data and is ready to accept
further data.
INIT# This active low output initializes (resets) the printer.
AFD# This active low output causes the printer to add a line feed after each line printed.
ERR# Signal from printer indicating that an error has been detected.
PE# Signal from printer indicating that the printer is out of paper.
The printer port additionally supports operation in the EPP and ECP mode as defined in [3].
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Note
Pull
U/D
Ioh/Iol
Type Signal
PIN
Signal
Type
Ioh/Iol
Pull
U/D
Note
- -
PWR
GND
1 2 DENSEL0#
OC
/48 - - - PWR
GND
3 4 NC
- - - - -
PWR
GND
5 6 NC
- - - - -
PWR
GND
7 8 INDEX#
IS
-
330R - -
PWR
GND
9
10
MOTEA#
OC
/48 -
- -
PWR
GND
11
12
NC
- - - - -
PWR
GND
13
14
DRVA#
OC
/48 -
- -
PWR
GND
15
16
NC
- - - - -
PWR
GND
17
18
DIR#
OC
/48 - - - PWR
GND
19
20
STEP#
OC
/48 - - - PWR
GND
21
22
WDATA#
OC
/48 - - - PWR
GND
23
24
WGATE#
OC
/48 - - - PWR
GND
25
26
TRK0#
IS
-
330R - -
PWR
GND
27
28
WPT#
IS
-
330R - - - NC
29
30
RDATA#
IS
-
330R - -
PWR
GND
31
32
SIDE1#
OC
/48 - - - -
NC
33
34
DSKCHG#
IS
-
330R
Floppy connector (FLOPPY). 4.10
The KT690 supports connection of one standard 1.44M Floppy Disk Drive. The Floppy Drive shall be
connected as A: (The “last” connector on a standard Floppy Disk cable kit).
Signal Description:
RDATA# Read Disk Data, active low, serial data input from the floppy disk drive.
WDATA# Write Disk Data, active low, serial data output to the floppy disk drive.
WGATE# This output signal enables the head of the selected disk drive to write to the disk.
MOTEA# This output signal enables the motor in floppy disk drive A.
DRVA# Active low output signal to select floppy disk drive A.
SIDE1# This output signal selects side of the disk in the selected drive.
DIR# This signal controls the direction of the floppy disk drive head movement during a seek
operation. A low level request steps through centre.
STEP# This output signal supplies step pulses to move the head during seek operations.
DENSEL0# This output indicates whether a low data rate (250/300kbps at low level) or a high data
rate (500/1000kbps at high level) has been selected.
TRK0# Floppy Disk Track 0, active low input to indicate that the head of the selected drive is at
track 0.
INDEX# Floppy Disk Index, active low input indicates the beginning of a disk track.
WPT# Active low input signal indicating that the selected drive contains a write protected disk.
DSKCHG# Input pin that senses whether the drive door has been opened or the diskette has been
changed.
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Signal
Description
Note
Pull
U/D
Ioh/Iol
Type Signal
Signal
Type
Ioh/Iol
Pull
U/D
Note
- I DCD
1 2 DSR
I -
- I RxD
3 4 RTS
O - - O TxD
5 6 CTS
I - - O DTR
7 8 RI I -
- -
PWR
GND
9
10
5V
PWR - -
1
Note
Pull
U/D
Ioh/Iol
Type Signal
Signal
Type
Ioh/Iol
Pull
U/D
Note
- I DCD
1 2 DSR
I - - I RxD
3 4 RTS
O - - O TxD
5 6 CTS
I -
- O DTR
7 8 RI I - - - PWR
GND
9
10
5V
PWR - -
1
Serial Ports 4.11
Two RS232 serial ports are available on the KT690/mITX boards
The typical interpretation of the signals in the COM ports is as follows:
TxD Transmitte Data, sends serial data to the communication link. The signal is set to a marking
state on hardware reset when the transmitter is empty or when loop mode operation is initiated.
RxD Receive Data, receives serial data from the communication link.
DTR Data Terminal Ready, indicates to the modem or data set that the on-board UART is ready to
establish a communication link.
DSR D ata Set Rea d y, indicates that the modem or data set is ready to establish a communication
link.
RTS Request To Send, indicates to the modem or data set that the on-board UART is ready to
exchange data.
CTS Clear To Send, indicates that the modem or data set is ready to exchange data.
DCD Data Carrier Detect, indicates that the modem or data set has detected the data carrier.
RI Ring Indicator, indicates that the modem has received a telephone-ringing signal.
The connector pinout for each operation mode is defined in the following sections.
4.11.1 Com1 Pin Header Connector.
The pinout of Serial ports Com1 is as follows:
PIN
Note 1: The Com1 header 5V supply is fused with a 1.1A resetable fuse.
A DB9 adapter (ribbon cable) can be used to make a DB9 pinout available.
4.11.2 Com2 Pin Header Connector.
The pinout of Serial ports Com2 is as follows:
PIN
Note 1: The Com2 header 5V supply is fused with a 1.1A resetable fuse.
A DB9 adapter (ribbon cable) can be used to make a DB9 pinout available.
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Signal
PIN
Type
Ioh/Iol
Note
MDI0+
MDI0-
MDI1+
MDI2+
MDI2-
MDI1-
MDI3+
MDI3-
8 7 6 5 4 3 2 1
Ethernet connectors. 4.12
The KT690/mITX boards supports 2 channels of 10/100/1000Mb Ethernet RTL8111B LAN controllers.
In order to achieve the specified performance of the Ethernet port, Category 5 twisted pair cables must be
used with 10/100MB and Category 5E, 6 or 6E with 1Gb LAN networks.
The signals for the Ethernet ports are as follows:
Signal Description
MDI[0]+ In MDI mode, this is the first pair in 1000Base-T, i.e. the BI_DA+/- pair, and is the transmit
MDI[0]-
MDI[1]+ In MDI mode, this is the second pair in 1000Base-T, i.e. the BI_DB+/- pair, and is the
MDI[1]-
MDI[2]+
MDI[2]-
MDI[3]+
MDI[3]-
Note: MDI = Media Dependent Interfac e.
pair in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is the receive pair in
10Base-T and 100Base-TX.
receive pair in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is the transmit pair in
10Base-T and 100Base-TX.
In MDI mode, this is the third pair in 1000Base-T, i.e. the BI_DC+/- pair.
In MDI crossover mode, this pair acts as the BI_DD+/- pair.
In MDI mode, this is the fourth pair in 1000Base-T, i.e. the BI_DD+/- pair.
In MDI crossover mode, this pair acts as the BI_DC+/- pair.
4.12.1 Ethernet connectors (ETHER1 and ETHER2)
Ethernet connector 1 is mounted together with USB Ports 8 and 9.
Ethernet connector 2 is mounted together with USB Ports 4 and 5.
The pinout of the RJ45 connector is as follows:
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Note
Pull
U/D Ioh/Iol
Type Signal PIN
Signal
Type
Ioh/Iol
Pull
U/D
Note
1 2 3 4 1 - - PWR
5V/SB5V
GND
PWR - -
/15K
0.25/2
IO
USB2-
USB2+
IO
0.25/2
/15K
1 2 3 4
1 - -
PWR
5V/SB5V
GND
PWR - -
/15K
0.25/2
IO
USB0-
USB0+
IO
0.25/2
/15K
Signal
Description
Differential pair works as Data/Address/Command Bus.
USB Connector (USB) 4.13
The KT690 boards contains one Enhanced Host Controller Interface (EHCI) host controllers that supports
USB 2.0 allowing data transfers up to 480Mb/s. The KT690 boards also contains five Open Hos t Controller
Interface (OHCI) controllers that support USB full-speed and low-speed signaling (USB 1.1).
The KT690 boards supports a total of ten USB 2.0 por ts . All ten ports are high-speed (USB 2.0) , full-speed
(USB 1.1), and low-speed (USB 1.1) capable and USB Legacy mode is supported.
Over-current detection on all ten USB ports is supported.
USB Port 0 and 2 are supplied on the USB0, USB2 frontpanel connector.
USB Ports 1 and 3 are supplied on the internal FRONTPNL connector; please refer to the FRONTPNL
connector section for the pin-out.
USB Port 4 and 5 are supplied on the combined ETHER2, USB4, USB5 connector.
USB Port 6 and 7 are supplied on the internal USB6, USB7 pinrow connector.
USB Port 8 and 9 are supplied on the combined ETHER1, USB8, USB9 connector.
Note: It is recommended to use only High-/Full-Speed USB cable, specified in USB2.0 standard:
4.13.1 USB Connector 0/2 (USB0/2)
USB Ports 0 and 2 are supplied on the USB0, USB2 frontpanel connector.
Note 1: The 5V supply for the USB devices is on-board fused with a 2.0A reset-able fuse. The supply is
common for the two channels. SB5V is supplied during power down to allow wakeup on USB device activity.
In order to meet the requirements of USB standard, the 5V input supply must be at least 5.00V.
USB0+ USB0USB2+ USB2-
USB5V 5V supply for external devices. Fused with 2.0A reset-able fuse.
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Note
Pull
U/D Ioh/Iol
Type Signal PIN
Signal
Type
Ioh/Iol
Pull
U/D
Note
1 2 3 4 1 - - PWR
5V/SB5V
GND
PWR - -
/15K
0.25/2
IO
USB4-
USB4+
IO
0.25/2
/15K
1 2 3 4
1 - -
PWR
5V/SB5V
GND
PWR - -
/15K
0.25/2
IO
USB5-
USB5+
IO
0.25/2
/15K
Differential pair works as Data/Address/Command Bus.
Note
Pull
U/D
Ioh/Iol
Type Signal
Signal
Type
Ioh/Iol
Pull
U/D
Note 1 - PWR
5V/SB5V
1 2 5V/SB5V
PWR - 1 -
IO
USB6-
3 4 USB7-
IO - -
IO
USB6+
5 6 USB7+
IO - -
PWR
GND
7 8 GND
PWR - - - KEY
9
10
NC - -
Signal
Description
Differential pair works as Data/Address/Command Bus.
4.13.2 USB Connector 4/5 (USB4/5)
USB Ports 4 and 5 are are supplied on the combined ETHER2, USB4, USB5 connector.
Note 1: The 5V supply for the USB devices is on-board fused with a 2.0A reset-able fuse. The supply is
common for the two channels. SB5V is supplied during power down to allow wakeup on USB device activity.
In order to meet the requirements of USB standard, the 5V input supply must be at least 5.00V.
Signal Description
USB4+ USB4USB5+ USB5-
USB5V 5V supply for external devices. Fused with 2.0A reset-able fuse.
4.13.3 USB Connector 6/7 (USB6/7)
USB Ports 6 and 7 are are supplied on the internal USB6, USB7 pinrow connector.
PIN
USB6+ USB6USB7+ USB7-
USB5V 5V supply for external devices. Fused with 2.0A reset-able fuse.
Note 1: The 5V supply for the USB devices is on-board fused with a 2.0A reset-able fuse. The supply is
common for the two channels. SB5V is supplied during power down to allow wakeup on USB device activity.
In order to meet the requirements of USB standard, the 5V input supply must be at least 5.00V.
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Note
Pull
U/D Ioh/Iol
Type Signal PIN
Signal
Type
Ioh/Iol
Pull
U/D
Note
1 2 3 4 1 - - PWR
5V/SB5V
GND
PWR - -
/15K
0.25/2
IO
USB9-
USB9+
IO
0.25/2
/15K
1 2 3 4
1 - -
PWR
5V/SB5V
GND
PWR - -
/15K
0.25/2
IO
USB8-
USB8+
IO
0.25/2
/15K
Differential pair works as Data/Address/Command Bus.
4.13.4 USB Connector 8/9 (USB8/9)
USB Ports 8 and 9 are supplied on the combined ETHER1, USB8, USB9 connector.
Note 1: The 5V supply for the USB devices is on-board fused with a 2.0A reset-able fuse. The supply is
common for the two channels. SB5V is supplied during power down to allow wakeup on USB device activity.
In order to meet the requirements of USB standard, the 5V input supply must be at least 5.00V.
Signal Description
USB8+ USB8USB9+ USB9-
USB5V 5V supply for external devices. Fused with 2.0A reset-able fuse.
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IN
Signal
Type
Note
TIP
LINE1-IN-L
IA 1 RING
LINE1-IN-R
IA 1 SLEEVE
GND
PWR
TIP
FRONT-OUT-L
OA RING
FRONT-OUT-R
OA
SLEEVE
GND
PWR TIP
MIC1-L
IA 1 RING
MIC1-R
IA 1 SLEEVE
GND
PWR
PIN
Signal
Type
Ioh/Iol
Pull
U/D
Note
1
CD_Left
IA - - 1 2
CD_GND
IA - - 3
CD_GND
IA - - 4
CD_Right
IA - -
1
Audio Connector 4.14
The onboard Audio circuit implements 7.1+2 Channel High Definition Audio, featuring ten 24-bit stereo DACs
and two 20-bit stereo ADCs.
Thew Audio signals are made available on the Frontpanel stacked connector (Line in / Line out / MIC) and
the onboard AUDIO_HEAD and CDROM Audioinput connectors.
4.14.1 Audio Line-in, Line-out and Microphone
Audio Line-in, Line-out and Microphone are available in the stacked audio jack connector.
Note 1: Signals are shorted to GND internally in the connector, when jack-plug not inserted.
4.14.2 CD-ROM Audio input (CDROM)
CD-ROM audio input may be connected to this connector. It may also be used as a secondary line-in signal.
Note 1: The definition of which pins are use for the Left and Right channels is not a worldwide accepted
standard. Some CDROM cable kits expect reverse pin order.
Signal Description
CD_Left
CD_Right
CD_GND Analogue GND for Left and Right CD.
Left and right CD audio input lines or secondary Line-in.
(This analogue GND is not shorted to the general digital GND on the board).
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Pull
U/D
Ioh/
Iol
Ioh/
Iol
Pull
U/D
LFE-OUT
1 2 CEN-OUT
AAGND
3 4 AAGND
FRONT-OUT-L
5 6 FRONT-OUT-R
AAGND
7 8 AAGND
REAR-OUT-L
9
10
REAR-OUT-R
SIDE-OUT-L
11
12
SIDE-OUT-R
AAGND
13
14
AAGND
MIC1-L
15
16
MIC1-R
AAGND
17
18
AAGND
LINE1-IN-L
19
20
LINE1-IN-R
NC
21
22
AAGND
- -
PWR
GND
23
24
SPDIF-IN
SPDIF-OUT
25
26
GND
PWR - -
Signal
Description
Note
4.14.3 AUDIO Header (AUDIO_HEAD)
Note
FRONT-OUT-L Front Speakers (Speaker Out Left).
FRONT-OUT-R Front Speakers (Speaker Out Right).
REAR-OUT-L Rear Speakers (Surround Out Left).
REAR-OUT-R Rear Speakers (Surround Out Right).
SIDE-OUT-L Side speakers (Surround Out Left)
SIDE-OUT-R Side speakers (Surround Out Right)
CEN-OUT
LFE-OUT Subwoofer Speaker (Low Freq. Effect Out).
NC No connection
MIC1 MIC Input 1
LINE1-IN Line in 1 signals
F-SPDIF-IN S/PDIF Input
F-SPDIF-OUT S/PDIF Output
AAGND Audio Analogue ground
Type Signal PIN Signal Type
Center Speaker (Center Out channel).
Note
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Signal
Type
Ioh/Iol
Pull
U/D
Note
1
CONTROL
O - - 2
SENSE
I - - 3
+12 V
PWR - - 4
GND
PWR - -
Signal
Type
Ioh/Iol
Pull
U/D
Note
2
SENSE
I - - 3
+12 V
PWR - - 4
GND
PWR - -
+12V supply for fan, can be turned on/off or modulated (PWM) by the chipset.
A maximum of 2000 mA can be supplied from this pin.
Fan connectors , FAN_CPU and FAN_SYS. 4.15
The FAN_CPU is used for connection of the active cooler for the CPU.
The FAN_SYS can be used to power, control and monitor a fan for chassis ventilation etc.
The 4pin header supports connection of 3-pin FANs, but it is recommended to use the 4-pin type for
optimized FAN speed control. The 3- or 4-pin mode is controlled in the BIOS setup menu.
4-pin Mode:
PIN
Signal description:
Signal Description
CONTROL PWM signal for FAN speed control
SENSE Tacho signal from the fan for supervision. The signals shall be generated by an open
collector transistor or similar. On board is a pull-up resistor 4K7 to +12V. The signal has to
be pulses, typically 2 Hz per rotation.
12V +12V supply for fan. A maximum of 2000 mA can be supplied from this pin.
GND Power Supply GND signal
3-pin Mode:
PIN
Signal description:
Signal Description
SENSE Tacho signal from the fan for supervision. The signals shall be generated by an open
collector transistor or similar. On board is a pull-up resistor 4K7 to +12V. The signal has to
be pulses, typically 2 Hz per rotation.
12V
GND Power Supply GND signal
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55
↑ CPU location ↑
No Jumper installed
1 2 3
(Pin numbers)
Jumper normal position
•
Jumper in Clear CMOS position
•
Note
Pull
U/D Ioh/Iol
Type Signal
Signal
Type
Ioh/Iol
Pull
U/D Note
- -
PWR
LPC CLK
1 2 GND
- -
PWR
LPC FRAME#
3 KEY
LPC RST#
5 6 +5V
LPC AD3
7 8 LPC AD2
+3V3
9
10
LPC AD1
LPC AD0
11
12
GND
SMB_CLK
13
14
SMB_DATA
SB3V3
15
16
LPC SERIRQ
GND
17
18
CLKRUN#
SUS_STAT#
19
20
LPC IRQ#
The Clear CMOS Jumper, Clr-CMOS. 4.16
The Clr-CMOS Jumper is used to clear the CMOS content.
To clear all CMOS settings, including Password protection, move the CMOS_CLR jumper (with or without
power on the system) for approximately 1 minute.
Alternatively if no jumper is available, turn off power and remove the battery for 1 minute, but be careful to
orientate the battery corretly when reinserted.
TPM connector (unsupported). 4.17
PIN
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Note
Pull
U/D Ioh/Iol
Type Signal
Signal
Type
Ioh/Iol
Pull
U/D Note
USB13_5V
1 2 USB13_5V
USB1-
3 4 USB3-
USB1+
5 6 USB3+
- -
PWR
GND
7 8 GND
PWR - - - - - KEY
10
LINE2-IN-L
- - - - -
PWR
+5V
11
12
+5V
PWR - -
OC
HD_LED
13
14
SUS_LED
- -
PWR
GND
15
16
PWRBTN_IN#
RSTIN#
17
18
GND
PWR - - SB3V3
19
20
LINE2-IN-R
- - - AGND
21
22
AGND
1 MIC2-L
23
24
MIC2-R
1
+5V supply for the USB devices on USB Port 1 and 3 is on-board fused with a 1.5A
power down to allow wakeup on USB device activity.
Front Panel connector (FRONTPNL). 4.18
PIN
Note 1: Unsupported inputs, leave these inputs unconnected.
Signal Description
USB13_5V
USB1+
USB1-
USB3+
USB3-
+5V
HD_LED Hard Disk Activity LED (active low signal). Output is via 475Ω to OC.
SUS_LED Suspend Mode LED (active high signal). Output is via 475Ω.
PWRBTN_IN# Power Button In. Toggle this signal low to start the ATX / BTX PSU and boot the board.
RSTIN#
LINE2-IN Line in 2 signals
MIC2 MIC2-L and MIC2-R are unsupported. Leave these terminals unconnected.
SB3V3
AGND Analogue Ground for Audio
reset-able fuse. The supply is common for the two channels. SB5V is supplied during
Universal Serial Bus Port 1 Differentials: Bus Data/Address/Command Bus.
Universal Serial Bus Port 3 Differentials: Bus Data/Address/Command Bus.
Maximum load is 1A or 2A per pin if using IDC connectorfladkabel or crimp terminals
respectively.
Reset Input. When pulled low for minimum 16mS the reset process will be initiated.
The reset process continues even though the Reset Input is kept low.
Standby 3.3V voltage
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Note
Pull
U/D
Ioh/Iol
Type Signal
Signal
Type
Ioh/Iol
Pull
U/D Note
2
2M/ - I
INTRUDER#
1 2 GND
PWR - - 4 I EXT_ISAIRQ#
3 4 EXT_SMI#
I 4 PWR_OK
5 6 SB5V
PWR - - - -
PWR
SB3V3
7 8 EXT_BAT
PWR - - - -
PWR
+5V
9
10
GND
PWR - - 1
4K7/
/12mA
IOT
GPIO0
11
12
GPIO1
IOT
/12mA
2K7/ 1 1
4K7/
/12mA
IOT
GPIO2
13
14
GPIO3
IOT
/12mA
2K7/ 1 1
4K7/
/12mA
IOT
GPIO4
15
16
GPIO5
IOT
/12mA
2K7/ 3 3
4K7/
/12mA
IOT
GPIO6
17
18
GPIO7
IOT
/12mA
2K7/
3
- -
PWR
GND
19
20
FAN3OUT
FAN3IN
21
22
+12V
PWR - - TEMP3IN
23
24
VREF
- -
PWR
GND
25
26
IRRX
IRTX
27
28
GND
PWR - - 1
2K7/
SMBC
29
30
SMBD
2K7/
1
INTRUDER, may be used to detect if the system case has been opened. This signal’s
status is readable, so it may be used like a GPI when the Intruder s witc h is not needed .
(EXTernal BATtery) the + terminal of an external primary cell battery can be connected
Current draw is 3µA when PSU is disconnected.
General Purpose Input/Output. The GPIO’s may be controlled or monitored through the
use of the KT-API-V2 (Application Programming Interface).
Temperature sensor 3 input. (Recommended: Transistor 2N3904, having em itter
(Precision +/- 3ºC)
Featur e Conne c t or (FEATURE) 4.19
PIN
Note 1: Pull-up to +3V3Dual (+3V3 or SB3V3). Note 2: Pull-up to RTC-Voltage. Note 3: Pull-up to +3V3.
Note 4: NOT supported.
Signal Description
INTRUDER#
EXT_ISAIRQ# EXTernal ISA IRQ, (active low input) can activate standard AT-Bus IRQ-interrupt.
EXT_SMI# External SMI, (active low input) signal can activate SMI interrupt.
PWR_OK PoWeR OK, signal is high if no power failures is detected.
SB5V StandBy +5V supply.
SB3V3 Max. load is 0.75A (1.5A < 1 sec.)
to this pin. The – terminal of the battery shall be connected to GND (etc. pin 10). The
EXT_BAT
+5V Max. load is 0.75A (1.5A < 1 sec.)
GPIO0..7
FAN3OUT
FAN3IN FAN3 Input. 0V to +3V3 amplitude Fan 3 tachometer input.
+12V Max. load is 0.75A (1.5A < 1 sec.)
external battery is protected against charging and can be used with or without the on
board battery installed. The external battery voltage shall be in the range: 2.5 - 4.0 V DC.
FAN 3 speed control OUTput. This analogue voltage output signal can be set to output
voltages from 0 – 3V3 to control the Fan’s speed.. For more information please look into
the datasheet for the Winbond I/O controller W83627.
TEMP3IN
VREF Voltage REFerence, reference voltage to be used with TEMP3IN input.
IRRX IR Receive input (IrDA 1.0, SIR up to 1.152K bps)
IRTX IR Transmit output (IrDA 1.0, SIR up to 1.152K bps)
SMBC SMBus Clock signal
SMBD SMBus Data signal
connected to GND (pin 25), collector and basis shorted and connected to pin23 (Temp3In). Further a resistor 30K/1% shall be connected between pin 23 and pin 24 (Vref).
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Terminal
Note
Type
Signal
S
C
Signal
Type
Note
PWR
-12V
F01
E01
TRST#
O
O TCK
F02
E02
+12V
PWR
PWR
GND
F03
E03
TMS
O NC
F04
E04
TDI O PWR
+5V
F05
E05
+5V
PWR
PWR
+5V
F06
E06
INTA#
I I INTB#
F07
E07
INTC#
I I INTD#
F08
E08
+5V
PWR
NC
F09
E09
NC
NC
F10
E10
+5V (I/O)
PWR
NC
F11
E11
NC O PWR
GND
F12
E12
GND
PWR
PWR
GND
F13
E13
GND
PWR
NC
F14
E14
3V3
OT
PWR
GND
F15
E15
RST#
O O PCICLK
F16
E16
+5V (I/O)
PWR
PWR
GND
F17
E17
GNT0#
OT
I
REQ0#
F18
E18
GND
PWR
PWR
+5V (I/O)
F19
E19
PME#
O
IOT
AD31
F20
E20
AD30
IOT
IOT
AD29
F21
E21
+3.3V
PWR
PWR
GND
F22
E22
AD28
IOT
IOT
AD27
F23
E23
AD26
IOT
IOT
AD25
F24
E24
GND
PWR
PWR
+3.3V
F25
E25
AD24
IOT
IOT
C/BE3#
F26
E26
IDSEL
IOT
IOT
AD23
F27
E27
+3.3V
PWR
PWR
GND
F28
E28
AD22
IOT
IOT
AD21
F29
E29
AD20
IOT
IOT
AD19
F30
E30
GND
PWR
PWR
+3.3V
F31
E31
AD18
IOT
IOT
AD17
F32
E32
AD16
IOT
IOT
C/BE2#
F33
E33
+3.3V
PWR
PWR
GND
F34
E34
FRAME#
IOT
IOT
IRDY#
F35
E35
GND
PWR
PWR
+3.3V
F36
E36
TRDY#
IOT
IOT
DEVSEL#
F37
E37
GND
PWR
PWR
GND
F38
E38
STOP#
IOT
IOT
LOCK#
F39
E39
+3.3V
PWR
IOT
PERR#
F40
E40
SMB_CLK
IO
PWR
+3.3V
F41
E41
SMB_DATA
IO
IOC
SERR#
F42
E42
GND
PWR
PWR
+3.3V
F43
E43
PAR
IOT
IOT
C/BE1#
F44
E44
AD15
IOT
IOT
AD14
F45
E45
+3.3V
PWR
PWR
GND
F46
E46
AD13
IOT
IOT
AD12
F47
E47
AD11
IOT
IOT
AD10
F48
E48
GND
PWR
PWR
GND
F49
E49
AD09
IOT
SOLDER SIDE
COMPONENT SIDE
IOT
AD08
F52
E52
C/BE0#
IOT
IOT
AD07
F53
E53
+3.3V
PWR
PWR
+3.3V
F54
E54
AD06
IOT
IOT
AD05
F55
E55
AD04
IOT
IOT
AD03
F56
F56
GND
PWR
PWR
GND
F57
E57
AD02
IOT
IOT
AD01
F58
E58
AD00
IOT
PWR
+5V (I/O)
F59
E59
+5V (I/O)
PWR
8K2/ PU
IOT
ACK64#
F60
E60
REQ64#
IOT
8K2/ PU
PWR
+5V
F61
E61
+5V
PWR
PWR
+5V
F62
E62
+5V
PWR
PCI Slot Connector 4.20
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Date 2012-06-01
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SYSTEM PINS
Clock provides timing for all transactions on PCI and is an input to every PCI device. All other PCI signals,
timing parameters are defined with respect to this edge. PCI operates at 33 MHz.
Reset is used to bring PCI-specific registers, sequencers, and signals to a consistent state. What effect
required to boot the system will respond after reset.
ADDRESS AND DATA
Address and Data are multiplexed on the same PCI pins. A bus transaction consists of an address phase
IRDY# and TRDY# are asserted.
Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address phase of a
meaningful data. C/BE[0]# applies to byte 0 (lsb) and C/BE[3]# applies to byte 3 (msb).
Parity is even parity across AD[31::00] and C/BE[3::0]#. Parity generation is required by all PCI agents.
has the same timing as AD[31::00], but it is delayed by one clock.) The master drives PAR for address and
write data phases; the target drives PAR for read data phases.
INTERFACE CONTROL PINS
Cycle Frame is driven by the current master to indicate the beginning and duration of an access. FRAME#
When FRAME# is deasserted, the transaction is in the final data phase or has completed.
Initiator Ready indicates the initiating agent’s (bus master’s) ability to complete the current data phase of
both IRDY# and TRDY# are asserted together.
Target Ready indicates the target agent’s (selected device’s) ability to complete the current data phase of
both IRDY# and TRDY# are asserted together.
Stop indicates the current target is requesting the master to stop the curre nt tra ns act ion.
Lock indicates an atomic operation that may require multiple transactions to complete. When LOCK# is
them should implement LOCK# as a target from the PCI bus point of view and optionally as a master.
Initialization Device Select is used as a chip select during configuration read and write transactions.
Device Select, when actively driven, indicates the driving device has decoded its address as the target of
the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected.
4.20.1 Signal Description –PCI Slot Connector
CLK
RST#
AD[31::00]
C/BE[3::0]#
PAR
except RST#, INTA#, INTB#, INTC#, and INTD#, are sampled on the rising edge of CLK and all other
RST# has on a device beyond the PCI sequencer is beyond the scope of this specification, except for
reset states of required PCI configuration registers. Anytime RST# is asserted, all PCI output signals must
be driven to their benign state. In general, this means they must be asynchronously tri-stated. SERR#
(open drain) is floated. REQ# and GNT# must both be tri-stated (they cannot be driven low or high during
reset). To prevent AD, C/BE#, and PAR signals from floating during reset, the central resource may drive
these lines during reset (bus parking) but only to a logic low level–they may not be driven high.
RST# may be asynchronous to CLK when asserted or deasserted. Although asynchronous, deassertion is
guaranteed to be a clean, bounce-free edge. Except for configuration accesses, only devices that are
followed by one or more data phases. PCI supports both read and write bursts.
The address phase is the clock cycle in which FRAME# is asserted. During the address phase AD[31::00]
contain a physical address (32 bits). For I/O, this is a byte address; for configuration and memory, it is a
DWORD address. During data phases AD[07::00] contain the least significant byte (lsb) and AD[31::24]
contain the most significant byte (msb). Write data is stable and valid when IRDY# is asserted and read
data is stable and valid when TRDY# is asserted. Data is transferred during those clocks where both
transaction, C/BE[3::0]# define the bus command. During the data phase C/BE[3::0]# are used as Byte
Enables. The Byte Enables are valid for the entire data phase and determine which byte lanes carry
PAR is stable and valid one clock after the address phase. For data phases, PAR is stable and valid one
clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction.
Once PAR is valid, it remains valid until one clock after the completion of the current data phase. (PAR
FRAME#
IRDY#
TRDY#
STOP#
LOCK#
IDSEL
DEVSEL#
is asserted to indicate a bus transaction is beginning. While FRAME# is asserted, data transfers continue.
the transaction. IRDY# is used in conjunction with TRDY#. A data phase is completed on any clock both
IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates that valid data is present on
AD[31::00]. During a read, it indicates the master is prepared to accept data. Wait cycles are inserted until
the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed on any clock both
TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that valid data is present on
AD[31::00]. During a write, it indicates the target is prepared to accept data. Wait cycles are inserted until
asserted, non-exclusive transactions may proceed to an address that is not currently locked. A grant to
start a transaction on PCI does not guarantee control of LOCK#. Control of LOCK# is obtained under its
own protocol in conjunction with GNT#. It is possible for different agents to use PCI while a single master
retains ownership of LOCK#. If a device implements Executable Memory, it should also implement LOCK#
and guarantee complete access exclusion in that memory. A target of an access that supports LOCK#
must provide exclusion to a minimum of 16 bytes (aligned). Host bridges that have system memory behind
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ARBITRATION PINS (BUS MASTERS ONLY)
Request indicates to the arbiter that this agent desires use of the bus. This is a point to point signal. Every
master has its own REQ# which must be tri-stated while RST# is asserted.
Grant indicates to the agent that access to the bus has been granted. This is a point to point signal. Every
master has its own GNT# which must be ignored while RST# is asserted.
While RST# is asserted, the arbiter must ignore all REQ# lines since they are tri-stated and do not contain
buffer.
ERROR REPORTING PINS.
The error reporting pins are required by all devices and maybe asserted when enabled
Parity Error is only for the reporting of data parity errors during all PCI transactions except a Special
when a data parity error may be lost or when reporting of an error may be delayed. An agent cannot report
ntil it has claimed the access by asserting DEVSEL# (for a target) and completed a data phase
or is the master of the current transaction.
System Error is for reporting address parity errors, data parity errors on the Special Cycle command, or
system does so anytime SERR# is sampled asserted.
INTERRUPT PINS (OPTIONAL).
only INTA# may be used while the other three interrupt lines have no meaning.
Interrupt A is used to request an interrupt.
Interrupt B is used to request an interrupt and only has meaning on a multi-function device.
Interrupt C is used to request an interrupt and only has meaning on a multi-function device.
Interrupt D is used to request an interrupt and only has meaning on a multi-function device.
Board type
Slot
IDSEL
INTA
INTB
INTC
INTD
KT690/mITX
1
AD16
INT_PIRQ#A
INT_PIRQ#B
INT_PIRQ#C
INT_PIRQ#D
KT690/mITX-FW
1
AD16
INT_PIRQ#A
INT_PIRQ#B
INT_PIRQ#C
INT_PIRQ#D
KT690/mITX (BGA)
1
AD16
INT_PIRQ#A
INT_PIRQ#B
INT_PIRQ#C
INT_PIRQ#D
REQ#
GNT#
KT690 Family
PERR#
SERR#
Interrupts on PCI are optional and defined as “level sensitive,” asserted low (negative true), using open drain output
drivers. The assertion and deassertion of INTx# is asynchronous to CLK. A device asserts its INTx# line when requesting
attention from its device driver. Once the INTx# signal is asserted, it remains asserted until the device driver clears the
pending request. When the request is cleared, the device deasserts its INTx# signal. PCI defines one interrupt line for a
single function device and up to four interrupt lines for a multi-function device or connector . For a single fun ctio n devi ce,
a valid request. The arbiter can only perform arbitration after RST# is deasserted. A master must ignore
its GNT# while RST# is asserted. REQ# and GNT# are tri-state signals due to power sequencing
requirements when 3.3V or 5.0V only add-in boards are used with add-in boards that use a universal I/O
Cycle. The PERR# pin is sustained tri-state and must be driven active by the agent receiving data two
clocks following the data when a data parity error is detected. The minimum duration of PERR# is one
clock for each data phase that a data parity error is detected. (If sequential data phases each have a data
parity error, the PERR# signal will be asserted for more than a single clock.) PERR# must be driven high
for one clock before being tri-stated as with all sustained tri-state signals. There are no special conditions
a PERR# u
any other system error where the result will be catastrophic. If an agent does not want a non-maskable
interrupt (NMI) to be generated, a different reporting mechanism is required. SERR# is pure open drain
and is actively driven for a single PCI clock by the agent reporting the error. The assertion of SERR# is
synchronous to the clock and meets the setup and hold times of all bused signals. However, the restoring
of SERR# to the deasserted state is accomplished by a weak pullup (same value as used for s/t/s) which
is provided by the system designer and not by the 60signaling agent or central resource. This pull-up may
take two to three clock periods to fully restore SERR#. The agent that reports SERR#s to the operating
INTA#
INTB#
INTC#
INTD#
4.20.2 KT690 PCI IRQ & INT routing
When using the 820982 “PCI Riser - Flex - 2slot w. arbiter” the lower slot has IDSEL / IRQs routed straight
through and the top slot has the routing: IDSEL=AD22, INT_PIRQ#F, INT_PIRQ#G, INT_PIRQ#H,
INT_PIRQ#E. 820982 PCI Riser shall be plugged into Slot #1.
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Onboard Connectors
Mating Connectors
Manufacturer
Type no.
Manufacturer
Type no.
FAN_SYS,
Molex
22-23-2031
AMP
1375820-3
FAN_CPU
KBDMSE
Molex
22-23-2061
Molex
22-01-2065
CDROM
Foxconn
HF1104E
Molex
50-57-9404
Molex
70543-0038
SATA0-3
Molex
67491-0020
Molex
67489-8005
Kontron
KT 821035 (cable kit)
IEEE1394_0
IEEE1394_1
ATXPWR
Foxconn
HM2510E
Molex
39-01-2205
COM1 + COM2
Foxconn
HL20051
Molex
90635-1103
Kontron
KT 821016 (cable kit)
Kontron
KT 821017 (cable kit)
USB6
USB7
PRINTER
Foxconn
HL2213F
Molex
90635-1263
Kontron
KT 821031 (cable kit)
AUDIO_HEAD
Molex
87831-2620
Molex
51110-2651
Kontron
KT 821043 (cable kit)
FRONTPNL
Foxconn
HL20121
Molex
90635-1243
Kontron
KT 821042 (cable kit)
FEATURE
Molex
87831-3020
Molex
51110-3051
Kontron
KT 821041 (cable kit)
LVDS
Don Connex
C44-40BSB1-G
Don Connex
A32-40-C-G-B-1
Kontron
KT 821515 (cable kit)
Kontron
KT 821155 (cable kit)
5. Onboard Connectors
Connector
Foxconn HC11051-P9 Kontron KT 821040 (cable kit)
Foxconn HC11051-P9 Kontron KT 821401 (cable kit)
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Address range (hex)
Size (bytes)
Description
00000000
0009FFFF
655359
System board
000A0000
000BFFFF
131071
ATI Radeon X1200 Series
000A0000
000BFFFF
131071
PCI bus
000A0000
000BFFFF
131071
PCI standart PCI-to-PCI brigde
000C0000
000CFFFF
65535
System board
000D0000
000DFFFF
65535
PCI bus
000E0000
000FFFFF
131071
System board
00100000
37FFFFFF
938475519
System board
38000000
3FFFFFFF
134217727
Motherboard resources
38000000
DFFFFFFF
2818572287
PCI bus
E0000000
EFFFFFFF
268435455
Motherboard resources
F0000000
F7FFFFFF
134217727
ATI Radeon X1200 Series
F0000000
F7FFFFFF
134217727
PCI standart PCI-to-PCI brigde
F0000000
FED44FFF
248795135
PCI bus
FE7F4000
FE7F7FFF
16383
Microsoft UAA Bus Driver for High Definition Audio
FE7FA000
FE7FAFFF
4095
Standard OpenHCD USB Host Controller
FE7FB000
FE7FBFFF
4095
Standard OpenHCD USB Host Controller
FE7FC000
FE7FCFFF
4095
Standard OpenHCD USB Host Controller
FE7FD000
FE7FDFFF
4095
Standard OpenHCD USB Host Controller
FE7FE000
FE7FEFFF
4095
Standard OpenHCD USB Host Controller
FE7FF000
FE7FFFFF
4095
Standard Enchanced PCI to USB Host Controller
FE7FF800
FE7FFBFF
1023
Standart Dual Channel PCI IDE Controller
FE800000
FE8FFFFF
1048575
ATI Radeon X1200 Series
FE800000
FE9FFFFF
2097151
PCI standart PCI-to-PCI brigde
FE9F0000
FE9FFFFF
65535
ATI Radeon X1200 Series
FEA00000
FEAFFFFF
1048575
PCI standart PCI-to-PCI brigde
FEAFF000
FEAFFFFF
4095
Realtek RTL8168/8111 PCI-E Gigabit Ethernet NIC
FEB00000
FEBFFFFF
1048575
PCI standart PCI-to-PCI brigde
FEBFF000
FEBFFFFF
4095
Realtek RTL8168/8111 PCI-E Gigabit Ethernet NIC
FEC00000
FEC00FFF
4095
Motherboard resources
FED00000
FED003FF
1023
High precision event timer
FED45000
FFFFFFFF
19640319
System board
FEE00000
FEE00FFF
4095
Motherboard resources
FFB80000
FFBFFFFF
524287
Motherboard resources
6. S ystem Ressources
Memory map 6.1
KT690 Family
KTD-00738-J
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Bus
#
Device
#
Function
#
Vendor
ID
Device
ID
IDSEL
Chip
Device Function
0 0 0
1002h
7910h
SB600
Host brigde
0 1 0
1002h
7912h
SB600
Pci to Pci Brigde
0 6 0
1002h
7916h
SB600
Pci to Pci Brigde
0 7 0
1002h
7917h
SB600
Pci to Pci Brigde
0
18
0
1002h
4380h
SB600
IDE Controller
0
19
0
1002h
4387h
SB600
USB 0 19
1
1002h
4388h
SB600
USB 0 19
2
1002h
4389h
SB600
USB 0 19
3
1002h
438Ah
SB600
USB 0 19
4
1002h
438Bh
SB600
USB 0 19
5
1002h
4386h
SB600
USB 0 20
0
1002h
4385h
SB600
SMBus 0 20
1
1002h
438Ch
SB600
IDE Controller
0
20
2
1002h
4383h
SB600
HD Audio
0
20
3
1002h
438Dh
SB600
ISA Brigde
0
20
4
1002h
4384h
SB600
Pci to Pci Brigde
0
24
0
1002h
1100h
SB600
Host brigde
0
24
1
1022h
1101h
SB600
Host brigde
0
24
2
1022h
1102h
SB600
Host brigde
0
24
3
1022h
1103h
SB600
Host brigde
1 5 0
1022h
791Fh
RS690
VGA Controller
2 0 0
10ECh
8168h
RTL8111
Ethernet
3 0 0
10ECh
8168h
RTL8111
Ethernet
4 0 0 - -
- PCI Slot
* - - - -
- PCI-E Slot
PCI devices 6.2
When a PCI-E card is used it could change the BUS number on other PCI-E and PCI devices like
RTL8111b.
Note: PCI slot supports PCI BUS Mastering.
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IRQ
Notes
• ?
IRQ0
•
IRQ1
•
IRQ2
•
• 1, 2
IRQ4
• 1, 2
IRQ5
• 1, 2
IRQ6
1, 2
• • 1, 2
IRQ8
•
IRQ9
• • 1, 2
IRQ10
• 1, 2
• 1, 2
IRQ12
• 1
IRQ13
•
1
IRQ15
1
IRQ16
• • 3
IRQ17
• 3
• • • 3
IRQ19
• • 3
IRQ20
3
3
IRQ22
• 3
IRQ23
3
3
IRQ25
3
IRQ26
3
Interrupt Usage 6.3
NMI
IRQ3
IRQ7
IRQ11
IRQ14
IRQ18
IRQ21
Onboard system parity errors and IOCHCHK signal activation
Onboard Timer 0 Interrupt
Onboard Keyboard Interrupt
Used for Cascading IRQ8-IRQ15
May be used by onboard Serial Port A
May be used by onboard Serial Port B / IrDA Port
May be used by onboard Parallel Port
Used by onboard Real Time Clock Alarm
May be used by onboard P/S 2 support
Used for Onboard co-processor support
May be used for SATA RAID controller
May be used for onboard Sound System
May be used for PCI Express Root Port
May be used by onboard USB controller
May be used by onboard Ethernet controller 1
May be used by onboard Ethernet controller 2
May be used by onboard VGA Controller
May be used by onboard IDE Controller
May be used by Microsoft ACPI-Compliant System
Available on PCI slots as IRQA-IRQD depending on selections in BIOS
IRQ24
1. Availability of the shaded IRQs depends on the setting in the BIOS. According to the PCI Standard,
2. These IRQ´s are managed by the PnP handler and are subject to change during system initialisation.
3. IRQ16 to IRQ26 are APIC interrupts
Notes:
PCI Interrupts IRQA-IRQD can be shared.
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Address (hex)
Size
Description
0020
0021
2
Programmable interupt controller
0040
0043
4
System timer
0060
0060
1
Standard Keyboard
0061
0061
1
System speaker
0064
0064
1
Standard Keyboard
0070
0071
2
System CMOS/Real time clock
00F0
00FF
16
Numeric data processor
0170
0177
8
Secondary IDE Channel
01F0
01F7
8
Primary IDE Channel
0274
0277
4
ISAPNP Read Data Port
0279
0279
1
ISAPNP Read Data Port
02F8
02FF
8
Com2
0376
0376
1
Secondary IDE Channel
0378
037F
8
LPT1
03B0
03BB
12
PCI-to-PCI brigde
03C0
03DF
32
PCI-to-PCI brigde
03F6
03F6
1
Primary IDE Channel
0A79
0A79
1
ISAPNP Read Data Port
0B00
0B0F
16
ATI SMBus
7000
700F
16
Standart Dual Channel PCI IDE Controller
8000
8003
4
Standart Dual Channel PCI IDE Controller
9000
9007
8
Standart Dual Channel PCI IDE Controller
A000
A003
4
Standart Dual Channel PCI IDE Controller
B000
B007
8
Standart Dual Channel PCI IDE Controller
C000
CFFF
4096
PCI-to-PCI brigde
C000
C0FF
256
ATI Radeon X1200 Series
D000
DFFF
4096
PCI-to-PCI brigde
D800
D8FF
256
Realtek RTL8168/8111 PCI-E Gigabit Ethernet NIC
E000
EFFF
4096
PCI-to-PCI brigde
E800
E8FF
256
Realtek RTL8168/8111 PCI-E Gigabit Ethernet NIC 2
FF00
FF0F
16
Standart Dual Channel PCI IDE Controller
DMA Channel Number
Data Width
System Ressources
0
8 or 16 bits
Available
1
8 or 16 bits
Available
2
8 or 16 bits
Available
3
8 or 16 bits
Available
4
8 or 16 bits
DMA Controller
5
16 bits
Available
6
16 bits
Available
7
16 bits
Available
I/O Map 6.4
Notes: This is the IO map after a standard Windows XP SP2 installation
DMA Channel Usage 6.5
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7. Overview of BIOS features
This Manual section details specific BIOS features for the KT690 boards.
The KT690 boards are based on the AMI BIOS core version 8.10 with Kontron BIOS extensions.
System Management BIOS (SMBIOS / DMI) 7.1
SMBIOS is a Desktop Management Interface (DMI) compliant method for managing computers in a
managed network.
The main component of SMBIOS is the Management Information Format (MIF) database, which contains
information about the computing system and its components. Using SMBIOS, a system administrator can
obtain the system types, capabilities, operational status, and installation dates for system components.
The MIF database defines the data and provides the method for accessing this information. The BIOS
enables applications such as third-party management software to use SMBIOS.
The BIOS stores and reports the following SMBIOS information:
• BIOS data, such as the BIOS revision level
• Fixed-system data, such as peripherals, serial numbers, and asset tags
• Resource data, such as memory size, cache size, and processor speed
• Dynamic data, such as event detection and error logging
Non-Plug and Play operating systems, such as Windows NT*, require an additional interface for obtaining
the SMBIOS information. The BIOS supports an SMBIOS table interface for such operating systems. Using
this support, an SMBIOS service-level application running on a non-Plug and Play operating system can
obtain the SMBIOS information.
Legacy USB Support 7.2
Legacy USB support enables USB devices such as keyboards, mice, and hubs to be used even when the
operating system’s USB drivers are not yet available. Legacy USB support is used to access the BIOS Setup
program, and to install an operating system that supports USB. By default, Legacy USB support is set to
Enabled.
Legacy USB support operates as follows:
1. When you apply power to the computer, legacy support is disabled.
2. POST begins.
3. Legacy USB support is enabled by the BIOS allowing you to use a USB keyboard to enter and
configure the BIOS Setup program and the maintenance menu.
4. POST completes.
5. The operating system loads. While the operating system is loading, USB keyboards and mice are
recognized and may be used to configure the operating system. (Keyboards and mice are not
recognized during this period if Legacy USB support was set to Disabled in the BIOS Setup
program.)
6. After the operating system loads the USB drivers, all legacy and non-legacy USB devices are
recognized by the operating system, and Legacy USB support from the BIOS is no longer used.
To install an operating system that supports USB, verify that Legacy USB support in the BIOS Setup
program is set to Enabled and follow the operating system’s installation instructions.
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BIOS SETUP UTILITY
Main Advanced PCIPnP Boot Security Chipset Exit
BIOS SETUP UTILITY
Main Advanced PCIPnP Boot Security Chipset Exit
System Overview
Use [ENTER], [TAB] or
AMIBIOS
System Date [09/08/2010]
V02.59+ (C)Copyright 1985-2005, American Megatrends, Inc.
Feature
Options
Description
System Ti me
HH:MM:SS
Set the system time.
System Date
MM/DD/YYYY
Set the system date.
8. BIOS Configuration / Setup
Introduction 8.1
The BIOS Setup is used to view and configure BIOS settings for the KT690 board. KT690/mITX (BGA) is
supported by BIOS version from KT690013 . The BIOS Setup is accessed by pressing the DEL key after the
Power-On Se lf-Test (POST) memory test begins and before the operating system boot begins. The Menu
bar look like this:
The available keys for the Menu screens are:
Select Menu: <←> or <→>
Select Item: <↑> or <↓>
Select Field: <Tab>
Change Field: <+> or <->
Help: <F1>
Save and Exit: <F10>
Exits the Menu: <Esc>
Please note that in the following the different BIOS Features will be described as having some options.
These options will be selected automatically when loading either Failsafe Defaults or Optimal Defaults. The
Default options will be indicated by the option in bold, but please notice that when Failsafe Defaults are
loaded a few of the options, marked with “*”, are now the default option.
Main Menu 8.2
Version : 08.00.14
Build Date: 07/30/10
ID : KT690013
PCB ID : 82
Serial # : 00615444
Part # : 61620001
<- Select Screen
|| Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit
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BIOS SETUP UTILITY
Advanced
IDE Configuration
Options
OnBoard PCI IDE Controller [Primary]
V02.59+ (C)Copyright 1985-2005, American Megatrends, Inc.
Feature
Options
Description
OnBoard PCI IDE Controller
Disable
Primary
Controls the 40Pin PATA connector and CF
interface.
Feature
Options
Description
OnChip SATA Channel
Enabled
Disabled
Enabled/Disabled the SATA circuit
OnChip SATA Channel
Native IDE
Legacy IDE
Native IDE
Legacy IDE
Feature
Options
Description
Hard Disk Write Protect
Disabled
Enabled
Disabled
Enhanced
IDE Detect Time Out (Sec)
0
35
Select the time out value for detecting ATA/ATAPI
ATA(PI) 80Pin Cable
Host & Device
Device
Select the mechanism for detecting 80Pin ATA(PI)
8.3.2 Advanced settings – IDE Configuration
OnChip SATA Type [Enabled]
OnChip SATA Channel [Native IDE]
Primary IDE Master : [Hard Disk]
Secondary IDE Master : [Not Detected]
Third IDE Master : [Not Detected]
Third IDE Slave : [Not Detected]
Fourth IDE Master : [Not Detected]
Fourth IDE Slave : [Not Detected]
Hard Disk Write Protect [Disabled]
IDE Detect Time Out (Sec) [35]
ATA(PI) 80Pin Cable Detection [Host & Device]
Controls the 40Pin
PATA connector and
CF interface.
<- Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
ESC Exit
RAID
AHCI
5
10
15
20
25
30
RAID (Press <Ctrl><F> to enter RAID BIOS menu)
AHCI
device(s)
Detection
Host
Cable
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BIOS SETUP UTILITY
Advanced
Primary IDE Master
Select the type of
Device :Hard Disk
S.M.A.R.T. :Supported
V02.59+ (C)Copyright 1985-2005, American Megatrends, Inc.
Feature
Options
Description
Type
Not Installed
ARMD
Select the type of device installed
LBA/Large Mode
Disabled
Auto
Enabling LBA causes Logical Block Addressing to be
used in place of Cylinders, Heads, and Sectors.
Block (Multi-Sector Transfer)
Disabled
Auto
Select if the device should run in Block mode
PIO Mode
Auto
4
Selects the method for transferring the data between
DMA Mode
Auto
UDMA5
Selects the Ultra DMA mode used for
S.M.A.R.T.
Auto
Enabled
Select if the Device should be monitoring itself (SelfSystem)
the hard disk and system memory. The Setup menu
only lists those options supported by the drive and
platform.
moving data to/from the drive. Autotype the drive to
select the optimum transfer mode.
Note: To use UDMA Mode 2, 3, 4 and 5 with a
device, the harddisk cable used MUST be
UDMA66/100 cable (80-conductor cable).
Disabled
Enabled
Monitoring, Analysis and Reporting Technology
Transfer
(continues)
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Feature
Options
Description
Hard Disk Write Protect
Disabled
Enabled
Enable write protection on HDDs, only works when
it is accessed through the BIOS
IDE Detect Time Out (Sec)
0
35
Select the time out value when the BIOS is
ATA(PI) 80Pin Cable
Host & Device
Device
Select the mechanism for detecting 80Pin ATA (PI)
Detection
5
10
15
20
25
30
Host
detecting ATA/ATAPI Devices
Cable
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BIOS SETUP UTILITY
Advanced
LAN Configuration
Control of Ethernet
V02.59+ (C)Copyright 1985-2005, American Megatrends, Inc.
Feature
Options
Description
ETH1 Configuration
Disabled
With RPL/PXE boot
Select if you want to enable the LAN adapter, or if
ETH2 Configuration
Disabled
With RPL/PXE boot
Select if you want to enable the LAN adapter, or if
BIOS SETUP UTILITY
Advanced
Floppy Configuration
Select the type of
ESC Exit
Floppy A [Disabled]
V02.59+ (C)Copyright 1985-2005, American Megatrends, Inc.
Feature
Options
Description
Floppy A
Disabled
Enabled
Select the type of floppy drive connected to the
system.
8.3.3 Advanced settings – LAN Configuration
ETH1 Configuration (Left) [Enabled]
MAC Address : 00E0F4000001
ETH2 Configuration (Right) [Enabled]
MAC Address : 00E0F4000002
Devices and PXE boot
<- Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
ESC Exit
Enabled
Enabled
you want to activate the RPL/PXE boot rom
you want to activate the RPL/PXE boot rom
8.3.4 Advanced settings – Floppy Configuration
floppy drive
connected to the
system.
<- Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
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BIOS SETUP UTILITY
Advanced
Configure Win627DHG Super IO Chipset
Allows BIOS to Enable
ESC Exit
OnBoard Floppy Controller [Enabled]
V02.59+ (C)Copyright 1985-2005, American Megatrends, Inc.
Feature
Options
Description
OnBoard Floppy Controller
Enabled
Disabled
Allows BIOS to Enable or Disable Floppy
Controller.
Serial Port1 Address
Disabled
2E8/IRQ11
Select the BASE I/O addresse and IRQ.
Serial Port2 Address
Disabled
2E8/IRQ11
Select the BASE I/O addresse and IRQ.
Serial Port2 Mode
Normal
ASK IR
Select Mode for Serial Port2
Parallel Port Address
Disabled *
3BC
Select the I/O address for the PRINTER.
Parallel Port Mode
Normal
ECP & EEP
Select the mode that the parallel port will operate in
EPP Version
1.9
1.7
Setup with version of EPP you want to run on the
parallel port
ECP Mode DMA Channel
DMA0
DMA3
Select a DMA channel
Parallel Port IRQ
IRQ5
IRQ7
Select a IRQ
8.3.5 Advanced settings – Super IO Configuration
Serial Port1 Address [3F8/IRQ4]
Serial Port2 Address [2F8/IRQ3]
Serial Port2 Mode [Normal]
Parallel Port Address [378]
Parallel Port Mode [Normal]
Parallel Port IRQ [IRQ7]
or Disable Floppy
Controller.
<- Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
3F8/IRQ4
3E8/IRQ4
3E8/IRQ6
3E8/IRQ10
2F8/IRQ3
2E8/IRQ3
3E8/IRQ6
3E8/IRQ10
IRDA
378
278
Bi-Directional
EPP
(The available options depends on the setup for the
the other Serial Ports).
(The available options depends on the setup for the
the other Serial Ports).
DMA1
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BIOS SETUP UTILITY
Advanced
Hardware Health Configuration
Disable = Full Speed
System Temperature :37ºC/98ºF
V02.59+ (C)Copyright 1985-2005, American Megatrends, Inc.
Feature
Options
Description
Fan Cruise Control
Disabled
Select how the Fan shall operate.
speed set below.
Fan Type
4 wire
Select the electrical interface for the fan:
4 Wire = 12VDC always PWM on control signal
Fan Settings
1406-5625 RPM
30°-75°C
The fan can operate in Thermal mode or in a fixed
fan speed mode
Watchdog
Disabled
10 minutes
To be serviced via A PI.
8.3.6 Advanced settings – Hardware Health Configuration
CPU Temperature :43ºC/109ºF
External Temperature Sensor :N/A
System Fan Speed :Fail
Fan Cruise Control [Disabled]
Fan Type [4 Wire]
CPUFan0 Speed :2537 RPM
Fan Cruise Control [Thermal]
Fan Setting [45°C/113°F]
Fan Type [4 Wire]
AUXFAN Speed :2164
Fan Cruise Control [Speed]
Fan Setting [2177 RPM]
Watchdog Function [Disabled]
Thermal: Does regulate
fan speed according to
specified temperature
Speed: Does regulate
according to specified
RPM
<- Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
ESC Exit
Serial port number [COM1]
Base Address, IRQ [3F8h, 4]
Serial Port Mode [115200 8,n,1]
Flow Control [None]
Redirection After BIOS POST [Always]
Terminal Type [ANSI]
type.
<- Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
ESC Exit
Enabled
57600 8 n 1
38400 8 n 1
19200 8 n 1
Hardware
Boot Loader
VT100
serial ports behave like a TTY terminal, so that
keyboard and monitor (in a terminal window) is
emulated by the remote PC. As remote PC terminal
serial port
Delay 1 Sec
Delay 2 Sec
information
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BIOS SETUP UTILITY
Advanced
Trusted Computing
Enables/Disable TPM
TCG/TPM Support [No]
V02.59+ (C)Copyright 1985-2005, American Megatrends, Inc.
Feature
Options
Description
TCG/TPM Support
No
Yes
Enables/Disable TPM TCG (TPM 1.1/1.2) Support.
BIOS SETUP UTILITY
Advanced
USB Configuration
Enables support for
Module Version – 2.24.2-13.4
V02.59+ (C)Copyright 1985-2005, American Megatrends, Inc.
Feature
Options
Description
Legacy USB Support
Disabled
Auto
Support for legacy USB Keyboard
USB 2.0 Controller Mode
FullSpeed
Configure the USB 2.0 controller in HiSpeed
disabled as default.
BIOS EHCI Hand-Off
Enabled
This is a workaround for OSes without EHCI hand-off
by EHCI driver.
8.3.10 Advanced settings – Trusted Support
TCG (Tpm 1.1/1.2)
Support in Bios
<- Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
ESC Exit
8.3.11 Advanced settings – USB Configuration
USB Devices Enabled :
1 Drive
Legacy USB Support [Enabled]
USB 2.0 Controller Mode [HiSpeed]
BIOS EHCI Hand-Off [Enabled]
USB Mass Storage Device Configuration
legacy USB. AUTO
option disables if no
USB Devices are
connected.
<- Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
ESC Exit
Enabled
HiSpeed
Disabled
(480Mbps) or FullSpeed (12Mbps).
Note: This feature is not available when Failsafe
Defaults are loaded, because USB2.0 controller is
support. The EHCI Ownership change should claim
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BIOS SETUP UTILITY
Advanced
USB Mass Storage Device Configuration
Number of seconds POST
USB Mass Storage Reset Delay [20 Sec]
V02.59+ (C)Copyright 1985-2005, American Megatrends, Inc.
BIOS SETUP UTILITY
Advanced
Clock Generator Settings
V02.59+ (C)Copyright 1985-2005, American Megatrends, Inc.
Feature
Options
Description
USB Mass Storage Reset
10 Sec
40 Sec
Number of seconds POST waits for the USB mass
Emulation Type
Auto
CDROM
If Auto, USB devices less than 530MB will be
Feature
Options
Description
Spread Spectrum
Disabled
0.5%
Controls the clock generator clock output to enable
(0.5%) or disable Spread spectrum
8.3.12 Advanced settings – USB Mass Storage Device Configuration
waits for the USB mass
Device #1 JetFlash TS256MJF2L
Emulation Type [Auto]
storage device after
start unit command.
<- Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
ESC Exit
configure all the
devices in the system.
YES: lets the
operating system
configure Plug and
Play (PnP) devices not
required for boot if
your system has a Plug
and Play operating
system.
<- Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
ESC Exit
Yes
Reserved
system.
YES: lets the operating system configure Plug and
Play (PnP) devices not required for boot if your
PCI/PnP device. Reserved: Specified IRQ is
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BIOS SETUP UTILITY
Main Advanced PCIPnP Boot Security Chipset Exit
Boot Settings
Configure Settings
V02.59+ (C)Copyright 1985-2005, American Megatrends, Inc.
BIOS SETUP UTILITY
Boot
Boot Settings
Configure Settings
V02.59+ (C)Copyright 1985-2005, American Megatrends, Inc.
Boot Menu 8.5
>
Boot Settings Configuration
>
Boot Device Priority
KT690 Family
during System Boot.
<- Select Screen
|| Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
8.5.1 Boot – Boot Settings Configuration
Quick Boot [Enabled]
Quiet Boot [Disabled]
AddOn ROM Display Mode [Force BIOS]
Bootup Num-Lock [On]
PS/2 Mouse Support [Auto]
Wait for ‘F1’ If Error [Enabled]
Hit ‘DEL’ Message Display [Enabled]
Interrupt 19 Capture [Disabled]
PC Speaker/Beep [Enabled]
Default init boot order [0->4->3->5->2->1]
Force boot Device [Disabled]
during System Boot.
<- Select Screen
|| Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
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Feature
Options
Description
Quick Boot
Enabled
Disabled
Allows BIOS to skip certain test while booting in
order to decrease boot time.
Quiet Boot
Disabled
Enabled
Disabled: Displays normal POST messages.
Enabled: Displays OEM Logo (no POST messages).
AddOn ROM Display Mode
Force BIOS
Keep current
Set display mode for Option ROM.
Bootup Num-Lock
Off
On
Select Power-on state for numlock
PS/2 Mouse Support
Disabled
Auto
Select support for PS/2 Mouse.
Wait for ‘F1’ If Error
(see note)
Disabled
Enabled
Wait for F1 key to be pressed if error occurs.
Hit ‘DEL’ Message Display
Disabled
Enabled
Displays “Press DEL to run Setup” in POST.
Interrupt 19 Capture
Disabled
Enabled
Enabled: Allows option ROMs to trap interrupt 19
PC Speaker/Beep
Disabled
Control the default beeps during boot of the system.
enumeration and (un)plug of USB.
Default init boot order
0->4->3->5->2->1
3->1->0->4->2->5
The numbers in the sequence means:
Force boot Device
Disabled
Network
Does override current boot setting. Device must be
<- Select Screen
|| Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
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BIOS SETUP UTILITY
Chipset
Internal Graphics Configuration
Disabled
V02.59+ (C)Copyright 1985-2005, American Megatrends, Inc.
Feature
Options
Description
Internal Graphics Mode
Disabled
UMA
Disabled
UMA
UMA Frame Buffer Size
Auto
1024MB
auto
1024MB
Primary Video Controller
PCIE/IGFX/PCI
IGFX/PCIE/PCI
PCIE/IGFX/PCI
IGFX/PCIE/PCI
Video Display Devices
Auto
TV + EDFP
Auto
TV Standard
NTSC
Scart_RGB
NTSC
Scart_RGB
Expansion Mode
Enabled
Disabled
Enabled/Disabled Expansion Mode
Internal Graphics Configuration:
Internal Graphics Mode [UMA]
UMA Frame Buffer Size [Auto]
Current UMA Size [128MB]
Primary Video Controller [PCIE/IGFX/PCI]
Video Display Devices [Auto]
TV Standard [NTSC]
Expansion Mode [Disabled]
Replace GFX subid [Enabled]
UMA
<- Select Screen
|| Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
32MB
64MB
128MB
256MB
512MB
PCI/PCIE/IGFX
CRT
LVDS
DVI
EDFP
TV
CRT + LVDS
CRT + DVI
CRT + EDFP
DVI + LVDS
DVI + EDFP
LVDS + EDFP
TV + LVDS
TV + DVI
32MB
64MB
128MB
256MB
512MB
PCI/PCIE/IGFX
CRT: onboard analogue VGA output
LVDS: onboard LVDS output
DVI: onboard DVI output
EDFP: External Digit al Flat Pan el via PCIe car d
TV: onboard TV output (if TV-out version of board)
PAL
PAL-M
PAL-60
NTSC-JAP
PAL-CN
Pal-N
PAL
PAL-M
PAL-60
NTSC-JAP
PAL-CN
Pal-N
KT690 Family
KTD-00738-J
Public
User Manual
Date 2012-06-01
Page
88
BIOS SETUP UTILITY
Chipset
Displays Configuration
Display module V0.04
LVDS [None]
V02.59+ (C)Copyright 1985-2005, American Megatrends, Inc.
Feature
Options
Description
LVDS
None
Select Panel setup
Backlight Signal Inversion
Disabled
Enabled
Select signal Polarity
LCDVCC Voltage
3.3V
5.0V
LVDVCC voltage selection (power sequenced)
TMDS Support
Disabled
Auto
Disabled
Auto
Displays Configuration:
Backlight Signal Inversion [Disabled]
LCDVCC Voltage [3.3V]
TMDS Support [Auto]
<- Select Screen
|| Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
Enabled
Enabled
KT690 Family
KTD-00738-J
Public
User Manual
Date 2012-06-01
Page
89
BIOS SETUP UTILITY
Main Advanced PCIPnP Boot Security Chipset Power Exit
Exit Options
Enable/Disable SMI
V02.59+ (C)Copyright 1985-2005, American Megatrends, Inc.
Feature
Options
Description
Power Management/APM
Disabled
Enabled
Enable/Disable SMI based power management and
APM support
Power Button Mode
Disabled
Suspend
Disabled
Suspend
Restore on AC Power Loss
Power On
Select whether or not to restart the system after AC
loss occurred.
RTC Resume
Disabled
Enabled
RTC to generate a wake event
PME/WOL Enable
Disabled
Enabled
Disabled/Enabled PME to power on system with
Wake on Lan function
PS/2 kbd/Mouse S4/S5 Wake
Disabled
Enabled: System can be waked also from S4 or S5.
S3
Keyboard Wake Hotkey
Any key
“Sleep button”
Any key
“Sleep button”
Power 8.8
Power Management/APM [Enabled]
Power Button Mode [On/Off]
Restore on AC Power Loss [Power On]
RTC Resume [Disabled]
PME/WOL Enable [Disabled]
PS/2 Kbd/Mouse S4/S5 Wake [Disabled]
Keyboard Wake Hotkey [Any key]
based power management
and APM support
<- Select Screen
|| Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
Standby
Power Off
Last state
Enabled
Standby
power loss (ATX +5VSB signal goes high):
Power Off keeps the power off until the power
button is pressed.
Power On restores power to the computer.
Last State use same power state as before power
Disabled: PS/2 KBD/MSE can still wake system from
“SPACE”
“ENTER”
“SPACE”
“ENTER”
KT690 Family
KTD-00738-J
Public
User Manual
Date 2012-06-01
Page
90
BIOS SETUP UTILITY
Main Advanced PCIPnP Boot Security Chipset Exit
Exit Options
Exit system setup
V02.59+ (C)Copyright 1985-2005, American Megatrends, Inc.
Feature
Options
Description
Save Changes and Exit
Ok
Cancel
Exit system setup after saving the changes
Discard Changes and Exit
Ok
Cancel
Exit system setup without saving any changes
Discard Changes
Ok
Cancel
Discards changes done so far to any of the setup
questions
Load Optimal Defaults
Ok
Cancel
Load Optimal Default values for all the setup
questions
Load Failsafe Defaults
Ok
Cancel
Load Failsafe Default values for all the setup
questions
Halt on invalid Time/Date
Enabled
Disabled
Enabled: System halt if incorrect Date & Time.
Secure CMOS
Enabled
Enable will store current CMOS in non volatile ram.
failure etc.)
Exit Menu 8.9
Save Changes and Exit
Discard Changes and Exit
Discard Changes
Load Optimal Defaults
Load Failsafe Defaults
Halt on invalid Time/Date [Enabled]
Secure CMOS [Disabled]
after saving the
changes.
F10 Key can be used
for this operation.
<- Select Screen
|| Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
Disabled
(For protection of CMOS data in case of battery
KT690 Family
KTD-00738-J
Public
User Manual
Date 2012-06-01
Page
91
Number of
Beeps
Description
1
Insert diskette in floppy drive A:
2
‘AMIBOOT.ROM’ file not found in root directory of diskette in A:
3
Base Memory error
4
Flash Programming successful
5
Floppy read error
6
Keyboard controller BAT command failed
7
No Flash EPROM detected
8
Floppy controller failure
9
Boot Block BIOS checksum error
10
Flash Erase error
11
Flash Program error
12
‘AMIBOOT.ROM’ file size error
13
BIOS ROM image mismatch (file layout does not match image present in flash device)
Number of
Beeps
Description
1
Memory refresh timer error.
2
Parity error in base memory (first 64KB block)
3
Base memory read/write test error
4
Motherboard timer not operational
5
Processor error
6
8042 Gate A20 test error (cannot switch to protected mode)
7
General exception error (processor exception interrupt error)
8
Display memory error (system video adapter)
9
AMIBIOS ROM checksum error
10
CMOS shutdown register read/write error
11
Cache memory test failed
Number of
Beeps
Troubleshooting Action
1, 2 or 3
Reseat the memory, or replace with known good modules.
4-7, 9-11
Fatal error indicating a serious problem with the system. Consult your system manufacturer.
the problem happens again. This will reveal the malfunctioning card.
8
If the system video adapter is an add-in card, replace or reseat the video adapter. If the video
adapter is an integrated part of the system board, the board may be faulty.
9. AMI BIOS Beep Codes
Boot Block Beep Codes:
POST BIOS Beep Codes:
Troubleshooting POST BIOS Beep Codes:
Before declaring the motherboard beyond all hope, eliminate the possibility of interference by
a malfunctioning add-in card. Remove all expansion cards except the video adapter.
• If beep codes are generated when all other expansion cards are absent, consult your
system manufacturer’s technical support.
• If beep codes are not generated when all other expansion cards are absent, one of the addin cards is causing the malfunction. Insert the cards back into the system one at a time until
KT690 Family
KTD-00738-J
Public
User Manual
Date 2012-06-01
Page
92
10. O S set up
Use the Setup.exe files for all relevant drivers. The drivers can be found on KT690 Driver CD or they can be
downloaded from the homepage www.kontron.com
Note: P.T. on the web you will now find latest Video XP driver (version 9.11) for the KT690. On ATI
homepage you will find newer drivers, but they do not support KT690.
KT690 Family
KTD-00738-J
Public
User Manual
Date 2012-06-01
Page
93
11. Warranty
KONTRON Technology warrants its products to be free from defects in material and workmanship during the
warranty period. If a product proves to be defective in material or workmanship during the warranty period,
KONTRON Technology will, at its sole option, repair or replace the product with a similar product.
Replacement Product or parts may include remanufactured or refurbished parts or components.
The warranty does not cover:
1. Damage, deterioration or malfunction resulting from:
1.1. Accident, misuse, neglect, fire, water, lightning, or other acts of nature, unauthorized product
modification, or failure to follow instructions supplied with the product.
1.2. Repair or attempted repair by anyone not authorized by KONTRON Technology.
1.3. Causes external to the product, such as electric power fluctuations or failure.
1.4. Normal wear and tear.
1.5. Any other causes which does not relate to a product defect.
2. Removal, installation, and set -up service charges.
Exclusion of damages:
KONTRON TECHNOLOGY LIABILITY IS LIMITED TO THE COST OF REPAIR OR REPLACEMENT OF
THE PRODUCT. KONTRON TECHNOLOGY SHALL NOT BE LIABLE FOR:
1. DAMAGE TO OTHER PROPERTY CAUSED BY ANY DEFECTS IN THE PRODUCT, DAMAGES
BASED UPON INCONVENIENCE, LOSS OF USE OF THE PRODUCT, LOSS OF TIME, LOSS OF
PROFITS, LOSS OF BUSINESS OPPORTUNITY, LOSS OF GOODWILL, INTERFERENCE WITH
BUSINESS RELATIONSHIPS, OR OTHER COMMERCIAL LOSS, EVEN IF ADVISED OF THEIR
POSSIBILITY OF SUCH DAMAGES.
2. ANY OTHER DAMAGES, WHETHER INCIDENTAL, CONSEQUENTIAL OR OTHERWISE.
3. ANY CLAIM AGAINST THE CUSTOMER BY ANY OTHER PARTY.
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