14IPMI and Hot Swap LEDs Function .............................................................45
P R E L I M I N A R Y
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PrefaceCP6003-SA/RA/RC
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P R E L I M I N A R Y
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1.Introduction
1.1Terminology and Acronym Definitions
The following table provides descriptions for terms and acronyms used in this guide. The descriptions are derived primarily from the IPMI specifications.
Table 1:Terminology and Acronym Definitions
TERM or ACRONYMDESCRIPTION
BMCBaseboard Management Controller
Each board is equipped with an IPMI controller acting either as a BMC or as an SMC.
However, in a CompactPCI chassis, there can be only one BMC present. The BMC
administrates the SEL and the SDRR for the complete system. The BMC is connected
to the other boards in the shelf via a dedicated bus (IPMB-0). The CP6003-SA/RA/
RC’s IPMI controller can be configured to operate in SMC mode or in BMC mode via
an IPMI OEM command or an uEFI Shell command. The factory setting is SMC.
BSPBoard Support Package
FRUField Replaceable Unit
Every board is a FRU. The FRU data contains information about the board such as
the part number and the serial number. See PICMG Specification 2.9 for complete
details on the FRU data structure. The free Linux tool “ipmitool” can be used to
update or display the FRU data.
FWHFirmware Hub memory location where a complete uEFI BIOS code is stored.
2
I
C
IPMBIntelligent Platform Management Bus
IPMB-0Intelligent Platform Management Bus which connects all SMCs with the BMC or the
IPMIIntelligent Platform Management Interface
IOLIPMI over LAN. An IPMI controller is accessed via LAN, not IPMB.
KCSKeyboard Controller Style (Interface)
Inter-Integrated Circuit
The dedicated I
shelf manager.
This is the IPMI mandatory interface on the host system (payload) to communicate
with the BMC.
2
C management bus where the BMC and the SMCs communicate.
P R E L I M I N A R Y
MPManagement Power
This powers the BMC or SMC controller.
PICMGPCI Industrial Computer Manufacturer Group
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Table 1:Terminology and Acronym Definitions (Continued)
TERM or ACRONYMDESCRIPTION
PWRPayload Power.
This powers the host side of the board where the application software runs. It is
granted by the BMC or the SMC after all prerequisites are met. Prerequisites can be,
for example, a closed handle switch, power on the backplane etc.
SDRSensor Data Record
This is the IPMI data structure that defines a sensor.
SDRRSensor Data Record Repository
The SDRR is located in the BMC and contains all SDRs of the chassis’ boards that
are administrated. A free Linux utility named “ipmitool” makes a full chassis discovery
and fills the SDRR with the SDRs being found.
SELSystem Event Log
The SEL is located in the BMC and keeps track of all events in the chassis. If an
event occurs on any board, the sensor event is sent through the IPMB bus to the
BMC, which additionally stores its own events as well.
SMBIOSSystem Management BIOS
SMCSatellite Management Controller
Each board is equipped with an IPMI controller acting either as a BMC or as an SMC.
In a CompactPCI chassis, there can be several SMCs. The SMC administrates the
sensor and FRU data of the CP6003-SA/RA/RC and makes it available to the BMC.
Each SMC can be connected to the BMC via a dedicated bus (IPMB-0). The CP6003-
SA/RA/RC’s IPMI controller can be configured to operate in SMC mode or in BMC
mode via an IPMI OEM command or an uEFI Shell command. The factory setting is
SMC.
SMSSystem Management Software (designed to run under the OS)
SOLSerial over LAN
A serial interface is redirected by LAN using the RMCP+ protocol.
P R E L I M I N A R Y
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1.2Related Publications
The following publications contain information relating to this product.
IPMIAddenda, Errata, and Clarifications document revision 4 for IPMI v2.0 rev 1.0
specification
IPMIIntelligent Platform Management Bus Communications Protocol Specification v1.0
Document Revision 1.0, November 1999
IPMIIPMB v1.0 Address Allocation Document Revision 1.0, September 1998
PICMGCompactPCI System Management Specification PICMG 2.9 Rev. 1.0
CompactPCI Hot Swap Specification PICMG 2.1 Rev. 2.0
PICMG® AMC.0 R2.0, Advanced Mezzanine Card Base Specification, Nov. 15, 2006
CP6003-SA/RA/RCCP6003-SA/RA/RC User Guide
CP6003-SA/RA/RC uEFI BIOS User Guide
CP6003-SA/RA/RC Linux Board Support Package
IPMI Tools“ipmitool” documentation: http://ipmitool.sourceforge.net
IPMI ToolsOpenIPMI documentation: http://www.openipmi.sourceforge.net
1.3IPMI Overview
This product fully supports the Intelligent Platform Management Interface a nd PICMG 2.9 R1.0
specifications. All of its IPMI functionality operates under an autonomous management
controller even if the board is held in reset or power-down mode by a management card within
a system designed for high availability.
While the CP6003-SA/RA/RC IPMI implementation is fully compliant with IPMI v2.0 and has
been designed to operate with any system management software (SMS) that respects this
specification, can be easily integrated with the Service Availability Forum-Hardware Platform
Interface (SAF-HPI) specification.
More information about Service Availability can be found on the following website:
http://www.saforum.org/home
IPMI is an extensible and open standard that defines autonomous system monitoring. It is au-
tonomous because every management controller within a CompactPCI chassis monitors its
own sensors and sends critical events through a dedicated bus to the BMC that logs it into a
non-volatile System Event Log (SEL). The CP6003-SA/RA/RC IPMI implementation includes
a device SDR repository module that allows the user's system management software to detect
all system components and build a database of all management controller sensors.
P R E L I M I N A R Y
For further information concerning IPMI refer to the following website:
http://www.intel.com/design/servers/ipmi/
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BMC
IPMB
Address
Fix: 20h
Backplane
SMC
IPMB
Address:
B0h
(1)
SMC
IPMB
Address:
B2h
(1)
SMC
IPMB
Address:
B4h
(1)
SMC
IPMB address for SMC is determined via the location of the slot in the chassis
IPMB
Address:
B6h
SMC
IPMB
Address:
B8h
(1)
(1)
SMC
IPMB
Address:
BAh
(1)
SMC
IPMB
Address:
BCh
(1)
IPMB 0
IPMB 0
(1)
IPMB 1
2.IPMI Setup
2.1IPMI in a CompactPCI Chassis
Kontron's IPMI implementation in the CompactPCI environment is compliant with the PICMG
2.9 R1.0 specification. This specification defines the pinout of the J1 and J2 Comp actPCI connectors as well as the addressing scheme. There should be only one BMC in the chassis, or at
least on the IPMB segment. The BMC may reside either on an CP6003-SA/RA/RC, or on an
external system management card, or in a shelf management controller (ShMC). The specification allows all of these variants. As a BMC in the system slot, the CP6003-SA/RA/RC supports dual-ported IPMB (IPMB-0 to the SMCs and IPMB-1 to the external segments via the
CompactPCI backplane connector in accordance with PICMG 2.9).
To use the IPMI resources in a rack requires an initial setup for IPMI operation. The following
actions must first be performed to achieve operable IPMI functionality.
P R E L I M I N A R Y
2.2IPMI Setup for the CP6003-SA/RA/RC
Initially the default configuration for the IPMI controller of the CP6003-SA/RA/RC is:
•IRQ = none
•MODE = SMC
•IPMB = single-ported.
If this is the required configuration, no further action is required. If the configuration must be
modified, either the kipmi uEFI Shell command or on e of the open tools “ipmitool” or “ipmicmd”
may be used to modify the configuration as required.
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Fur further information on the kipmi uEFI Shell command, refer to the CP6003-SA/RA/RC uEFI
BIOS User Guide. When uEFI BIOS stores the configuration, it creates an “IPMI Device Information Record” entry in the SMBIOS table. This record contains information, among others,
about:
•Type of the supported interface (KCS style)
•Selected interrupt (10, 11 or none).
This information is required by the CP6003-SA/RA/RC payload’s IPMI OS kernel drivers for
Linux during their loading time. After the loading, most available IPMI communications tools
which access the IPMI controller via IPMI OS drivers should work (e.g. “ipmicmd”, “ipmitool”,
etc.).
Now it is possible to use such a tool to issue the Set Firmware Parameters OEM IPMI
command to modify the configuration again. Changing the interrupt number always requires a
uEFI BIOS restart for a correct setup of the SMBIOS table.
2.3IPMI Setup for the Rack
For a working IPMI configuration the SDRR of the BMC must be filled with all sensor data records of all IPMI controllers in the rack. After every system start the BMC uses the SDRR to
initialize all sensors of all boards. The SDRR setup must be done by a management tool e.g.
the open Linux tool “ipmitool”. Then the command is:
ipmitool sdr fill sensors
This will work only if the IPMI controller configured as BMC is addressed. This addressing is
the default if the “ipmitool” is running on the payload side of the board where the BMC is residing.
3.IPMI Controller Hardware
On the CP6003-SA/RA/RC, the IPMI controller is implemented using the NXP ARM7 microcontroller with 512 kB of internal flash and 56 kB of RAM.
An external 64 kB serial EEPROM chip is used for firmware private data and FRU inventory
storage. An additional external 2 MB serial SPI flash is used for redundant firmware image storage.
The IPMI controller implements a local Keyboard Controller Style (KCS) interface (KCS) with
interrupt support for communication with system-side management software and the uEFI BIOS. The IPMB bus is used for interconnection with the BMC or the shelf manager.
IPMI over LAN (IOL) and Serial Over LAN (SOL) are supported on four Ethernet channels
(GbE A – GbE D) of the board. SOL is only available on one Ethernet channel at a time.
P R E L I M I N A R Y
The IPMI controller provides access to various board sensors which permit the monitoring of: