Memory Module Specifications
KVR800D2D4F5K2/8G
8GB (4GB 512M x 72-Bit x 2 pcs.) PC2-6400
CL5 ECC 240-Pin FBDIMM Kit
Description:
ValueRAM's KVR800D2D4F5K2/8G is a kit of two 4GB (512M x 72-bit) PC2-6400 CL5 SDRAM (Synchronous
DRAM) "fully buffered" ECC "dual rank" memory modules. Total kit capacity is 8GB (8192MB). Each module is
based on thirty-six 256M x 4-bit 800MHz DDR2 FBGA components. Each module also includes an AMB device
(Advanced Memory Buffer). The electrical and mechanical specifications are as follows:
Feature:
· FBDIMM Module: 240-pin
· JEDEC Standard: R/C H or E
· Memory Organization: 2 rank of x4 devices
· DDR2 DRAM Interface: SSTL_18
· DDR2 Speed Grade: 800 Mbps
· CAS Latency: 5-5-5
· Module Bandwidth: 6.4 GB/s
· DRAM: VDD = VDDQ = 1.8V
· AMB: VCC = VCCFBD = 1.5V
· EEPROM: VDDSPD = 3.3V (typical)
· Heat Spreader: Full DIMM Heat Spreader (FDHS)
· PCB Height: 30.35mm, double-side
· RoHS Compliant
VALUERAM0640-001.A00 03/13/08 Page 1
DDR2 240-pin FBDIMM Pinout:
TECHNOLOGY
Pin#Front
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 VID1 136 VID0 46
17 RESET 137 DNU/M_Test 47
18
19
20
21
22 PN0 142 SN0 52 PN6 172 SN6 81
23 PN0 143 SN0 53
24
25 PN1 145 SN1 55 PN7 175 SN7 84
26 PN1 146 SN1 56
27
Side
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
RFU
RFU
V
V
V
DD
DD
DD
SS
DD
DD
DD
SS
CC
CC
SS
CC
CC
SS
TT
SS
SS
SS
SS
Pin#Back
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
138
139
**
140
**
141
144
147
Side
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
RFU
RFU
V
V
V
DD
DD
DD
SS
DD
DD
DD
SS
CC
CC
SS
CC
CC
SS
TT
SS
SS
SS
SS
Pin#Front
Side
Pin#Back
Side
Pin#Front
Side
Pin#Back
Side
Pin#Front
Side
31 PN3 151 SN3 61 PN9 181 SN9 91 PS9 211 SS9
32 PN3 152 SN3 62
V
33
153
SS
V
SS
V
PN10
63
182
SS
183
V
SS
SN10
V
92
SS
93 PS5 213 SS5
34 PN4 154 SN4 64 PN10 184 SN10 94 PS5 214 SS5
35 PN4 155 SN4 65
V
36
156
SS
V
SS
V
185
SS
66 PN11 186 SN11 96 PS6 216 SS6
V
SS
V
95
SS
37 PN5 157 SN5 67 PN11 187 SN11 97 PS6 217 SS6
38 PN5 158 SN5 68
V
39
159
SS
V
SS
40 PN13 160 SN13 69
V
188
SS
KEY 99 PS7 219 SS7
V
189
SS
41 PN13 161 SN13 70 PS0 190 SS0 101
V
42
43
162
SS
V
163
SS
V
SS
V
SS
71 PS0 191 SS0 102 PS8 222 SS8
V
72
192
SS
44 RFU* 164 RFU* 73 PS1 193 SS1 104
45 RFU* 165 RFU* 74 PS1 194 SS1 105
V
166
SS
V
167
SS
V
SS
V
SS
V
75
195
SS
76 PS2 196 SS2 107
48 PN12 168 SN12 77 PS2 197 SS2 108
49 PN12 169 SN12 78
**
V
50
**
170
SS
V
SS
V
198
SS
79 PS3 199 SS3 110
51 PN6 171 SN6 80 PS3 200 SS3 111
V
V
173
SS
V
SS
82 PS4 202 SS4 113
201
SS
54 PN7 174 SN7 83 PS4 203 SS4 114
V
V
176
SS
V
SS
V
85
204
SS
205
SS
57 PN8 177 SN8 86 RFU* 206 RFU* 117
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
98
SS
100 PS7 220 SS7
V
SS
103 PS8 223 SS8
V
SS
RFU
**
106
RFU
**
V
SS
V
DD
V
109
112
115
116
DD
V
SS
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
TT
Pin#Back
Side
212
215
218
221
224
225
226
227
228 SCK
229 SCK
230
231
232
233
234
235
236
237
V
V
V
V
V
RFU
RFU
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
SS
DD
DD
TT
28 PN2 148 SN2 58 PN8 178 SN8 87 RFU* 207 RFU* 118 SA2 238 VDDSPD
29 PN2
V
30
SS
149 SN2 59
150
V
SS
V
179
SS
60 PN9 180 SN9 89
V
SS
V
88
V
208
SS
209
SS
90 PS9 210
V
SS
V
SS
SS9
119 SDA 239 SA0
120 SCL 240 SA1
RFU = Reserved Future Use.
* These pin positions are reserved for forwarded clocks to be used in future module implementations
** These pin positions are reserved for future architecture flexibility
1) The following signals are CRC bits and thus appear out of the normal sequence: PN12/PN12
PS9/PS9
, SS9/SS9
, SN12/SN12, PN13/PN13, SN13/SN13,
**
**
VALUERAM0640-001.A00 Page 2
DIMM Connector Pin Description:
Pin Name Pin Description Count
SCK
SCK
System Clock Input, positive line
System Clock Input, negative line
PN[13:0] Primary Northbound Data, positive lines 14
[13:0] Primary Northbound Data, negative lines 14
PN
PS[9:0] Primary Southbound Data, positive lines 10
[9:0] Primary Southbound Data, negative lines 10
PS
SN[13:0] Secondary Northbound Data, positive lines 14
[13:0] Secondary Northbound Data, negative lines 14
SN
SS[9:0] Secondary Southbound Data, positive lines 10
[9:0] Secondary Southbound Data, negative lines 10
SS
SCL Serial Presence Detect (SPD) Clock Input 1
SDA SPD Data Input / Output 1
SA[2:0] SPD Address Inputs, also used to select the DIMM number in the AMB 3
VID[1:0]
RESET
RFU
V
CC
V
DD
V
TT
V
DDSPD
V
SS
Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered DIMMs
VID[0] is V
value: OPEN = 1.8 V, GND = 1.5 V; VID[1] is VCC value: OPEN = 1.5 V, GND = 1.2 V
DD
AMB reset signal 1
Reserved for Future Use
AMB Core Power and AMB Channel Interface Power (1.5 Volt) 8
DRAM Power and AMB DRAM I/O Power (1.8 Volt) 24
DRAM Address/Command/Clock Termination Power (VDD/2)
SPD Power 1
Ground 80
The DNU/M_Test pin provides an exter nal connection on R/Cs A-D for testing
the margin of Vref which is produced by a voltage divider on the module. It
DNU/M_Test
is not intended to be used in normal system operation and must not be
connected (DNU) in a system. This test pin may have other features on future card designs
and if it does, will be included in this specification at that time.
1
Total 240
1. System Clock Signals SCK and SCK
switch at one half the DRAM CK/CK frequency
2. Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility
1
1
2
TECHNOLOGY
1
1
2
16
4
1
Absolute Maximum Ratings
Symbol Parameter MIN MAX Units
V
IN
, V
CC
V
V
DD
V
TT
T
STG
T
CASE
Voltage on any pin relative to V
OUT
Voltage on VCC pin relative to V
Vol tag e VDD pin relative to Vss
Voltage on VTT pin relative to V
Storage temperature
DDR2 SDRAM device operating temperature (Ambient)
SS
SS
SS
AMB device operating temperature (Ambient)
Note: (1) Above 85°C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
VALUERAM0640-001.A00 Page 3
-0.3 1.75 V
-0.3 1.75 V
-0.5 2.3 V
-0.5 2.3 V
-55 100 °C
095°C
95
(1)
0110°C
Functional Block Diagram:
VSS
S1
S0
DQS0
DQS0
DQ0
DQ1
DQ2
DQ3
DQS1
DQS1
DQ8
DQ9
DQ10
DQ11
DQS2
DQS2
DQ16
DQ17
DQ18
DQ19
DQS3
DQS3
DQ24
DQ25
DQ26
DQ27
DQS4
DQS4
DQ32
DQ33
DQ34
DQ35
DQS5
DQS5
DQ40
DQ41
DQ42
DQ43
DQS6
DQS6
DQ48
DQ49
DQ50
DQ51
DQS7
DQS7
DQ56
DQ57
DQ58
DQ59
DQS8
DQS8
CB0
CB1
CB2
CB3
PN0-PN13
PN
0-PN13
PS0-PS9
PS
0-PS9
SCL
SDA
SA1-SA2
SA0
RESET
SCK/SCK
DM
DM
DM
DM
DM
DM
825
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
A
M
B
DQS
CS
D0
DQS
CS
D1
DQS
CS
D2
DQS
CS
D3
DQS
CS
D4
DQS
CS
D5
DQS
CS
D6
DQS
CS
D7
DQS
CS
D8
SN0-SN13
0-SN13
SN
SS0-SS9
0-SS9
SS
0 -> CS (D0-D17)
S
CKE0 -> CKE (D0-D17)
1 -> CS (D18-D35)
S
CKE1 -> CKE (D18-D35)
ODT -> ODT0 (all SDRAMs)
BA0-BA2 (all SDRAMs)
A0-A15 (all SDRAMs)
(all SDRAMs)
RAS
CAS
(all SDRAMs)
WE
(all SDRAMs)
CK/CK
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
(all SDRAMs)
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
D18
CS
D19
CS
D20
CS
D21
CS
D22
CS
D23
CS
D24
CS
D25
CS
D26
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
All address/command/control/clock
SCL
WP
Notes:
1
. DQ-to-I/O wiring may be changed within a nibble
2. There are two physical copies of each address/command/control
3. There are four physical copies of each clock
DQS9
DQS9
DQS10
DQS10
DQS11
DQS11
DQS12
DQS12
DQS13
DQS13
DQS14
DQS14
DQS15
DQS15
DQS16
DQS16
DQS17
DQS17
Serial PD
A0
A1
SA0 SA1
DQ4
DQ5
DQ6
DQ7
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQ30
DQ31
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQ46
DQ47
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQ62
DQ63
CB4
CB5
CB6
CB7
A2
SA2
TECHNOLOGY
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
33
V
TT
SDA
CS
D9
CS
D10
CS
D11
CS
D12
CS
D13
CS
D14
CS
D15
CS
D16
CS
D17
V
V
V
V
V
V
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
TT
CC
DDSPD
DD
REF
SS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS
CS
D27
DQS
CS
D28
DQS
CS
D29
DQS
CS
D30
DQS
CS
D31
DQS
CS
D32
DQS
CS
D33
DQS
CS
D34
DQS
CS
D35
Terminators
AMB
SPD, AMB
D0-D35, AMB
D0-D35
D0-D35, SPD,
AMB
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
VALUERAM0640-001.A00 Page 4
Architecture:
Advanced Memory Buffer Pin Description:
Pin Name Pin Description Count
TECHNOLOGY
FB-DIMM Channel Signals
SCK System Clock Input, positive line 1
SCK
PN[13:0] Primary Northbound Data, positive lines 14
[13:0] Primary Northbound Data, negative lines 14
PN
PS[9:0] Primary Southbound Data, positive lines 10
[9:0] Primary Southbound Data, negative lines 10
PS
SN[13:0] Secondary Northbound Data, positive lines 14
[13:0] Secondary Northbound Data, negative lines 14
SN
SS[9:0] Secondary Southbound Data, positive lines 10
[9:0] Secondary Southbound Data, negative lines 10
SS
FBDRES To an external precision calibration resistor connected to Vcc 1
System Clock Input, negative line 1
DDR2 Interface Signals
DQS[8:0] Data Strobes, positive lines 9
[8:0] Data Strobes, negative lines 9
DQS
DQS[17:9]/DM[8:0] Data Strobes (x4 DRAM only), positive lines. These signals are driven low to x8 DRAM on writes. 9
[17:9] Data Strobes (x4 DRAM only), negative lines 9
DQS
DQ[63:0] Data 64
CB[7:0] Checkbits 8
A[15:0]A, A[15:0]B Addresses. A10 is part of the pre-charge command 32
BA[2:0]A, BA[2:0]B Bank Addresses 6
A, RASB Part of command, with CAS, WE, and CS[1:0]. 2
RAS
A, CASB Part of command, with RAS, WE, and CS[1:0]. 2
CAS
A, WEB Part of command, with RAS, CAS, and CS[1:0]. 2
WE
ODTA, ODTB On-die Termination Enable 2
CKE[1:0]A, CKE[1:0]B Clock Enable (one per rank) 4
[1:0]A, CS[1:0]B Chip Select (one per rank) 4
CS
CLK[3:0]
CLK
[3:0] Negative lines for CLK[3:0] 4
DDRC_C14 DDR Compensation: Common return pin for DDRC_B18 and DDRC_C18. 1
DDRC_B18 DDR Compensation: Resistor connected to common return pin DDRC_C14 1
DDRC_C18 DDR Compensation: Resistor connected to common return pin DDRC_C14 1
DDRC_B12
DDRC_C12
CLK[1:0] used on 9 and 18 device DIMMs, CLK[3:0] used on 36 device DIMMs. CLK[3:2] should be output disabled when not in use.
DDR Compensation: Resistor connected to V
DDR Compensation: Resistor connected to V
SS
DD
99
175
4
1
1
VALUERAM0640-001.A00 Page 5
Advanced Memory Buffer Pin Description:
TECHNOLOGY
SPD Bus Interface Signals
SCL Serial Presence Detect (SPD) Clock Input 1
SDA SPD Data Input / Output 1
SA[2:0] SPD Address Inputs, also used to select the DIMM number in the AMB 3
Miscellaneous Signals
PLLTSTO PLL Clock Observability Output 1
VCCAPLL Analog VCC for the PLL. Tied with low pass filter to VCC. 1
VSSAPLL Analog VSS for the PLL. Tied to ground on the AMB die. Do not tie to ground on the DIMM. 1
TEST_pin# Leave floating on the DIMM 6
TESTLO_pin#
BFUNC Tie to ground to set functionality as buffer on DIMM. 1
RESET
NC
RFU Reserved for Future Use 18
Tie to ground on the DIMM
AMB reset signal 1
No connect. Many NC are connected to VDD on the DIMM, to lower the impedance of the VDD power
islands.
2
Power/Ground Signals
V
V
CCFBD
V
V
DDSPD
V
CC
DD
SS
AMB Core Power (1.5 Volt) 24
AMB Channel I/O Power (1.5 Volt) 8
AMB DRAM I/O Power (1.8 Volt) 24
SPD Power (3.3 Volt) 1
Ground 156
5
163
5
129
213
Total 655
1. System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency.
2. TESTLO_AB20 and TESTLO_AC20 should be configured for debug purposes on prototype DIMMs: each pin should have a zero
ohm resistor pulldown to ground, and an unpopulated resistor pullup to VCC. These resistors can be replaced on production
DIMMs with a direct connection to ground.
VALUERAM0640-001.A00 Page 6
Package Dimensions:
TECHNOLOGY
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
FBGA DDR2
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
(Units = millimeters)
SDRAM
SDRAM
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
Advanced Memory Buffer
AMB
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
TECHNOLOGY
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
SDRAM
FBGA DDR2
0.346 (8.8)
MAX with heat sink
Units: inches (millimeters)
45°x 0.0071(0.18)
0.042 (1.06)
0.042 (1.06)
Detail A
0.054 (1.37)
0.046 (1.17)
0.047 (1.19)
VALUERAM0640-001.A00 Page 7
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