Kingston KVR667D2S4F5-2G User Manual

Memory Module Specications

KVR667D2S4F5/2G

2GB 256M x 72-Bit PC2-5300
CL5 ECC 240-Pin FBDIMM

DESCRIPTION

This document describes ValueRAM’s 2GB (256M x 72-bit)

PC2-5300 CL5 SDRAM (Synchronous DRAM) “fully buffered”

ECC “single rank” memory module. This module is based on

eighteen 256M x 4-bit 667MHz DDR2 FBGA components.

The module also includes an AMB device (Advanced Memory

Buffer). The electrical and mechanical specications are

as follows:

SPECIFICATIONS

· FBDIMM Module 240-pin

· JEDEC Standard R/C H

· Memory Organization 2 rank of x4 devices

· DDR2 DRAM Interface SSTL_18

· DDR2 Speed Grade 667 Mbps

· CAS Latency 5-5-5

· Module Bandwidth 5.3 GB/s

· FBDIMM Channel 8.0 GB/s
Peak Throughput

· DRAM VDD = VDDQ = 1.8V

· AMB VCC = VCCFBD = 1.5V

· EEPROM VDDSPD = 3.3V (typical)

· Heat Spreader FDHS

· PCB Height 30.35mm, double-side

Continued >>

Kingston.com Document No. VALUERAM0547-001.A00 03/16/07 Page 1

continued ValueRAM

DDR2 240-pin FBDIMM Pinout:

Pin#Front

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Side

V

DD

V

DD

V

DD

V

SS

V

DD

V

DD

V

DD

V

SS

V

CC

V

CC

V

SS

V

CC

V

CC

V

SS

V

TT

Pin#Back

Side

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

V

DD

V

DD

V

DD

V

SS

V

DD

V

DD

V

DD

V

SS

V

CC

V

CC

V

SS

V

CC

V

CC

V

SS

V

TT

Pin#Front

31 PN3151 SN361PN9 181SN9 91 PS9 211SS9

32 PN3 152SN3 62

33

34 PN4154 SN464PN10 184SN10 94 PS5 214SS5

35 PN4 155SN4 65

36

37 PN5157 SN567PN11 187SN11 97 PS6 217SS6

38 PN5 158SN5 68

39

40 PN13160 SN13 69

41 PN13 161SN13 70 PS0190 SS0101

42

43

44 RFU* 164RFU*73PS1 193SS1 104

45 RFU*165 RFU* 74 PS1 194 SS1 105

16 VID1 136VID046

17 RESET 137 DNU/M_Test 47

V

18

19

20

21

RFU

RFU

V

138

SS

139

**

140

**

141

SS

V

RFU

RFU

V

SS

SS

48 PN12168 SN12 77 PS2 197 SS2 108

49 PN12 169SN12 78

**

50

**

51 PN6171 SN680PS3 200 SS3 111

22 PN0142 SN052PN6 172SN6 81

23 PN0 143SN0 53

V

24

144

SS

V

SS

54 PN7174 SN783PS4 203 SS4 114

25 PN1145 SN155PN7 175SN7 84

26 PN1 146SN1 56

V

27

147

SS

V

SS

57 PN8177 SN886RFU*206 RFU*117

28 PN2148 SN258PN8 178SN8 87 RFU*207 RFU* 11 8SA2 238 VDDSPD

29 PN2

30

149SN2 59

V

150

SS

V

SS

60 PN9180 SN989

RFU = Reserved Future Use.
* These pin positions are reserved for forwarded clocks to be used in future module implementations
** These pin positions are reserved for future architecture flexibility

1) The following signals are CRC bits and thus appear out of the normal sequence: PN12/PN12
PS9/PS9

, SS9/SS9

Side

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

Pin#Back

Side

153

156

159

162

163

166

167

170

173

176

179

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

Pin#Front

Side

V

PN10

63

V

SS

SS

Pin#Back

Side

182

183

185

V

SS

SN10

V

SS

Pin#Front

Side

92

V

SS

Pin#Back

Side

212

V

93 PS5213 SS5

V

95

215

SS

V

66 PN11 186SN1196PS6 216SS6

V

188

SS

V

SS

V

98

218

SS

V

KEY 99 PS7219 SS7

V

189

SS

V

100PS7 220SS7

SS

V

SS

221

V

71 PS0 191 SS0 102PS8 222SS8

V

72

V

75

192

SS

195

SS

76 PS2196 SS2107

V

198

SS

79 PS3199 SS3110

V

201

SS

82 PS4202 SS4113

V

V

85

V

88

V

204

SS

205

SS

208

SS

209

SS

90 PS9210

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

SS9

103PS8 223SS8

106

109

112

115

116

V

RFU

RFU

V

V

V

V

V

V

V

V

V

V

V

SS

**

**

SS

DD

DD

SS

DD

DD

DD

SS

DD

DD

TT

224

225

226

227

228SCK

229SCK

230

231

232

233

234

235

236

237

V

RFU

RFU

V

V

V

V

V

V

V

V

V

119SDA 239SA0

120SCL 240SA1

, SN12/SN12, PN13/PN13, SN13/SN13,

SS

SS

SS

SS

SS

**

**

SS

SS

DD

DD

DD

SS

DD

DD

TT

Continued >>

Kingston.com Document No. VALUERAM0547-001.A00 03/16/07 Page 2

continued ValueRAM

DIMM Connector Pin Description:

Pin Name Pin Description Count

SCK

SCK

System Clock Input, positive line

System Clock Input, negative line

PN

PS

SN

SS

SDA SPD Data Input / Output 1

VID[1:0]

RESET

RFU

V

CC

V

DD

V

TT

V

DDSPD

V

SS

Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered DIMMs

VID[0] is V

value: OPEN = 1.8 V, GND = 1.5 V; VID[1] is VCC value: OPEN = 1.5 V, GND = 1.2 V

DD

AMB reset signal 1

Reserved for Future Use

DRAM Address/Command/Clock Termination Power (VDD/2)

SPD Power 1

Ground 80

The DNU/M_Test pin provides an exter nal connection on R/Cs A-D for testing

the margin of Vref which is produced by a voltage divider on the module. It

DNU/M_Test

is not intended to be used in normal system operation and must not be

connected (DNU) in a system. This test pin may have other features on future card designs

and if it does, will be included in this specification at that time.

1

Total 240

1. System Clock Signals SCK and SCK

switch at one half the DRAM CK/CK frequency

2. Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility

1

1

1

1

41senil evitisop ,ataD dnuobhtroN yramirP]0:31[NP

41senil evitagen ,ataD dnuobhtroN yramirP]0:31[

01senil evitisop ,ataD dnuobhtuoS yramirP]0:9[SP

01senil evitagen ,ataD dnuobhtuoS yramirP]0:9[

41senil evitisop ,ataD dnuobhtroN yradnoceS]0:31[NS

41senil evitagen ,ataD dnuobhtroN yradnoceS]0:31[

01senil evitisop ,ataD dnuobhtuoS yradnoceS]0:9[SS

01senil evitagen ,ataD dnuobhtuoS yradnoceS]0:9[

1tupnI kcolC )DPS( tceteD ecneserP laireSLCS

3BMA eht ni rebmun MMID eht tceles ot desu osla ,stupnI sserddA DPS]0:2[AS

2

2

16

8)tloV 5.1( rewoP ecafretnI lennahC BMA dna rewoP eroC BMA

42)tloV 8.1( rewoP O/I MARD BMA dna rewoP MARD

4

1

Continued >>

Kingston.com Document No. VALUERAM0547-001.A00 03/16/07 Page 3

continued ValueRAM

Functional Block Diagram:

VSS

S0

DQS0
DQS0

DQS1

DQS1

DQS2
DQS2

DQ16
DQ17
DQ18
DQ19

DQS3
DQS3

DQ24
DQ25
DQ26
DQ27

DQS4
DQS4

DQ32
DQ33
DQ34
DQ35

DQS5

DQS5

DQ40
DQ41
DQ42
DQ43

DQS6

DQS6

DQS7

DQS7

DQ56
DQ57
DQ58
DQ59

DQS8

DQS8

PN0-PN13
PN

0-PN13

PS0-PS9

0-PS9

PS

DQ0-DQ63

CB0-CB7
DQS0-DQS17
DQS

0-DQS17

SCL
SDA

SA1-SA2

SA0

RESET

SCK/SCK

DQ0
DQ1
DQ2
DQ3

DQ8
DQ9
DQ10
DQ11

DQ48
DQ49
DQ50
DQ51

CB0
CB1
CB2
CB3

DQS9

DM

I/O 0
I/O 1
I/O 2
I/O 3

DM

I/O 0
I/O 1
I/O 2
I/O 3

DM

I/O 0
I/O 1
I/O 2
I/O 3

DM

I/O 0
I/O 1
I/O 2
I/O 3

DM

I/O 0
I/O 1
I/O 2
I/O 3

DM

I/O 0

I/O 1
I/O 2
I/O 3

DM

I/O 0
I/O 1
I/O 2
I/O 3

DM

I/O 0
I/O 1
I/O 2
I/O 3

DM

I/O 0
I/O 1
I/O 2
I/O 3

A

M

B

DQS

DQS

CS

D0

DQS

DQS

CS

D1

DQS

DQS

CS

D2

DQS

DQS

CS

D3

DQS

DQS

CS

D4

DQS

DQS

CS

D5

DQS

DQS

CS

D6

DQS

DQS

CS

D7

DQS

DQS

CS

D8

SN0-SN13
SN

0-SN13
SS0-SS9
SS

0-SS9

0 -> CS (all SDRAMs)

S
CKE0 -> CKE (all SDRAMs)

ODT -> ODT (all SDRAMs)
BA0-BA2 (all SDRAMs)
A0-A15 (all SDRAMs)
RAS

(all SDRAMs)

CAS

(all SDRAMs)

WE

(all SDRAMs)

CK/CK

(all SDRAMs)

DQS9

DQS10
DQS10

DQ12
DQ13
DQ14
DQ15

DQS11
DQS11

DQ20
DQ21
DQ22
DQ23

DQS12
DQS12

DQ28
DQ29
DQ30
DQ31

DQS13
DQS13

DQ36
DQ37
DQ38
DQ39

DQS14
DQS14

DQ44
DQ45
DQ46
DQ47

DQS15

DQS15

DQ52
DQ53
DQ54
DQ55

DQS16
DQS16

DQ60
DQ61
DQ62
DQ63

DQS17
DQS17

DQ4
DQ5
DQ6
DQ7

CB4
CB5
CB6
CB7

DM

I/O 0
I/O 1
I/O 2
I/O 3

DM

I/O 0
I/O 1
I/O 2
I/O 3

DM

I/O 0
I/O 1
I/O 2
I/O 3

DM

I/O 0
I/O 1
I/O 2
I/O 3

DM

I/O 0
I/O 1
I/O 2
I/O 3

DM

I/O 0
I/O 1
I/O 2
I/O 3

DM

I/O 0
I/O 1
I/O 2
I/O 3

DM

I/O 0
I/O 1
I/O 2
I/O 3

DM

I/O 0
I/O 1
I/O 2
I/O 3

CS

D9

D10

D11

D12

D13

D14

D15

D16

D17

DQS

DQS

DQS

DQS

CS

DQS

DQS

CS

V

TT

V

CC

V

DDSPD

V

DD

V

REF

V

SS

SCL

All address/command/control/clock

DQS

DQS

CS

DQS

DQS

CS

DQS

DQS

CS

DQS

DQS

CS

DQS

DQS

CS

DQS

DQS

CS

Notes:

. DQ-to-I/O wiring may be changed within a nibble.

1

2. There are two physical copies of each address/command/control/clock

WP

Serial PD

A0

A1

SA0SA1

A2

SA2

Terminators

AMB

SPD, AMB

D0-D17, AMB

D0-D17

D0-D17,SPD,
AMB

SDA

V

TT

Continued >>

Kingston.com Document No. VALUERAM0547-001.A00 03/16/07 Page 4

continued ValueRAM

Architecture:

.9

Advanced Memory Buffer Pin Description:

Pin Name Pin Description Count

SCK

PN

PS

SN

SS

FBDRESTo an external precision cali 1ccV ot detcennoc rotsiser noitarb

DQS[8:0] Data Strobes, positive lines 9

DQS

DQS[17:9]/DM[8:0]Data Strobes (x4 DRAM only), positive lines. These signals are driven low to x8 DRAM on writes

DQS

DQ[63:0]Data 64

CB[7:0]Checkbits 8

BA[2:0]A, BA[2:0]BBank Addresses 6

RAS

A, RASBPart of command, with CAS, WE, and CS 2.]0:1[

CAS

A, CASBPart of command, with RAS, WE, and CS 2.]0:1[

WE

A, WEBPart of command, with RAS, CAS, and CS 2.]0:1[

ODTA, ODTBOn-die Termination Enable 2

CKE[1:0]A, CKE[1:0]BClock Enable (one per rank) 4

[1:0]A, CS[1:0]BChip Select (one per rank) 4

CS

CLK[3:0]

CLK[3:0] Negative lines for CLK[3:0] 4

DDRC_B12

DDRC_C12

FB-DIMM Channel Signals

DDR2 Interface Signals

[8:0] Data Strobes, negative lines 9

CLK[1:0] used on 9 and 18 device DIMMs, CLK[3:0] used on 36 device DIMMs. CLK[3:2] should be out­put disabled when not in use.

DDR Compensation: Resistor connected to V

DDR Compensation: Resistor connected to V

SS

DD

99

1enil evitisop ,tupnI kcolC metsySKCS

1enil evitagen ,tupnI kcolC metsyS

41senil evitisop ,ataD dnuobhtroN yramirP]0:31[NP

41senil evitagen ,ataD dnuobhtroN yramirP]0:31[

01senil evitisop ,ataD dnuobhtuoS yramirP]0:9[SP

01senil evitagen ,ataD dnuobhtuoS yramirP]0:9[

41senil evitisop ,ataD dnuobhtroN yradnoceS]0:31[NS

41senil evitagen ,ataD dnuobhtroN yradnoceS]0:31[

01senil evitisop ,ataD dnuobhtuoS yradnoceS]0:9[SS

01senil evitagen ,ataD dnuobhtuoS yradnoceS]0:9[

175

9senil evitagen ,)ylno MARD 4x( sebortS ataD]9:71[

23dnammoc egrahc-erp eht fo trap si 01A .sesserddAB]0:51[A ,A]0:51[A

4

1.81C_CRDD dna 81B_CRDD rof nip nruter nommoC :noitasnepmoC RDD41C_CRDD

141C_CRDD nip nruter nommoc ot detcennoc rotsiseR :noitasnepmoC RDD81B_CRDD

141C_CRDD nip nruter nommoc ot detcennoc rotsiseR :noitasnepmoC RDD81C_CRDD

1

1

Continued >>

Kingston.com Document No. VALUERAM0547-001.A00 03/16/07 Page 5

continued ValueRAM

Advanced Memory Buffer Pin Description:

SPD Bus Interface Signals

SDA SPD Data Input / Output 1

Miscellaneous Signals

PLLTSTOP LL Clock Observability Output 1

VSSAPLLA nalog VSS for the PLL. Tied to ground on the AMB die. Do not tie to ground on the DIMM.1

TEST_pin# Leave floating on the DIMM 6

TESTLO_pin#

RESET

NC

RFUR eserved for Future Use 18

Tie to ground on the DIMM

AMB reset signal 1

No connect. Many NC are connected to VDD on the DIMM, to lower the impedance of the VDD power
islands.

2

Power/Ground Signals

V

V

CCFBD

V

V

DDSPD

V

CC

DD

SS

AMB Core Power (1.5 Volt) 24

SPD Power (3.3 Volt) 1

Ground 156

5

1tupnI kcolC )DPS( tceteD ecneserP laireSLCS

3BMA eht ni rebmun MMID eht tceles ot desu osla ,stupnI sserddA DPS]0:2[AS

163

1.CCV ot retlif ssap wol htiw deiT .LLP eht rof CCV golanALLPACCV

5

1”.MMID no reffub“ sa ytilanoitcnuf tes ot dnuorg ot eiTCNUFB

129

213

8)tloV 5.1( rewoP O/I lennahC BMA

42)tloV 8.1( rewoP O/I MARD BMA

System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency.

556 latoT

Continued >>

Kingston.com Document No. VALUERAM0547-001.A00 03/16/07 Page 6

continued ValueRAM

Package Dimensions :

AMB

Advanced Memory Buffer

(Units = millimeters)

0.346 (8.8)

MAX with heat sink

Units: inches (millimeters)

45°x 0.0071(0.18)

0.042 (1.06)

0.042 (1.06)

Detail A

0.054 (1.37)

0.046 (1.17)

0.047 (1.19)

Kingston.com Document No. VALUERAM0547-001.A00 03/16/07 Page 7