Kingston KVR667D2Q8F5-4G User Manual
Memory Module Specications
KVR667D2Q8F5/4G
4GB 512M x 72-Bit PC2-5300
CL5 ECC 240-Pin FBDIMM
DESCRIPTION
This document describes ValueRAM’s 4GB (512M x 72-bit)
PC2-5300 CL5 SDRAM (Synchronous DRAM) fully buffered
ECC quad rank memory module. This module is based on
thirty-six 128M x 8-bit 667MHz DDR2 FBGA components.
The module also includes an AMB device (Advanced Memory
Buffer). The electrical and mechanical specications are
as follows:
SPECIFICATIONS
· FBDIMM Module 240-pin
· JEDEC Standard
· Memory Organization 4 rank of x8 devices
· DDR2 DRAM Interface SSTL_18
· DDR2 Speed Grade 667 Mbps
· CAS Latency 5-5-5
· Module Bandwidth 5.3 GB/s
· DRAM VDD = VDDQ = 1.8V
· AMB VCC = VCCFBD = 1.5V
· EEPROM VDDSPD = 3.3V (typical)
· Heat Spreader Full DIMM Heat Spreader (FDHS)
· PCB Height 30.35mm, double-side
· RoHS Compliant
Continued >>
Kingston.com Document No. VALUERAM0617-001.B00 07/22/09 Page 1
continued ValueRAM
DDR2 240-pin FBDIMM Pinout:
Pin#Front
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Side
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
SS
V
CC
V
CC
V
SS
V
CC
V
CC
V
SS
V
TT
Pin#Back
Side
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
SS
V
CC
V
CC
V
SS
V
CC
V
CC
V
SS
V
TT
Pin#Front
31 PN3151 SN361PN9 181SN9 91 PS9 211SS9
32 PN3 152SN3 62
33
34 PN4154 SN464PN10 184SN10 94 PS5 214SS5
35 PN4 155SN4 65
36
37 PN5157 SN567PN11 187SN11 97 PS6 217SS6
38 PN5 158SN5 68
39
40 PN13160 SN13 69
41 PN13 161SN13 70 PS0190 SS0101
42
43
44 RFU* 164RFU*73PS1 193SS1 104
45 RFU*165 RFU* 74 PS1 194 SS1 105
16 VID1 136VID046
17 RESET 137 DNU/M_Test 47
V
18
19
20
21
RFU
RFU
V
138
SS
139
**
140
**
141
SS
V
RFU
RFU
V
SS
SS
48 PN12168 SN12 77 PS2 197 SS2 108
49 PN12 169SN12 78
**
50
**
51 PN6171 SN680PS3 200 SS3 111
22 PN0142 SN052PN6 172SN6 81
23 PN0 143SN0 53
V
24
144
SS
V
SS
54 PN7174 SN783PS4 203 SS4 114
25 PN1145 SN155PN7 175SN7 84
26 PN1 146SN1 56
V
27
147
SS
V
SS
57 PN8177 SN886RFU*206 RFU*117
28 PN2148 SN258PN8 178SN8 87 RFU*207 RFU* 11 8SA2 238 VDDSPD
29 PN2
30
149SN2 59
V
150
SS
V
SS
60 PN9180 SN989
RFU = Reserved Future Use.
* These pin positions are reserved for forwarded clocks to be used in future module implementations
** These pin positions are reserved for future architecture flexibility
1) The following signals are CRC bits and thus appear out of the normal sequence: PN12/PN12
PS9/PS9
, SS9/SS9
Side
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
Pin#Back
Side
153
156
159
162
163
166
167
170
173
176
179
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
Pin#Front
Side
V
PN10
63
V
SS
SS
Pin#Back
Side
182
183
185
V
SS
SN10
V
SS
Pin#Front
Side
92
V
SS
Pin#Back
Side
212
V
93 PS5213 SS5
V
95
215
SS
V
66 PN11 186SN1196PS6 216SS6
V
188
SS
V
SS
V
98
218
SS
V
KEY 99 PS7219 SS7
V
189
SS
V
100PS7 220SS7
SS
V
SS
221
V
71 PS0 191 SS0 102PS8 222SS8
V
72
V
75
192
SS
195
SS
76 PS2196 SS2107
V
198
SS
79 PS3199 SS3110
V
201
SS
82 PS4202 SS4113
V
V
85
V
88
V
204
SS
205
SS
208
SS
209
SS
90 PS9210
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SS9
103PS8 223SS8
106
109
112
115
116
V
RFU
RFU
V
V
V
V
V
V
V
V
V
V
V
SS
**
**
SS
DD
DD
SS
DD
DD
DD
SS
DD
DD
TT
224
225
226
227
228SCK
229SCK
230
231
232
233
234
235
236
237
V
RFU
RFU
V
V
V
V
V
V
V
V
V
119SDA 239SA0
120SCL 240SA1
, SN12/SN12, PN13/PN13, SN13/SN13,
SS
SS
SS
SS
SS
**
**
SS
SS
DD
DD
DD
SS
DD
DD
TT
Continued >>
Kingston.com Document No. VALUERAM0617-001.B00 07/22/09 Page 2
continued ValueRAM
DIMM Connector Pin Description:
5°
Pin Name Pin Description Count
SCK
SCK
System Clock Input, positive line
System Clock Input, negative line
PN
PS
SN
SS
SDA SPD Data Input / Output 1
VID[1:0]
RESET
RFU
V
CC
V
DD
V
TT
V
DDSPD
V
SS
DNU/M_Test
1. System Clock Signals SCK and SCK
2. Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility
Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered DIMMs
VID[0] is V
value: OPEN = 1.8 V, GND = 1.5 V; VID[1] is VCC value: OPEN = 1.5 V, GND = 1.2 V
DD
AMB reset signal 1
Reserved for Future Use
DRAM Address/Command/Clock Termination Power (VDD/2)
SPD Power 1
Ground 80
The DNU/M_Test pin provides an exter nal connection on R/Cs A-D for testing
the margin of Vref which is produced by a voltage divider on the module. It
is not intended to be used in normal system operation and must not be
connected (DNU) in a system. This test pin may have other features on future card designs
and if it does, will be included in this specification at that time.
1
Total 240
1
1
2
switch at one half the DRAM CK/CK frequency
1
1
41senil evitisop ,ataD dnuobhtroN yramirP]0:31[NP
41senil evitagen ,ataD dnuobhtroN yramirP]0:31[
01senil evitisop ,ataD dnuobhtuoS yramirP]0:9[SP
01senil evitagen ,ataD dnuobhtuoS yramirP]0:9[
41senil evitisop ,ataD dnuobhtroN yradnoceS]0:31[NS
41senil evitagen ,ataD dnuobhtroN yradnoceS]0:31[
01senil evitisop ,ataD dnuobhtuoS yradnoceS]0:9[SS
01senil evitagen ,ataD dnuobhtuoS yradnoceS]0:9[
1tupnI kcolC )DPS( tceteD ecneserP laireSLCS
3BMA eht ni rebmun MMID eht tceles ot desu osla ,stupnI sserddA DPS]0:2[AS
2
16
8)tloV 5.1( rewoP ecafretnI lennahC BMA dna rewoP eroC BMA
42)tloV 8.1( rewoP O/I MARD BMA dna rewoP MARD
4
1
Absolute Maximum Ratings
Symbol Parameter MIN MAX Units
V
IN
, V
CC
V
V
DD
V
TT
T
STG
T
CASE
Voltage on any pin relative to V
OUT
Voltage on VCC pin relative to V
Voltage VDD pin relative to Vss
Voltage on VTT pin relative to V
Storage temperature
DDR2 SDRAM device operating temperature (Ambient)
SS
SS
SS
AMB device operating temperature (Ambient)
Note: (1) Above 85°C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
Kingston.com Document No. VALUERAM0617-001.B00 07/22/09 Page 3
-0.31.75 V
-0.31.75 V
-0.5 2.3 V
-0.5 2.3 V
-55100 °C
09
95
(1)
0110 °C
C
Continued >>
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