kingston KVR1333D3S8E9S-2GHC User Manual

Memory Module Specifi cations

KVR1333D3S8E9S/2GHC

2GB 1Rx8 256M x 72-Bit PC3-10600
CL9 240-Pin ECC DIMM

DESCRIPTION

This document describes ValueRAM's 256M x 72-bit (2GB)
DDR3-1333 CL9 SDRAM (Synchronous DRAM), 1Rx8, ECC
memory module, based on nine 256M x 8-bit DDR3-1333 FBGA
components. The SPD is programmed to JEDEC standard
latency DDR3-1333 timing of 9-9-9. This 240-pin DIMM uses
gold contact fingers. The electrical and mechanical specifica­tions are as follows:

FEATURES

• JEDEC standard 1.5V (1.425V ~1.575V) Power Supply

• VDDQ = 1.5V (1.425V ~ 1.575V)

• 667MHz fCK for 1333Mb/sec/pin

• 8 independent internal bank

• Programmable CAS Latency: 9, 8, 7, 6

• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock

• Programmable CAS Write Latency(CWL) = 7 (DDR3-1333)

• 8-bit pre-fetch

SPECIFICATIONS

CL(IDD) 9 cycles
Row Cycle Time (tRCmin) 49.5ns (min.)
Refresh to Active/Refresh 160ns (min.)

Command Time (tRFCmin)
Row Active Time (tRASmin) 36ns (min.)
Power (Operating) 0.810 W*

UL Rating 94 V - 0
Operating Temperature 0o C to 85o C
Storage Temperature -55o C to +100o C

*Power will vary depending on the SDRAM used.

SDRAM SUPPORTED

Hynix (C-Die)

• Burst Length: 8 (Interleave without any limit, sequential with

starting address “000” only), 4 with tCCD = 4 which does not
allow seamless read or write [either on the fly using A12 or
MRS]

• Bi-directional Differential Data Strobe

• Thermal Sensor Grade B

• Internal(self) calibration : Internal self calibration through ZQ

pin (RZQ : 240 ohm ± 1%)

• On Die Termination using ODT pin

• Average Refresh Period 7.8us at lower than TCASE 85°C,

3.9us at 85°C < TCASE

< 95°C

• Asynchronous Reset

• PCB: Height 1.18” (30mm), single sided component

Continued >>

Document No. VALUERAM1040-001.A00 02/08/12 Page 1

MODULE DIMENSIONS:

TECHNOLOGY

30.00

18.80

15.80

11.00

8.00

0.00

Units: millimeters

0.00

133.35

54.70

Document No. VALUERAM1040-001.A00 Page 2