SERVICE MANUAL
DIGITAL STORAGE + 100MHz OSCILLOSCOPE
COM 7101A
100MHz OSCILLOSCOPE
COM 7100A
First Edition Firsst Printing March 1988
Parts No. Z1-512-371
© Copyright KIKUSUI ELECTRONICS CORP.
SECTION 1 GENERAL
SECTION 2 SPECIFICATION
SECTION 3 CIRCUIT DESCRIPTION
SECTION 4 CALIBRATION
SECTION 5 MAINTENANCE
SECTION 6 CIRCUIT DIAGRAM
SECTION 7 PARTS LIST
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1. GENERAL | 1-1 |
1-1 Description ····· | 1-1 |
1-2 Features | 1-1 |
1-2-1 Common Features of COM7101A / COM7100A | 1-1 |
1-2-2 Features of COM7101A | 1-2 |
The COM7101A/7100A have a frequency bandwidth of between DC and 100MHz, a maximum sensitivity of 1mV/DIV, and a maximum sweep speed of 2ns/DIV. In addition, four vertical and horizontal cursors are available to permit a multi-function CRT readout function.
Particularly, the COM7101A is provided with a digital storage function having a maximum sampling speed of 20ns, enabling instantaneously decaying events to be memorized. The COM7101A is also provided with a GP-IB function, enabling data held by the digital storage function or CRT readout function to be sent to a computer or other device.
(1) CRT readout
All information concerning measurement together with the waveform of the signal being measured, are displayed on the CRT. The displayed items include the vertical sensitivity, input coupling mode, and timebase sweep speed and delay time, together with the measured values obtained using the cursor lines, and the measured values obtained from the internal digital voltmeter and frequency counter.
(2) 4-channel display
The oscilloscope emplays a multi-mode select system which permits any combination of the four channels to be selected. All of the four channels provide the specified highest frequency range either at the BNC input terminals or at the probe tips.
(3) Cursor function
The two cursors displayed on the CRT permit measurement of voltage difference, time difference, and phase difference. In addition, the results of measurement are digitally displayed on the CRT.
When the tracking mode is activated, the two cursors can be moved while maintaining a constant distance between them.
(4) Digital voltmeter and frequency counter functions
The Oscilloscope contains a digital voltmeter and frequency counter. The digital voltmeter is a 3-1/2 digit auto-range digital multimeter which measures the DC, AC RMS, or peak-to-peak voltage of the signal applied to the input terminal of channel 1. The frequency counter is a 4-digit auto-range counter which measures the frequency of the trigger signal selected by the trigger source switch. The measured values are displayed on the CRT.
(5) Extensive use of ICs and self calibration function
A large number of newly developed ICs are employed in the main circuits of the oscilloscope, thereby minimizing the number of discrete components. As a result, reliability and maintainability are improved. The circuits are self-calibrating, ensuring reliable measurement.
(6) Memory for panel setting
All data for panel setting is stored in the internal memory of the oscilloscope and is not destroyed even when the power is turned off. When the power switch is turned on again, the panel setting is automatically restored.
(7) Programmable functions
By using the RC01-COM remote controller in combination with the oscilloscope, up to 100 different panel settings can be memorized and recalled by a simple pushbutton operation.
(1) Sampling rate of up to 50MS/sec
The maximum sampling rate is 50MS/sec and the vertical resolution is 8 bits, allowing to capture one-shot phenomena of up to 20MHz.
(2) Digitizing of periodic signals up to 100MHz
Periodic signals of up to 100MHz can be captured by equivalent sampling. the equivalent sampling rate in this case is as high as 10 GS/sec.
(3) Envelope mode for detecting one-shot glitches of down to 20ns
The oscilloscope has a peak value detector circuit which is able to capture periodic pulses of as narrow as 20ns within one sampling period, and to display the maximum and minimum values. This circuit can thus detect pulses of very short duration which occur in slowly changing phenomena and, even when the frequency of the input signal has become higher than one-half of the sampling frequency, aliasing that may cause measuring error can be identified.
(4) Reference memory for storing up to four waveforms
In addition to the display memory, the storage section has a reference memory for up to four waveforms which can be arbitrarily re-written. The reference memory is internally backed up, enabling the stored data to be maintained for a long period.
(5) Other
Various convenient functions are realized with the digital storage, such as pretriggering for viewing the signal waveform preceding the trigger point, interpolation which is convenient for measuring high-speed one-shot phenomena, expansion of time base up to 100 times for stored signal magnification, roll mode which is convenient for monitoring low-speed continuous signals, and delayed magnification which allows high-speed sampling of any portion of a signal sampled at a slow rate.
(6) GP-IB interface functions
Waveform data and front panel setting informations can be transferred to computer in the storage mode, enabling the oscilloscope to be used as a fully programmable digital storage instrument.
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2. | SPECIFICATION | 2-1 |
2-1 Vertical Axis | 2-1 | |
2-2 Triggering | 2-2 | |
2-3 Horizontal Axis | 2-3 | |
2-4 CRT Readout | 2-4 | |
2-5 Storage Mode | 2-6 | |
2-6 GP-IB Interface Functions | 2-7 | |
2-7 Programmable Control Functions | 2-7 | |
2-8 Zaxis | 2-7 | |
2-9 Signal Outputs | 2-8 | |
2-10 Calibration Voltage | 2-8 | |
2-11 Pen Out Signals | 2-8 | |
2-12 CRT | 2-8 | |
2-13 Power Requirements | 2-9 | |
2-14 Ambient Conditions | 2-9 | |
2-15 Dimension and Weight | 2-9 | |
2-16 Accessories | 2-9 |
Item | Specification | Remarks |
---|---|---|
CH1, CH2 | ||
Deflection
factor |
1mV / DIV to 5V / DIV | 1-2-5 sequence, 12 settings |
Accuracy |
5mV/DIV to 5V/DIV : ±2%
1mV/DIV, 2mV/DIV : ±4% |
15 to 35°C, 1kHz,
4 to 5 DIV reference |
Frequency
bandwidth |
DC to 100MHzwithin - 3dB
DC to 30MHz within - 3dB (1mV / DIV, 2mV / DIV) Lower limit frequency of AC coupling : 10Hz |
50kHz 8 DIV reference
COM7101A : REAL MODE |
Vriable Factor |
Continuously variable attenuation to 1/2.5
or less of set value |
|
Input
impedance |
1MΩ±1%, 20PF±3PF | |
СН3, СН4 | ||
Deflection
factor |
0.1V / DIV, 0.5V / DIV | 2 settings |
Accuracy | ±5% |
15 to 35°C 1 kHz,
4 to 5 DIV reference |
Frequency bandwidth |
DC to 100MHz within — 3dB
Lower limit of AC coupling : 10Hz |
50kHz 8 DIV reference
COM7101A : REAL MODE |
Input
impedance |
1MΩ±1%, 20PF±3PF | |
Maximum safe
input voltage |
400V peak (DC + AC peak) | AC : 1kHz max |
Input coupling | AC, GND, DC | |
Rise time |
Approx. 3.5ns;
Approx. 11.7ns (1mV/DIV, 2mV/DIV) |
Theoretic values
COM7101A : REAL MODE |
Channel modes |
CH1, ADD (CH1 + CH2), CH2, CH3, CH4
Any combination of the above. X-Y display with CH1 as X and any or all of CH2, CH3 and CH4 as Y. |
|
Time Difference
Among Channels |
±500ps (of all channels) |
Exept 1mV / DIV,
2mV / DIV ranges |
Signal delay time | Approx. 40ns | |
CHOP frequency | Approx. 1MHz | |
Bandwidth
limiter |
20MHz±5MHz within - 3dB | |
Polarity select | For CH2 only | |
CH1 Signal
output |
Open : Approx, 50mV/DIV
Terminated (50Ω): Approx, 25mV/DIV |
|
Freq.band width : DC to 100MHz
within — 3dB |
Item | Specification | Remarks |
A trigger | ||
Signal |
CH1, CH2, CH3, CH4, LINE, and V-MODE (In the V-
MODE, channels which normally operate in the VERT modes are used as signal sources. In the ADD mode, CH1 is used as a signal source. In the CHOP mode or AUTO LEVEL mode, the leftmost of the operating channels indicated by the VERT mode lamps on the panel is used as a signal source.) |
V-MODE is effective in the
ALT SWEEP mode or SINGLE SWEEP mode, or when the AUTO LEVEL mode is cancelled. |
Coupling | AC, LF REJ, HF REJ, DC, TV-V, TV-H | |
Polarity | + or - | |
Sensitivity |
DC to 10MHz : 0.4 DIV
DC to 100MHz : 1.5 DIV TV-V, TV-H : 1.0 DIV |
|
AC : Attenuates signal components of
10 Hz and lower |
||
LF-REJ : Attenuates signal components of
50kHz and lower |
||
HF-REJ : Attenuates signal components of
50kHz and higher |
||
AUTO LEVEL | Add 0.5 DIV to above values. | For sinusoidal waves |
Modes |
AUTO : When no triggering signal is
applied, sweep runs automatically. |
COM7101A : REAL MODE |
NORM : When triggering signal is lost,
trace disappears, and sweep goes into READY state. |
||
SINGL : When triggering signal is applied,
sweep runs only once. When RESET key is pressed, sweep is reset to READY state. And ready LED lights. |
||
B trigger | ||
Triggering
signal source |
CH1, CH2, CH3, CH4, and V-MODE (In the V-MODE,
channels which normally operate in the VERT modes are used as signal sources. In the ADD mode, CH1 is used as a signal source. In the CHOP mode or AUTO LEVEL mode, the leftmost of the operating channels indicated by the VERT mode lamps on the panel is used as a signal source.) |
V-MODE is effective in ALT
SWEEP mode or SINGLE SWEEP mode or when AUTO LEVEL mode is cancelled. |
Coupling | AC, LF REJ, HF REJ, DC | |
Polarity | + and _ | |
Sensitivity |
DC to 10MHz : 0.4 DIV
DC to 100MHz : 1.5 DIV AC : Attenuates signal components of 10 Hz and lower |
|
LF REJ : Attenuates signal components of
50 kHz and lower |
||
HF REJ : Attenautes signal components of
50 kHz and above |
||
AUTOLEVEL | Add 0.5 DIV to above value | For sinusoidal waves |
Item | Specification | Remarks |
---|---|---|
A sweep | ||
Sweep speed |
COM7100A
20ns / DIV to 0.5s / DIV COM7101A REAL : 20ns / DIV to 0.5s / DIV STORAGE : 20ns / DIV to 5s / DIV |
1-2-5 sequence |
Sweep error | Within ±2% |
15 to 35°C ; Accuracy for 8 DIV
at center of CRT |
Sweep
vaariable |
Sweep speed can be increased to at least 2.5 times set value. | COM7101A : REAL MODE |
Variable
hold-off |
Provided | COM7101A : REAL MODE |
B sweep | ||
Sweep speed |
COM7100A
20ns / DIV to 0.5s / DIV COM7101A REAL : 20ns / DIV to 0.5s / DIV STORAGE : 20ns / DIV to 50ms / DIV |
1-2-5 sequence |
Accuracy | within ±2% |
15 to 35°C ; Accuracy for 8 DIV
at center of CRT |
Delayed sweep | ||
Type of sweep | Continuous delay, triggered delay | |
Delay jitter | Less than 1 / 10,000 | |
Sweep
magnification |
10 times
Maximum sweep speed : 2ns / DIV |
In ALT mode, B sweep alone is magnified. |
Accuracy of
sweep magnification |
COM7101A
5ns/DIV to 0.5s/DIV : ±4% 2ns/DIV : ±8% COM7100A 5ns/DIV to 50ms/DIV : ±4% 2ns/DIV +8% |
15 to 35°C ; Accuracy for 8 DIV
at center of CRT |
X-Y operation | COM7101A · REAL MODE | |
X-Y operation |
X axis : CH1
Y axis : CH2, CH3, CH4 (X-Y operation of up to 3 channels) |
Y axis : CHOP Operation |
Deflection
factor |
Identical to those of CH1, CH2, CH3 and CH4 | |
Accuracy |
X axis : ±3% (5mV to 5V / DIV)
±5% (1mV / DIV, 2mV / DIV) Y axis : ±2% (CH2), ±5% (CH3, 4) |
15 to 35°C, 1kHz, 4 to 5 DIV
reference |
Frequency
bandwidth |
DC to 2MHz within — 3dB |
X axis : For CH1 ;
Y axis : Identical to CH2, CH3, and CH4 |
X-Y phase
difference |
Within 3° between DC and 100kHz |
Item | Specification | Remarks |
Setting display | ||
Vertical axis |
CH1, CH2, CH3, and CH4 DEFLECTION
FACTOR and COUPLING ; Display when 10 : 1 probe is used ; CH1 and CH2 UNCAL status ; BWL |
BWL=Band Width Limiter |
Sweep |
A and B sweep speed.
A sweep UNCAL status ; HOLDOFF ; Delay time |
|
Cursor |
ΔREF cursor and Δ cursor
ΔV, voltage ratio, ΔT, 1 / ΔT, and time ratio Phase difference |
|
Others | Frequency couner and DVM reading | |
Storage |
Display of DEFLECTION FACTOR and
coupling modes of reference memory Reference memory sweep speed : Predelay trigger point; Magnification point; Delay start point; View time |
COM7101A : STORAGE
MODE |
DLY | Delay time | |
Delay time
range ; |
0.5 to 10.00 times A sweep setting of
highest sweep speed range to 0.5s / DIV range |
|
Accuracy | Within ±2% | |
Δ٧ | Voltage between ARFF cursor and Acursor is measured and displayed. |
In CH2 SINGLE SWEEP mode
or in CH21 and CH3 / CH4 channel modes, DEFLECTION FACTOR is that of CH2; in other cases, it is that of CH1. |
Measuring
range |
±3.6 DIV from center of CRT | Minimum guaranteed value |
Accuracy | Within ±3% | ······································ |
Voltage ratio |
Displays the ratio of voltage between \Delta RFF
cursor and \Delta cursor with respect to 5 DIV on CRT as reference (100%). |
For ΔV measurement, GAIN
VARIABLE is displayed in UNCAL status. |
Measuring
range |
±3.6 DIV from center of CRT | Minimum guarantee value |
Accuracy | Within ±3% | |
ΔΤ | Time between ΔRFF cursor and Δcursor is displayed. | Minimum guaranteed value |
Measuring
range |
±4.6 DIV from center of CRT | |
Accuracy | Within ±3% |
Item | Specification | Persoulea |
---|---|---|
£05331 | ореспісаціон | Kemarks |
1/ΔΤ | Reciprocal (frequency) of D T is displayed. | |
Time ratio |
Displays the ratio of time interval between
ARFF cursor and Acursor with respect to 5 DIV or CRT as reference (100%). |
For ΔT measurement, SWEEP
VARUABLE is displayed in UNCAL status. |
Measuring
range |
±4.6 DIV from center of CRT | Minimum guaranteed value |
Accuracy | Within ±3% | |
Phase difference |
Displays in degress the phase difference
between AREF cursor and Acursor with respect to 5 DIV on CRT as reference (360 degrees). |
For 1 / ΔT measurement,
SWEEP VARIABLE is displayed in UNCAL status. |
Measuring range | ±4.6 DIV from center of CRT | Minimum guarantee value |
Accuracy | Within ±3% | |
ΔDelay | Measures ΔT or 1 / ΔT by using B sweep instead of ΔREF cursor and Δcursor. |
Operates in ALT sweep and B
sweep modes at the same time. |
Measuring
range |
3.6 DIV from center of CRT | Minimum guarantee value |
Accuracy | Within ±2% (excluding 0.5 DIV from left hand end of CRT) | |
DVM |
Displays using 3-1/2 digits in auto-range
system the CH1 input for up to ±10 DIV on CRT (AC voltage, DC voltage, p-p voltage) |
COM7101A : Excluding
storage mode |
AC measuring |
Measures AC voltage as RMS value
between 20Hz and 100kHz accuracy ; within ±4% |
Tcal ±5%
Tcal=Self Calibration Temperature (20~30°C) at center of CRT |
DC measuring |
Measures DC voltage
accuracy ;within ±3% |
Tcal ±5%
Tcal=Self Calibration Temperature (20~30°C) at center of CRT |
p-p measuring |
Measures peak-to-peak voltage of AC
component between 20Hz and 10MHz; accuracy20Hz ~ 5MHz ; within ±5% 5MHz ~ 10MHz; within ±10% |
Tcal ±5%
Tcal=Self Calibration Temperature (20~30°C) at center of CRT |
FREQUENCY |
Measures frequency of input channel signal
selected by TRIG SOURCE switch 4-digit display, auto-range |
Operates simultaneously with
DVM. Not effective when two or more triggering source signals are selected. |
Measuring
rang |
1.0Hz to 100MHz | |
Error | ±0.1% |
Item | Specification | Remarks |
---|---|---|
Vertical axis resolution | 8 bits (25 points / DIV) | |
Horizontal axis resolution | 10 bits (100 points / DIV) | |
Sampling rate ; |
In single channel mode or multi- channel
ALT mode : 20 samples / sec to 50M samples / sec In CHOP or ALT mode : 20 samples / sec to 20M samples / sec |
|
Accuracy | ±0.02% | |
Effective storage
frequency |
100MHz (repeat mode) :
For 1µs / DIV to 20ns / DIV range (in CHOP mode, 2µs / DIV to 10ns / DIV range), and periodic signals. |
With Sine Interpolation
effective storage frequency band is 100MHz : — 3dB maxin vertical axis |
20MHz : For 2µs / DIV to 20ns / DIV
range excluding CHOP mode. |
||
8MHz : 5µs DIV to 10ns / DIV, in SINGLE
SWEEP |
||
Effective rise
time |
3.5ns max (repeat mode) :
1µs / DIV to 20ns / DIV range (2µs / DIV to 20ns / DIV range for CHOP mode), and periodic signals. |
With pulse interpolation |
32ns max : 2µs / DIV to 20ns / DIV range,
excluding CHOP mode. |
||
80 ns max : 5µs DIV to 10ns / DIV, in
SINGLE SWEEP |
||
Operating modes |
SINGLE SWEEP : CH1, CH2, CH3, CH4
ALT : Any combination of CH1 through CH4 CHOP : CH1 and CH2 |
|
Repecat mode |
For single channel or ALT sweep
: 1µs / DIV to 20ns / DIV For CHOP : 2µs / DIV to 20ns / DIV |
Except for SINGLE SWEEP
mode in random equivalent time sampling |
ROLL mode | 5s / DIV to 0.1s / DIV |
For single channel mode or
2-channel mode |
ENVELOPE
mode |
Operating ranges :
50ms / DIV to 10µs / DIV |
|
Waveform
magnification |
Waveform can be expanded up to × 100 of
the timebase setting. Reference position for magnification : 0 DIV to 10 DIV in 1-DIV steps, 11 positions |
|
Interpolation : Sine or pulse | 1 | |
Display memory | (1.024 words per channel) × 4 | |
Reference
memory |
For 4 waveforms | |
Pre-triggering | Trigger point; 0,2,4,6,8 DIV at CRT | For PAUSE status |
View time | 0 to about 10 seconds | 4 steps |
Item | Specification | Remarks |
---|---|---|
Interface
functions (IEEE488-1978) (IEC625) |
SH1 :All source handshakeAH1 :All acceptor handshakeT6 :TalkerL3 :ListenerSR1 :All service requestRL1 :All remote / localPP0 :No parallel pollDC1 :All device clearDT0 :No device triggerC0 :No control | |
Programmable
functions |
All functions except VARIABLE, FOCUS,
TRACE ROTATION |
|
Format |
Device commands: ASCII
Waveform data : Binary or ASCII (selectable) |
Item | Specification | Remarks |
---|---|---|
Program steps | 100 (00 to 99) | Displayed on 7 SEG LED |
Programmable functions | All functions except INTEN, FOCUS, and TRACE ROTATION |
Only models provided with GP-
IB interface |
Program backup | Provided | |
External control function |
Can be connected to probe selector
(PS01-COM) |
|
Step address
output |
BCD code |
Item | Specification | Remarks |
---|---|---|
Sensitivity |
Intensity modulation discernible with
3 Vp-p input signal. Negative-going signal for brighter trace and positive-going signal for dimmer trace. |
|
Frequency range | DC to 10 MHz | |
Input resistance | 5 kΩ±10% | |
Maximum safe
input voltage |
50V peak (DC+AC peak) |
AC components not higher than
1 kHz |
Item | Specification | Remarks |
---|---|---|
Sweep signal output | A sweep singal : Approx. 1 Vp-p | BNC terminal at rear panel |
Sweep gate
output |
A sweep gate signal output :
Approx. 5 Vp-p |
BNC terminal at rear panel |
B sweep gate signal output :
Approx. 5 Vp-p |
Item | Specification | Remarks |
---|---|---|
Waveform | Positive pulse singal | |
Frequency | 1 kHz±0.1% | |
Output voltage | 0.5 Vp-p±2% | |
Output resistance | Approx. 2kΩ |
Item | Specification | Remarks |
---|---|---|
X-Y recorder
output |
Operates in storage mode | |
X axis output |
0.1 V / DIV±10%
(Speed automatically varies in response to Y-axis amplitude) |
BNC terminal at rear panel
(common with sweep signal output terminal) |
Y axis output | 0.1 V/DIV±10% | BNC terminal at rear panel |
SYNC output | TTL level, positive output |
BNC terminal at rear panel
(common with A sweep gate terminal) |
Item | Specification | Remarks |
---|---|---|
Cathode-ray tube |
6-inch square screen, with internal white
graticule Effective screen area : 8×10 cm (3.15×3.94 in.) Acceleration voltage : Approx. 20 kV |
Item | Specification | Remarks |
---|---|---|
Line voltage | 90V to 250V | No voltage selection required |
Line frequency | 48 Hz to 62 Hz | |
Power
consumption |
COM7100A : Approx. 65W
COM7101A : Approx. 103W |
Item | Specification | Remarks |
---|---|---|
Operating range |
Temperature : 5°C to 40°C ;
Humidity : 90% max |
|
Maximum
operating range |
Temperature : 0°C to 50°C ;
Humidity : 95% max |
Item | Specification | Remarks |
---|---|---|
Dimensions | 318W×150H×400D (mm) | |
Weight |
COM7100A : Approx. 8 kg;
COM7101A : Approx. 10 kg |
Item | Specification | Remarks |
---|---|---|
Probe | P100 - S type ×two | 10:1 |
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3. | CIRC | UIT C | OPERATION | 3-1 |
3.1 | Block | Diagram | 3-1 | |
3-1.1 | General | 3-1 | ||
3.1.2 | Real time section | 3-1 | ||
3.1.3 | Storage section | 3-5 | ||
3.2 | Circui | it Description | 3-7 | |
3.2.1 | CRT section | 3-7 | ||
1) | High Voltage Circuit | 3-7 | ||
2) | Z. Axis circuit | 3-7 | ||
3) | Character generator circuit | 3-7 | ||
4) | DVM Circuit | 3-7 | ||
2.2.2 | Vertical axis section | 3-8 | ||
1) | Attenuator circuit | 3-8 | ||
2) | Preamplifier circuit | 3-8 | ||
3) | Switching circuit | 3-8 | ||
4) | Delay line circuit | 3-8 | ||
5) | Final stage | 3-8 | ||
3.2.3 | Trigger section | 3-9 | ||
1) | Trigger pickoff | 3-9 | ||
2) | Trigger source and coupling | 3-9 | ||
3.2.4 | Horizontal axis section | 3-10 | ||
1) | Triggering and sweep (A/B) | 3-10 | ||
2) | Sweep timing circuit | 3-10 | ||
3) | X-Y Function | 3-10 | ||
4) | Switching circuit | 3-10 | ||
5) | Final stage | 3-10 | ||
3.2.5 | Storage section | 3-11 | ||
1) | Input signal and channel divider | 3-11 | ||
2) | Peak hold circuit | 3-12 | ||
3) | Sample-hold and highspeed A/D conversion | 3-12 | ||
4) | Highspeed memory and highspeed address counter circuit | 3-13 | ||
5) | Random sampling | 3-13 | ||
6) | Roll function | 3-13 | ||
7) | Linear interpolation and sine interpolation | 3-13 | ||
3.2.6 | CPU Circuit | 3-14 | ||
1) | CPU Function | 3-14 | ||
2) | Address map | 3-14 | ||
3) | I/O Map | 3-15 | ||
4) | Keyboard circuit | 3-16 | ||
5) | LED Display circuit | 3-18 | ||
3.2.7 | Power source circuit | 3-20 |
COM7101A consists of real time section and storage section. COM7100A consists of real time section only.
Figure 3-1 shows oscilloscope section and Fig. 3-2 shows control section.
Most of mechanical switches used in conventional oscilloscopes are replaced with electronics switches in the COM7000A series. These switches are controlled by digital signals.
And gain, sweep variables, H, V-axis positions are also controlled digitally.
Thus most of the functions can be controlled remotely by GP-IB.
Majority of the circuits are built on HIC (Hybrid Integrated Circuit). Self-calibration is provided so that V-axis gain, DC-balance and sweep speed are automatically checked and adjusted.
For instance, when the DC-balance to be adjusted.
When the V-axis gain to be adjusted.
When the sweep speed to be adjusted
Nearly half of the adjustments are performed automatically.
The control section is handled by main C.P.U (Z80, 8 bit). All the front panel informations are read and made necessary changes by the C.P.U.
The main C.P.U also communicates with the sub-C.P.U in case of COM7100A.
Figure 3-1 Block Diagram (Real Time System, Oscilloscope Section)
Figure 3-2 Block Diagram (Real Time System, Control Section)
Block diagram for the storage section is shown in Fig. 3-3.
The storage section consists of analog processing, A/D memory, acquisition control, storage display and sub-C.P.U section.
The analog processing section amplify and convert the impedance of the signal picked-off from the real time section then fed to the A/D memory section. In case of "envelope" mode is selected the signal is routed to "envelope peak hold circuit" then to the A/D memory section.
The A/D memory section consists of sample and hold circuit, A/D converter, high speed memory, address counter, and timing generator. The maximum sampling frequency is 50 MHz. Two A/D converters are used alternately to achieve 50 MHz.
The timing generator produces sequential sampling pulses and random sampling pulses when in "repeat" mode.
The acquisition control section consists of clock generator, programmable divider, jitter meter, pre-trig, counter, analog multiplexer, and D/A converter.
The storage display section consists of display RAM, Y-axis D/A converter display address counter, interpolator, storage deglitcher, and X-Y recorder output circuit.
The sub-C.P.U section employs 8 bit C.P.U (Z80) to manage the storage section. Necessary informations are fed from the main C.P.U through common RAM. Also interface function is provided for step controller or GP-IB.
3-5
High voltage Generator Circuit (A6 PCB) High voltage generator circuit comprises DC-DC converter which is called BLOCKING generator
Approximately 50 kHz sine wave from the BLOCKING generator is stepped up by secondary winding of the high voltage transformer, and rectified to -2,100 V to accelerate the beam. The voltage is fed back to OP AMP via resistor. The OP AMP controls drive transistor of the BLOCKING generator to obtain constant -2,100 V. The secondary voltage is applied to multiplier circuit and used for post acceleration of the CRT beam. Voltage from secondary center tap of the transformer is used for intensity and focus control circuits.
2) Z-axis Circuit (A6 PCB)
Z-axis circuit amplifier comprises HIC. Blanking signal and focus signal are applied to differential AMP, which controls proper focus regardless to the brightness or delay sweep control.
3) Character Generator Circuit (A8-PCB)
Datas (ASCII code) for the characters are fed to character RAM (A8-U85 6116). The datas are then routed to character ROMs (A8-U105 2764) as the address signal. X-axis and Y-axis datas are fed out from the ROMs. These datas are latched and converted to analog signal by D/A converter.
These signals are called as CHR-X and CHR-Y.
4) DVM Circuit (A4 PCB)
By using CH1 2nd ATT (A4-U3 H5) output signal, the DVM circuit measures DC and AC voltage. Both RMS and P-P are measured. True RMS converter measures RMS, and + and – PEAK DETECTOR in HIC and differential OP AMP measures P-P.
1) Attenuator Circuit (A1, A3, A4 PCB)
Attenuator circuit consists of ATT (A1) for CH1 and 2, and ATT (A3) for CH3 and 4.
The ATT (A1) employs semiconductor switches and relays, and comprises 1st ATT of HIC (H3) and 2nd ATT on A4 PCB. The ATT includes input signal attenuation (10 mV ~ 5 V / DIV, 9 steps), input coupling (AC/DC/GND), and x 10 MAG circuit for 1 mV and 2 mV/DIV sensitivity setting.
ATT (A3) houses two channel in a case, and employs semiconductor switches and relays same as A1. It includes (H4) input signal attenuation (1/1, 1/5, 2 steps), input coupling (AC/DC/GND) and input impedance switching.
2) Preamplifier Circuit
There are two types of preamplifiers are used.
One is commonly used on CH1 and CH2, which is providing 1st AMP and 2nd AMP.
Other one for CH3 and CH4 which is providing input AMP and 2nd AMP.
The 1st AMP consists of unbalance to balance converter, x 2 MAG (when in 5 mV/DIV setting), step balance, and variable gain controls.
The position control, position centering, internal trigger-pickoff and V-axis gain circuits are provided in the 2nd AMP.
The input AMP for CH3 and CH4 consists of impedance converter, and attenuator.
3) Switching Circuit
Balanced signals from CH1, 2, 3, 4 and storage circuit are selected by the switching circuit (A4-U20 H8).
Real mode signal, X-Y mode signal, and storage signals are fed out. CH2 INV function is also provided.
4) Delay Line Circuit
Delay line circuit comprises delay line driver (A4-U25 H9) and delay line, and delays vertical signal, switches observation signal and character. BEAM FIND and BWL (Band Width Limit) are also provided.
5) Final Stage
Final stage comprises HIC (A5-U2 H10), deflector drive transistor (A5-Q2, Q3) and deflector potential detector circuit (A5-U1). Deflector drive transistor, with HIC internal transistor makes cascade amplifier for wide band amplification.
the Deflector potential detector circuit is for data feedback during self-calibration, it detects DC balance of differential amplifier in HIC, applies the potential to A/D converter [D/A converter on A10 (A10-U13)], and feeds back to C.P.U.
1) Trigger Pickoff
Internal trigger signal is picked off from 2nd AMP (A4-U13-U16) of CH1 ~ CH4. It picks off half a differential signal, and feeds the signal to TRIG SOURCE SW circuit (A4-U27) in current mode.
2) Trigger Source and Coupling
TRIG SOURCE SW (A4-U27) selects internal trigger signal obtained from trigger pickoff circuit and line trigger signal as A or B trigger signal. The line trigger signal at primary input voltage of power supply circuit (A12-PC1), is detected by transister (A12-Q1), isolated by photo-coupler (A12-PC1), impedance converted (A12-Q15), then applied to TRIG SOURCE SW circuit (A4-U27) via mother board.
A trigger signal from TRIG SOURCE SW circuit is applied to TRIG COUPLING circuit (A4-U28) and DC, AC, HF REJECT, or LF REJECT coupling will be selected.
And the output signal is applied to trig level comparator circuit (A4-U30) then shaped to square waveform.
The square waveform is fed to sweep controller circuit (A4-U48).
TRIG LEVEL COMPARATOR circuit output includes a signal 180° differs from SWEEP CONTROLLER output signal in phase, which applied to TV SYNC circuit (A4-U32) to separate TV synch signals (vertical synch signal, horizontal synch signal), and the signal is applied to SWEEP CONTROLLER circuit as TV TRIG signal.
B trigger circuit provides no TV SYNC circuit, and other functions are same as A trigger circuit.
1) Triggering and Sweep (A/B)
Trigger signal from the trigger circuit is applied to the sweep circuit and produces sweep signal. The sweep circuit comprises SWEEP CONTROLLER circuit (A4-U48), A/B SWEEP GEN circuit (A4-U43, A4-U44) mentioned below, and generates 10 ns/DIV maximum sweep signal to 0.5 s/DIV sweep signal. (Sweep signal in STORAGE MODE is generated in other circuit.)
The SWEEP CONTROLLER comprises A and B SWEEP GENERATORS, and controls sweep signal (A/B) synchronization by trigger signal, SWEEP MODE (AUTO, NORM, SINGLE selection), continuous and triggered delay.
2) Sweep Timing Circuit
Sweep timing circuit determines A/B sweep time respectively. This circuit is built in the A/B SWEEP GEN circuit with a Miller integrator circuit and a constant current circuit, and controls sweep signal in accurate timing. Component used in the circuit have better temperature coefficient.
3) X-Y function
The CH1 operates as X-axis and the CH2, 3, and 4 operate as Y-axis. Vert mode SW circuit (A4-U20) controls the vertical mode.
4) Switching Circuit
Horizontal axis switching circuit comprises SWEEP COMP SW circuit (A4-U52 H29) and HORIZ SW & DRIVE AMP circuit (A4-U55 H30).
The SWEEP COMP SW circuit switches A, B sweep signal and sweep signal in the STORAGE mode to panel operation. It has "HORI OUT" to be applied to next stage HORIZ SW & DRIVE AMP circuit, and "COMP OUT" to be applied to DELAY TIME COMP. circuit (A4-U56, H28).
The HORIZ SW & DRIVE AMP circuit switches sweep signal (A, B sweep signal and sweep signal during STORAGE MODE), X-axis signal for X-Y function, and character X-axis signal. Also controls x 10 MAG and BEAM FIND function.
5) Final Stage
Final stage is designed with HORIZ FINAL AMP (A5-U3 H31). The circuit is non-saturation type amplifier which employs Active Load and has good linearity to higher amplitude: double high frequency injection is provided to improve rise and fall time. Also composite horizontal axis signal (A5-Q4 ~ Q6) is applied to FOCUS DRIVE circuit (A6-U601 H31) to improve corner image of the CRT.
1) Input Signal and Channel Divider
Two A/D converters are used to facilitate 50 MHz/Sampling. And two A/D input signals, CHA and CHB, are routed from VERT MODE SW circuit.
Table 3-1 shows function of the VERT MODE SW circuit in the STORAGE mode.
SETTING | OUTPUT | |||||
---|---|---|---|---|---|---|
CHA | СНВ | SIGNALS FOR DIGITIZING | ||||
CH1 | CH1 CH2/CH4 | CHA signal. | ||||
Si | ngle | CH2 | CH1/CH3 | CH2 | CHB signal. | |
trace | СНЗ | СНЗ | CH2/CH4 | CHA signal. | ||
CH4 CH1/CH3 CH4 | CH4 | CHB signal. | ||||
ALT | CH1/CH2 | СН1 | CH2 | CHA/CHB signals alternately. | ||
CH1/CH3 | CH1/CH3 | CH2/CH4 | CHA signals (CH1 and CH3) alternately. | |||
မ္မ | CH1/CH4 | CH1 | CH4 | CHA/CHB alternately. | ||
l tra | CH2/CH3 | СНЗ | CH2 | CHA/CHB signals alternately. | ||
Dua | CH2/CH4 | CH1/CH3 | CH2/CH4 | CHB signals (CH2 and CH4) alternately. | ||
CH3/CH4 | СНЗ | CH4 | CHA/CHB alternately. | |||
СНОР | CH1/CH2 | CH1 | CH2 |
CHA/CHB signals.
Unable to select CH3 or CH4 in CHOP mode. |
Table 3-1 Function of VERT MODE SW circuit in STORAGE mode.
Output signal of the VERT MODE SW circuit is applied to the ST SIGNAL BUFFER circuit (A4-U26 H11), then converted to voltage from current, then routed to the ANALOG PROCESSING BOARD (A15).
The ANALOG PROCESSING BOARD routes the OUTPUT SIGNAL to the GND REF circuit (A15-CR1 ~ CR8, Q3, Q4).
The GND REF circuit switches its input signal between ground level and the output signal from the VERT MODE SW circuit when in the SELF CAL MODE.
The output of the GND REF circuit is applied to the STORAGE SIGNAL DRIVE circuit (A15-H12) for amplification and impedance conversion.
The STORAGE SIGNAL DRIVER output signal is fed to the CHANNEL DIVIDER circuit (A15-U6 H13). When the ENVELOPE MODE is not selected, Table 3-2 shows function of the CHANNEL DIVIDER circuit.
INPUT | OUTPUT | ||||||
---|---|---|---|---|---|---|---|
SETTING |
CHA
(20-21pin) |
CHB
(2-3pin) |
CHA
(32-33pin) |
CHB
(34-35pin) |
SIGNAL FOR DIGITIZING | ||
S | ingle | CH1 | CH1 | CH2/CH4 | CHI | CH1 | |
trace | CH2 | CH1/CH3 | CH2 | CH2 | CH2 · | ||
CH3 | CH3 | CH2/CH4 | CH3 | СНЗ | |||
CH4 | CH1/CH3 | CH4 | CH4 | CH4 | |||
ALT | CH1/CH2 | CH1 | CH2 | CH1/CH2 | CH1/CH2 | CH1 and CH2 signals alternately. | |
CH1/CH3 | CH1/CH3 | CH2/CH4 | CH1/CH3 | CH1/CH3 | CH1 and CH3 signals alternately. | ||
race | CH1/CH4 | CH1 | CH4 | CH1/CH4 | CH1/CH4 | CH1 and CH4 signals alternately. | |
tal ti | CH2/CH3 | CH3 | CH2 | CH2/CH3 | CH2/CH3 | CH2 and CH3 signals alternately. | |
1 a | CH2/CH4 | CH1/CH3 | CH2/CH4 | CH2/CH4 | CH2/CH4 | CH2 and CH4 signals alternately. | |
CH3/CH4 | СНЗ | CH4 | CH3/CH4 | CH3/CH4 | CH3 and CH4 signal alternately. | ||
СНОР | CH1/CH2 | СН1 | CH2 | CH1 | CH2 |
Table 3-2 Function of CHANNEL DIVIDER circuit
Thus the signals are divided and routed to the A/D, and memory board (A16).
2) Peak Hold Circuit
Peak Hold circuit functions when in the ENVELOPE MODE, and when the ENVELOPE MODE is not selected, output of this circuit is off. When in the ENVELOPE MODE, input signal is fed to the ENV PEAK HOLD circuit (A15-U7 U8 H16), then + and – PEAK are detected.
U8 detects CHA (CH1/CH3), and U7 detects CH3 (CH2/CH4), and holds the value until next sampling. Output of the ENV PEAK HOLD circuit is connected in parallel to output of the CHANNEL DIVIDER circuit.
3) Sample Hold and High Speed A/D Converter
A pair of signals routed from analog processing board (A15) are fed to a pair of differential to single signal converters (A160Q1 ~ Q4) on the A/D and menory board (A16).
The signal then routed to a pair of SAMPLE and HOLD circuits (A16-U12A, U12C H18). The clock frequency is upto 25 MHz.
The signals are digitaized by a pair of 8 bit A/D converters (A16-U11A, U11C UVC3120).
The sampling pulses are slightly delayed by delay cables (A16-DL1, DL2) and the associated circuit.
This delay circuit feed various delayed signals to MEMORY CIRCUIT (A16-U8A, U8C TMM2018-35), address counter circuit (A16-U6A, U6C, U7A, U7C, F269, F169) and so on.
4) High speed Memory and Address Counter
High speed devices are utilized to meet the high speed operation for following circuitry:
memory (A16-U8A, U18C TMM2018-35) data bus buffer (A16-U10A, U10C F541) address counter (A16-U6A, U6C, U7A, U7C, F269, F169).
5) Random Sampling
Random sampling technic is used for the REPEAT MODE.
The input signal is sampled in random manner and repeated over 1000 times to fill the memory.
The sampling timing is produced by jitter interval meter circuit (A17-U3B H33).
The circuit consists of charging and discharging circuit with counter and the time constants of these circuit are managed very tightly.
6) Roll Function
Roll mode is executed by the program.
The latest data captured is placed in the lead address and all data in the memory are shifted one address to the end.
7) Linear and Sine Interpolation
Linear INTERPOLATION circuit (A18-U1B H20) is located next to vertical axis D/A convertor (A18-U2A DACO8EN) of STORAGE DISPLAY PCB (A18). the Interpolation is also called dot-join circuit, and it joins D/A converted vertical axis data with straight line. It detects potential across two points and integrates it and adds the value to the head data. When the integration finished, it results in same value of the hind data.
The STORAGE SWEEP DEGLITCHER circuit (A18-U1C, H32) located next to horizontal D/A convertor (A18-U2C HA17012PB) eliminate conversion noise and joins horizontal axis steps with straight line.
Noises are eliminated by the SAMPLE and HOLD circuit and the step voltage is converted to slope by the integrator.
At least 2.5 datas per cycle are necessary to complete the calculation of the locus for 360°.
1) CPU Function
CPU circuit comprises Z-80 (A8-U12 later called MAIN CPU) to control real time section and other Z-80 (A14-U4D later called SUB CPU) to control STORAGE and GP-IB.
The MAIN CPU detects SWITCH or KNOB operation via KEYBOARD circuit, and controls internal circuit. Simultaneously displays internal status on the PANEL or on the CRT. When cursors are used, the DATA across the CURSORs are displayed on the CRT. Also controls automatic self-diagnosis, key operation, and automatic self-calibration.
The SUB CPU circuit controls STORAGE and GP-IB circuit, etc., on basis of instructions from the MAIN CPU, and handles self-diagnosis and self-calibration of STORAGE circuit.
2) Address MAP
Figure 3-4 shows the MAIN CPU ADDRESS MAP. Table 3-3 shows ROM/RAM REFERENCE DESIGNATOR and parts name .
POM and DAM | REF. DESIGNATOR |
and PARTS NAME | |
ROM | A8-U13 27256 |
RAM | A8-U15 6116-3 |
COMMON RAM | A8-U33 6117-3 |
CHARACTER RAM | A8-U85 6116-3 |
SEQUENCER RAM | A4-U59 H41 |
Note) The SEQUENCER RAM employs 4416 (1 k Byte) in H41.
The COMMON RAM works as buffer memory for the MAIN and SUB C.P.U. The DATA are switched in 1 ms interval.
The CHARACTER RAM displays PANEL DATA and CURSOR DATA on the CRT.
The SEQUENCE CONTROLLER (A4-U59 H41) controls vertical and horizontal mode on basis of PANEL setting.
Table 3-3 ROM/RAM circuit figure number.
PORT No. | IN/OUT | DEV | ICE | DESCRIPTION |
---|---|---|---|---|
00H(E0) | IN/OUT | A10-U17 | 8279 |
INPUT DATA from KEY SW MATRIX CKT
and OUTPUT DATA to LED DRIVE CKT. |
01H | IN/OUT | A10-U17 | 8279 |
READ STATUS of 8279 & WRITE
COMMAND of 8279. |
10H(E1) | INPUT | A10-U7 | HC541 |
PULSE COUNT DATA of CH1/CH2
VOLTS/DIV. |
11H | INPUT | A10-U8 | HC541 |
FLAG of CH1/CH2 UNCAL/CAL, TIME/DIV
A/B and UNCAL/CAL, PULSE COUNT DATA of TIME/DIV. |
12H | OUTPUT | A10-U11 | HC574 |
PANEL SETTING DATA, D/A CONVERT
DATA (4 Bit). |
A10-U13 | HC193 |
Clear signal for PULSE COUNT DATA. (CH1
VOLTS/DIV) |
||
1011 | A10-U14 | HC193 |
Clear signal for PULSE COUNT DATA. (CH2
VOLTS/DIV) |
|
13H | OUTPUT | A10-U15 | HC193 |
Clear signal for PULSE COUNT DATA.
(TIME/DIV) |
A10-U6 | MC14538 | Clear signal for IRQ OUTPUT. | ||
14H | OUTPUT | A10-U12 | HC574 | Data for D/A CONVERT DATA (8 Bit). |
15H | INPUT | A10-U16 | HC365 | Buffer for output data of comparator. |
20H(E2) | IN/OUT | A8-U01 | HC74 | Clear signal for 2 ms INT. |
30H(E3) | IN/OUT | A4-U10 | HC74 | Clear signal for OVER LOAD PROTECTOR INT. |
40H(E4) | IN/OUT | A8-U63 | HC107 | Clear signal for COUNTER INT. |
A8-U51 | HC107 | Clear signal for COUNTER DATA. | ||
50H(E5) | IN/OUT | A8-U55 | HC390 | Clear signal for COUNTER DATA. |
A8-U65 | HC74 | Clear signal for COUNTER DATA. | ||
60H(E6) | OUTPUT | A8-U107 | HC4094 | LATCH PULSE for SERIAL DATA of U107. |
70H(R0) | INPUT | A8-U36 | HC541 | INT (Interrupt) REQ FLAG. |
70H(W0) | OUTPUT | A8-U37 | HC174 | Select function mode of U38. |
74H(R1) | INPUT | A8-U38 | HC299 | Data for serial output. |
74H(W1) | OUTPUT | A8-U38 | HC299 | CLOCK for SERIAL DATA. |
A8-U | HC257 | COUNTER DATA & STATUS. | ||
78H(R2) | INPUT | A8-U56 | HC257 | COUNTER DATA. |
78H(W2) | OUTPUT | A8-U102 | HC4049 | LATCH PULSE for SERIAL DATA of U102. |
7CH(R3) | INPUT | A8-U113 | HC74 | FRAME REQUEST CLOCK. |
7CH(W3) | OUTPUT | A8-U62 | HC4049 | LATCH PULSE for SERIAL DATA of U62. |
Table 3-4 MAIN CPU I/O MAP
Keyboard circuit is entirely similar to personal computer keyboard. All panel switches are located above key-matrix. The circuit comprises PROGRAMMABLE KEYBOARD/DISPLAY CONTROLLER (A10-U17 8279), 3-8 LINE DECODER (A11-U8 HC138) and KEY MATRIX circuit.
Fig. 3-5 Shows Keyboard Circuit.
Fig. 3-5 Keyboard Circuit
The PROGRAMMABLE KEYBOARD/DISPLAY CONTROLLER (A10-U17) continuously scans the matrix keys. SL0 ~ SL2 continuously feed BINARY CORD for the scanning. 3-8 LINE DECODER (A11-U8) decodes the BINARY CODE and continuously scans all key matrix keys.
When if "LEVEL AUTO" key (A11-S36) is pressed, each SC0 ~ SC6 LINE consecutively turn to "H", and when SC3 turns to "H", the signal is sent to RL5. Thus determine which matrix key has been pressed. U17 feed preset CODE to DATA BUS.
When "H" is sent to RL5, CPU is ready to accept the data from DATA BUS. The CPU accepts the DATA and detects "LEVEL AUTO" key has been pressed.
KEY EN signal is a chip select signal from I/O ADDRESS DECODER (A8-U45 HC138), which delivered to 00H ~ 0FH.
However U17 functions only when 00H~ 01H I/O address is selected since A0 is fed from the ADDRESS BUS.
RL0 | RL1 | RL2 | RL3 | RL4 | RL5 | RL6 | RL7 | |
S01 | S02 | S03 | S04 | S05 | S06 | |||
SC0 | Cł | 11 COUPLIN | IG | CH | 12 COUPLIN | IG |
BINT/SCAL
/READOUT |
BEAM
FIND |
SC0
SC1 SC2 SC3 SC4 SC5 |
AC/DC | GND | 50Ω | AC/DC | GND | 50Ω | ||
S11 | S12 | S13 | S14 | S15 | S16 | |||
SC1 | С | H3 COUPLI | NG | CH | 14 COUPLIN | |||
AC/DC | GND | ÷5 | AC/DC | GND | ÷5 | |||
S21 | S22 | S23 | S24 | S25 | S26 | S27 | S28 | |
SC2 | L | VERT | MODE | BW | X-Y | |||
CH1 | ADD | CH2 | CH3 | CH4 | ALT/CHOP | 20MHz | (PEN OUT) | |
5 | S31 | S 32 | S33 | S34 | S35 | S36 | S37 | S38 |
SC3 | HORIZ. N | MODE | A/B | LEVEL | SLOPE | VIONO | ||
A | ALT | В | B TRIG | TRIGGER | AUTO | +/ | X IU MAG | |
S41 | $42($49) | S43 | S44 | S45 | S46 ′ | |||
SC4 | RESET | (READY) |
SOURCE
B |
SOURCE
A |
COUPLING
B |
COUPLING
A |
||
S51 | S52 | S54 | S55 | |||||
SC5 | ΔΤ/ΔV | DLY | 1 | Но | AC/DC/PP | |||
S61 | S62 | S63 | S64 | S65 | S66 | S67 | S68 | |
SC6 | PAUSE | SAVE |
REF
MEMO |
VIEW
TIME |
TRIG
POINT |
ENV |
SIN/
PULSE |
STRG/
REAL |
NOTE: BIND/SCAL/READ OUT & BEAM FIND SWITCH are located on the CRT CONTROL board (A7 PCB).
Table 3-5 Panel Switch Format
5) LED Display Circuit
LED display circuit employs display function of PROGRAMMABLE KEYBOARD/DISPLAY CONTROLLER (A10-U17 8279).
PANEL LEDs are located above matrix as same as keyboard switches.
LED display circuit comprises the PROGRAMMABLE KEYBOARD/DISPLAY CONTROLLER (A10-U17 8279), 3-8 LINE DECODER (A11-U2, U4 HC138), DISPLAY DRIVER (A11-U1, U3, U5), and LED matrix.
Figure 3-6 shows LED Display Circuit.
Figure 3-6 LED Display Circuit
The PROGRAMMABLE KEYBOARD/DISPLAY CONTROLLER (A10-U17) scans keys on the keyboard, and displays LED.
SL0 ~ SL3 continuously feed BINARY CODE. 3-8 LINE DOECODER (A11-U2, U4 HC138) decodes the BINARY CODE, and continuously scans LED MATRIX LEDs. U3 (TD62785) located next to 3-8 LINE DECODER is INVERTED BUFFER, and each LC0 ~ LC11 LINE consecutively turns to "H".
When if "x 10 MAG" LED (A11-CR66) is in "ON", output of U17 OA1 is "H", and LC6 is also "H" at the same time.
KO | K1 | K2 | K3 | K4 | K5 | K6 | K7 | ||
---|---|---|---|---|---|---|---|---|---|
CR01 | CR02 | CR03 | CR04 | CR05 | CR06 | CR07 | CR08 | ||
LC0 | CH1 COUPLING | I | CH2 CO | CH2 COUPLING | |||||
AC | DC | GND | 50Ω | AC | DC | GND | 50Ω | ||
LC1 | CR11 | CR12 | CR13 | CR14 | CR15 | CR16 | CR17 | CR18 | |
СНЗ СО | UPLING | CH4 CO | UPLING | ||||||
AC | DC | GND | +5 | AC | DC | GND | +5 | ||
CR21 | CR22 | CR23 | CR24 | CR25 | CR26 | CR27 | CR28 | ||
LC2 | VERT | MODE | |||||||
102 | CH1 | ADD | CH2 | CH3 | CH4 | ALT | CHOP | 20 MHz | |
ı. | CR31 | CR32 | CR33 | CR34 | CR35 | CR36 | CR37 | CR38 | |
LC3 | TRIC | GER | A TI | RIGGER LE | VEL | B TI | RIGGER LE | VEL | |
А | В | AUTO | + | _ | AUTO | + | - | ||
CR41 | CR42 | CR43 | CR44 | CR45 | CR46 | CR47 | CR48 | ||
LC4 | A TRIGGE | R SOURCE | · | B TRIGGER SOURCE | |||||
CH1 | CH2 | CH3 | CH4 | CH1 | CH2 | CH3 | CH4 | ||
CR51 | CR52 | CR53 | CR54 | CR55 | CR56 | CR57 | CR58 | ||
LC5 | MODE | SOURCE |
A TRIGGER
COUPLING |
TRIGGER SOURCE | |||||
LCS | AUTO | NORM | SINGLE | LINE | ТV-Н | TV-V | V-M (A) | V-M (B) | |
CR61 | CR62 | CR63 | CR64 | CR65 | CR66 | CR67 | |||
LC6 | HOR | IZONTAL M | IODE | HORIZ. | CH2 INTV | ||||
А | ALT | В | B TRIG | X-Y | X10MAG | ||||
CR81 | CR82 | CR83 | CR84 | CR85 | CR86 | CR87 | CR88 | ||
LC8 | 1 | A TRIGGER | COUPLING | . COUPLING | B TRIGGEI | J | |||
AC | LF REJ | HF REJ | DC | AC | LF REJ | HF REJ | DC | ||
CR93 | CR94 | CR95 | |||||||
LC9 | READOUT | ||||||||
Но | A ≠ B | DLY | |||||||
CR101 | CR102 | CR103 | CR104 | CR105 | CR106 | ||||
LC10 | DVM | CURSOR | |||||||
AC | DC | P-P | Δt | 1/ΔV | ΔV | ||||
CR111 | CR112 | CR113 | CR114 | CR115 | CR116 | CR117 | CR118 | ||
LC11 | GP-IB | REFERENC | EMEMORY | STORAGE | |||||
RMT | 4 | 3 | 2 | 1 | ENV | SIN/PULSE | STRG/REAL |
Table 3-6 Shows Panel LED Format above the LED Matrix.
Table 3-6 Panel LED Format
Power Supply Circuit comprises two pairs of multi output switching circuit and series regulator to stabilize the output.
The switching circuit is called ON/OFF convertor.
Figure 3-7 Switching Circuit
When the power is turned ON, unregulated voltage (E) is applied to the convertor circuit.
The base current of Q4 via starting resistor (R9), turns switching transistor (Q5) ON which induce the base winding voltage (VB) that turns the switching transistor (Q5) ON till saturate.
When the base winding voltage (VB) comes high before the transformer magnetic flux saturates, transistors (Q16, Q6) of the voltage regulator circuit turn diode (CR8) ON, which pull the base potential of Q4 to negative potential, and turn transistor (Q5) OFF. Then the energy stored in transformer is sent to the secondary rectifier circuit. And when the energy is fully transferred, the switching transistor (Q5) turn ON.
Output voltage from the secondary rectifier is detected by shunt regulator (U1) in reference to +12, isolated by photo-coupler (PC3), and stabilized by the voltage control circuits.
4. CAR | IBRATI | ON | 4-1 |
---|---|---|---|
4-1 | Genera | ıl | 4-1 |
4-2 | Prepar | ations for Calibration | 4-2 |
4-2-1 | Table of instruments | 4-2 | |
4-2-2 | Removing the case | 4-3 | |
4-2-3 | Board layout | 4-4 | |
4-3 | Perform | nance Check | 4-5 |
4-3-1 | General | 4-5 | |
4-3-2 | CRT System | 4-5 | |
4-3-3 | Vertical Axis system | 4-5 | |
4-3-4 | Trigger System | 4-7 | |
4-3-5 | Horizontal Axis System | 4-8 | |
4-3-6 | Storage System | 4-9 | |
4-3-7 | GP-IB Section | 4-10 | |
4-4 | Calibra | ation | 4-11 |
4-4-1 | Calibration procedure | 4-11 | |
1) | Initial setting | 4-11 | |
2) | Self Calibration | 4-12 | |
3) | Checking for self calibration defects | 4-14 | |
4-4-2 | Checking and adjusting internal power supply voltage | 4-16 | |
1) | Internal power supply voltage | 4-16 | |
2) | V.REF 30mV | 4-18 | |
4-4-3 | Checking and adjusting CRT circuit | 4-19 | |
1) | GEOMETRY | 4-19 | |
2) | ASTIG | 4-20 | |
3) | SUB FOCUS | 4-20 | |
4) | HALATION | 4-20 | |
5) | SUB INTEN | 4-20 | |
6) | X DEFLECTION FACTOR | 4-21 |
7) | X-axis position of characters and gain | 4-22 |
---|---|---|
8) | Y DFLECTION FACTOR | 4-23 |
9) | Y-axis position of characters and gain | 4-24 |
4-4-4 | Vertical circuit | 4-25 |
1) | ADD BALANCE | 4-25 |
2) | CH1 SIGNAL OUT OFFSET | 4-25 |
3) | CH3 POSITION CENTER | 4-26 |
4) | CH4 POSITION CENTER | 4-26 |
5) | CH3 GAIN | 4-27 |
6) | CH4 GAIN | 4-27 |
7) | CH1 and CH2 input attenuator | 4-28 |
8) | CH3 and CH4 input attenuator (ATT) | 4-29 |
9) | Flat characteristics of square waves of CH1 and CH2 | 4-30 |
10) | Flat characteristics of square waves of CH3 and CH4 | 4-31 |
4-4-5 | Checking and adjusting trigger circuit | 4-32 |
1) | TRIG AUTO CENTER | 4-32 |
2) | TRIG DC OFFSET | 4-33 |
4-4-6 | Checking and adjusting horizontal circuit | 4-35 |
1) | Comparator start | 4-35 |
2) | X-Y CENTER | 4-36 |
3) | X-Y GAIN ····· | 4-36 |
4) | SWEEP LENGTH | 4-37 |
5) | Horizontal axis ×10 MAG GAIN | 4-37 |
4-4-7 | Checking and adjusting DVM COMPEN | 4-38 |
4-4-8 | Checking and adjusting storage system | 4-39 |
1) | Mathod of displaying service waveform | 4-39 |
2) | Sweep position | 4-40 |
3) | Sweep gain | 4-40 |
4) | Vertical gain | 4-41 |
5) | Vertical POSITION | 4-41 |
6) | High frequency compensation | 4-41 |
7) | CH1 A/D gain | 4-42 |
8) | CH1 A/D OFFSET ····· | 4-42 |
---|---|---|
9) | CH2 A/D gain | 4-42 |
10) | CH2 A/D OFFSET | 4-42 |
11) | 2µs GAIN BAL ····· | 4-43 |
12) | CH1/CH2 envelope gain | 4-44 |
4-4-9 | Adjustment Table | 4-46 |
Recommended calibration cycle for this oscilloscope is one year under normal operation. Shorter calibratin cycle may be recommended when the ambient condition are not well controlled. Calibration consists of function operation checks and adjustments. First, operation checks of the functions are performed in which the units performance and functions are checked. These checks include a check of the specifications.
If there are items in the performance, functions or standards which cannot be satisfied, they will be readjusted in the adjustment procedure. At this time you should check that the adjustment item has been independently adjusted and that the operation has been completed as well as checking if the adjustment procedure has had an effect on another item (e.g., adjustment of the supply voltage).Fig. 4-1 shows the flow chart of the calibration procedure.
Fig. 4-1 Calibration Procedure Flow Chart
Optimum environmental conditions for the calibration of the unit are a temperature of 23°C±2°C and humidity of 60%±5%. Care should be taken when calibration are made at a location that receives wind from , for instance, the opening and closing of doors since calibration faults may occur in unexpected places.
When making calibration use calibrator which have been correctly calibrated and be careful of the supply voltage that is applied to them.
Perform sufficient warm up time on each piece of equipment used including this unit.
The measuring instruments that are necessary for calibrating this oscilloscope are shown below.
Measurin | g instrument | Perform | ance | Remarks |
---|---|---|---|---|
DC voltme
(lo |
ter (1)
w voltage) |
Measuring range
accuracy |
: 0 to 200V
: Within ±0.1% |
Checking internal power supply voltage |
DC voltme
(hig |
ter (2)
gh voltage) |
Measuring range
accuracy |
: 0 to 3kV
: Within ±1% |
Checking accelerator voltage |
Capacitan | ce meter |
Measuring range
accuracy |
: 0 to 50pF
: Within ±3% |
Checking input capacitance |
Vertical |
Standard
amplitude quare wave generator |
Output voltage
accuracy |
: 1mV to 50Vp-p
: within ±0.3% |
Vertical axis and
X-Y calibration 1kHz |
axis
calibrator |
Fastrise quare |
Output waveform
Frequency |
: Square wave
: 10Hz to 1MHz |
Square wave
Natness adjustment |
generator |
Rise time
Flatness |
: 1.0ns max
: Within ±0.5% |
||
Time marl | c generator |
Mark output
Output stability |
: 5s to 1ns
: Within ±0.1% |
Time axis calibration |
Constant a
signal gen |
umplitude
erator |
Frequency range |
: 250kHz
to 250MHz |
Vertical axis and X-Y
frequency bandwidth |
Frequency accuracy | : Within ±1% | reference | ||
Output voltage
Output flatness |
: 5mV to 5.5Vp-p
: Within ±2% |
|||
Oscilloscope |
Deflection factor
Frequency band Time axis |
: 5mV to 5V/DIV
: DC to 100MHz : 0.5s to 20ns |
||
Connecting cable |
Characteristic
impedance Length |
: 50ohms ;
: Approx 1m |
At least two | |
Terminator |
Characteristic
impedance Power consumption |
: 50ohms ;
: 1/2W min |
Two | |
Attenuator |
Characteristic
impedance Power consumption |
: 50ohms ;
: 1/2W min |
||
Screwdriv | er | 3mm screwdriver | ||
Adjusting | screwdriver | Low capacitance typ | е |
Table 4-1 Instruments necessary for calibration
The main unit can be pulled our from the case by first removing the four (4mm) screws of the rear panel cord winding setion as shown in Fig.4-2.
Fig 4-2 Removing the Case
The printed circuit boards used in this oscilloscope are shown in Table 4-2, and their layout is shown in Fig.4-2.
Name of printed circuit board | Remarks |
---|---|
A1 CH1, CH2ATT | Rear of input connector |
АЗ СНЗ, СН4 АТТ | Rear of input connector |
A4 MAIN BOARD FOR STORAGE | |
A5 V&H FINAL AMP | |
A6 H·V & Z – AXIS AMP | |
A7 CRT CONTROL | Bottom of CRT |
A8 MAIN CPU BOARD | |
A10 FRONT PANEL CONTROL | Behind panel |
A11 FRONT PANEL SWITCH | Behind panel |
A12 STORAGE POWER SUPPLY | |
A13 MOTHER BOARD STORAGE | |
A14 SUB CPU | |
A15 ANALOG PROSESSING | COM 7101A only |
A16 A/D, MEMORY | COM 7101A only |
A17 AQUISITION CONTROL | COM7101A only |
A18 STORAGE DISPLAY | COM7101A only |
A19 GP-IB ADDRESS SWITCH | COM7101A only |
A20 LINE FILTER | |
A21 CRT STOCKET | |
A22 H. V UNIT | Inside of H. V UNIT |
A23 BUS BOARD | |
A24 GP-1B DEVICE CONNECTOR | COM7101A only |
Table 4-2 Printed circuit boards
Fig. 4-3 Layout of printed circuit boards
4-3-1 General
Most of the functions can be checked by performing separate checks of the unit's functions as shown below. For details on the check method see the Instruction Manual and the specification items in this Service Manual.
2) Trigger Level Check
Prepare a personal computer with the GP-IB function (hereafter abbreviated as CPU) and connect it to the unit.
See the Operation Manual for the various commands.
Send the waveform data input/output commands from the CPU and check that the settings are made properly.
This oscilloscope must be calibrated correctly using the same procedure as that used when it is initially calibrated at the factory. The calibration procedure is set out in this manual so that the oscilloscope can be calibrated accurately and in as short a period as possible. Be sure, therefore, to observe this procedure.
The settings of the common items using the controls and switches on the panel of the oscilloscope are shown in Table 4-3. These are the initial settings.
FUNCTION | SETTING | REMARKS | |
---|---|---|---|
Power supply | POWER | ON | |
INTEN | Adequate brightness | ||
CRT Circuit | FOCUS | Set to best focus | |
SCALE | Turn fully left (MIN) | ||
VERT MODE | CH1 only, other channels off | ||
VOLT/DIV | 10mv/DIV | ||
VARIABLE | CAL'D | ||
Vertical circuit | COUPLING | DC (GND is OFF) | |
POSITION (CH1) | Center | ||
BW [20MHz] | OFF | ||
CH2 INV | OFF | ||
MODE | AUTO | ||
SOURCE | V-MODE (CH1) | ||
m_: | COUPLING | AC | |
Trigger circuit | TRIG LEVEL | Center | |
LEVEL AUTO | ON | ||
L | SLOPE | ||
HORIZ MODE | А | ||
Sweep circuit | A/B TIME/DIV | 1ms/DIV | |
VARIABLE | CAL'D | ||
TTtt = inout | POSITION (H) | Set so that trace is at center | |
riorizontai circuit | ×10 MAG | OFF | |
CURSOR SW | но | ||
Readout | READOUT CONT | Turn fully left | (KNOB) |
L | DVMSW | OFF | |
Others | STORAGE MODE | REAL | COM 7101A only |
Table 4-3 Initial setting of common items
Perform self-calibration. The method of starting self-calibration of the COM7101A is slightly different to that of the COM7100A. Table 4-4 shows the method of self-calibrating model.
Model | Method |
---|---|
COM7101A | Press the "DVM" switch while pressing the "(2nd)" function key. |
COM7100A | Press the "INTEN" knob, momentarily release it, then while the CRT screen is in the BEAM FIND status press the "DVM" switch. |
Table 4-4 Method of starting self-calibration
While self-calibration is taking place, "SELF CAL" and also the content of calibration will appear on the CRT screen.
The self calibration period is about 2minutes and 15seconds for the COM7101A, and about 45seconds for the COM7100A.
The contents which are calibrated by the self calibration function are shown below Table 4-5, 4-6.
Section | D | isplay | Content of calibration |
---|---|---|---|
Vertical | STEP BAL | CH1 STEP BALANCE | |
section | VAR B 5 | CH1 VARIABLE BALANCE (5mV/DIV RANGE) | |
1 | GAIN 5 | CH1 GAIN (5mV/DIV RANGE) | |
VERT CH1 | PC C 5 | CH1 POSITION CENTER (5mV / DIV RANGE) | |
VAR B 10 | CH1 VARIABLE BALANCE (10mV/DIV RANGE) | ||
GAIN 10 | CH1 GAIN (10mV/DIV RANGE) | ||
PC C 10 | CH1 POSITION CENTER (10mV/DIV RANGE) | ||
STEP BAL | CH2 STEP BALANCE | ||
VAR B 5 | CH2 VARIABLE BALANCE (5mV/DIV RANGE) | ||
GAIN 5 | CH2 GAIN (5mV / DIV RANGE) | ||
PC C 5 | CH2 POSITION CENTER (5mV / DIV RANGE) | ||
VAR B 10 | CH2 VARIABLE BALANCE (10mV / DIV RANGE) | ||
VERT CH2 | GAIN 10 | CH2 GAIN (10mV/DIV RANGE) | |
PC C 10 | CH2 POSITION CENTER (10mV/DIV RANGE) | ||
PC C 5
CH2 INV |
CH2 POSITION CENTER (10mV/DIV RANGE)
and CH2 INV BALANCE |
||
PC C 10
CH2 INV |
CH2 POSITION CENTER (10mV/DIV RANGE)
and CH2 INV BALANCE |
||
Sweep circuit | START A | A SWEEP POINT | |
START B | B SWEEP POINT | ||
HORIZ | START COMP | DELAY TIME COMPARATOR | |
GAIN A 1m | A SWEEP SPEED (1ms/DIV RANGE) | ||
GAIN A 2m | A SWEEP SPEED (2ms / DIV RANGE) |
Table 4-5 Content of self calibration (1/2)
Section | Di | splay | Content of calibration |
---|---|---|---|
Sweep circuit | GAIN A 5m | A SWEEP SPEED (5ms / DIV RANGE) | |
GAIN A 5m | A SWEEP SPEED (.5ms / DIV RANGE) | ||
GAIN A 10m | A SWEEP SPEED (10ms / DIV RANGE) | ||
GAIN A 50µ | A SWEEP SPEED (50µs / DIV RANGE) | ||
GAIN A 1mN | A SWEEP SPEED (1ms / DIV combination) | ||
GAIN A 1mN | A SWEEP SPEED (.1ms/DIV combination) | ||
HORIZ | GAIN B 1m | B SWEEP SPEED (1ms/DIV RANGE) | |
GAIN B 2m | B SWEEP SPEED (2ms/DIV RANGE) | ||
en Sentra Sentra
Referencia |
GAIN B 5m | B SWEEP SPEED (5ms / DIV RANGE) | |
GAIN B.5m | B SWEEP SPEED (.5ms/DIV RANGE) | ||
GAIN B 10m | B SWEEP SPEED (10ms / DIV RANGE) | ||
GAIN B 50µ | B SWEEP SPEED (50µs / DIV RANGE) | ||
l de la construcción de la constru
La construcción de la construcción d La construcción de la construcción d |
GAIN B 1mN | B SWEEP SPEED (1ms / DIV combination) | |
GAIN B.1mN | B SWEEP SPEED (.1ms/DIV combination) | ||
DVM section |
DC AUTO
ZERO |
OFFSET calibration for DC MODE of DIGITAL VOLTMETER function | |
AC RMS
OFFS |
OFFSET calibration for RMS MODE of DIGITAL VOLTMETER function | ||
DVM |
AC AUTO
ZERO |
OFFSET calibration for AC MODE of DIGITAL VOLTMETER function | |
DYM |
P-P AUTO
ZERO |
OFFSET calibration of P-P DETECTOR | |
GAIN MESUR
(DC) |
DC GAIN calibration of DIGITAL VOLTMETER | ||
GAIN MESUR
(DC) |
DC GAIN calibration of DIGITAL VOLTMETER | ||
Storage | No indicatio | )n | Each function in the storage circuit (COM7201A) only |
Note : The term "combination" pertaining to sweep speed means that this combination is not possible in the normal sweep mode. By performing this "combination" sweep, the sweep speed will be calibrated not only in the medium speed area but also in the low speed and high speed areas as well.
Table 4-6 Content of self calibration (2/2)
After the completion of the calibration, the pannel setting will return to the original seting.
By performing the following operation, the calibration setting values will be displayed on this oscilloscope, enabling the oscilloscope to be checked for possible calibration defects.
Fig. 4-4 Position of SELF CHECK SHORT PIN
NOTE The HEX value is data which is sent from the CPU to the D/A converter. This value is different for each set, hence it is not possible to compare the data between sets and judge whether or not it is satisfactory.
Fig. 4-5
Calibration setting value for vertical section
0 | 0 | 3 | ۲ | 6 | 6 | Ø | 8 | |
---|---|---|---|---|---|---|---|---|
CH1 | STEP BAL | VAR B 5 | GAIN 5 | PC C 5 | VAR B 10 | GAIN 10 | PC C 10 | |
CH2 | STEP BAL | VAR B 5 | GAIN 5 | PC C 5 | VAR B 10 | GAIN 10 | PC C 10 | |
PC C 5
CH2 INV |
PC C 10
CH2 INV |
Calibration setting value for sweep circuit
START A | START B |
START
COMP |
||||||
---|---|---|---|---|---|---|---|---|
А | 1 ms | 2 ms | 5 ms | .5 ms | 10 ms | 50 µs | 1 mN | .1 mN |
В | 1 ms | 2 ms | 5 ms | .5 ms | 10 ms | 50 µs | 1 mN | .1 mN |
Calibration setting value for DVM section
DC AUTO | AC RMS | AC AUTO | P-P AUTO |
---|---|---|---|
ZERO | OFFS | ZERO | ZERO |
GAIN
MESUR DC |
GAIN
MESUR AC |
Table 4-7 Table of calibration setting values
The +12V power supply contained in this oscilloscope constitutes the reference for all other power supply voltages. For this reason, be sure to check the +12V power supply first and foremost. If the +12V power supply voltage is outside the range indicated in Table 4-8, adjust +12V ADJ (RV1) on board A12. After this, simply check the other power supply voltages Do not adjust them. Table 4-8 shows the value of each power supply voltage. The point for checking each voltage and also the adjustment position of +12V ADJ (RV1) are shown in Fig. 4-7 and 4-8
Power supply voltage | Voltage range | Remarks |
---|---|---|
+12V | +11.94V~+12.06V | +12V ADJ (RV1 – A12 PCB) |
-12V | -11.94V~-12.06V | |
+5Va | +4.75V~+5.25V | For analog circuit |
+5Vd | +4.75V~+5.25V | For digital circuit |
5Vd | -4.75V~-5.25V | For digital circuit |
+70V | +69V~+72V | |
+140V | +133V~+147V | |
-2100V | -2050V~2150V |
Table 4-8 Range of each internal power supply voltage
Fig. 4-6 Adjustment position of + 12V ADJ (RV1)
Fig. 4-7 Power supply voltage checking position
Fig. 4-8 Checking position of -2100V
Using a DC digital voltmeter, check the voltage at the R4 on board A4. It is satisfactory, if the potential is between 30.01 mV and 30.09 mV. If it is outside this range, adjust V REF (RV1) on board A4 shown in Fig. 4-9.
Fig. 4-9 Adjustment position of VREF (RV1)
If the voltage in the CRT circuit are adjusted in the same way as described in the previous sub-section "Checking and adjusting internal power supply voltages", the deflection factor will be affected. After adjusting these voltages, therefore, be sure to check the vertical and horizontal deflection factor and the sweep speed.
Check the distortion of the CRT.
Fig. 4-10 Adjustment position of GEOMETARY (RV4)
Set the white dot on "FOCUS" knob to the 12 O'clock position, and confirm whether or not the electron beam is correctly focused. If the electron beam cannot be correctly focused when "FOCUS" knob is set to the 12 O'clock position, adjust SUB FOCUS (RV3) on board A6 shown in Fig. 4-11.
4) HALATION
Confirm that the characters near the periphery of the CRT are not blurred. If they are blurred, adjust HALATION (RV6) on board A6 shown in Fig. 4-11.
Fig. 4-11 Adjustment position of CRT circuit [ASTIG (RV5), SUB FOCUS (RV3) HALLATION (RV6), CRT BIAS (RV2)]
Sweep accuracy for all TIME/DIV setting. It should be within ±2% for all ranges between 0.5s and 10ns.
Fig. 4-12 Adjustment position of HORIZ GAIN ADJ (RV7)
Fig. 4-13 Two vertical cursors
Fig. 4-14 Adjustment positions of CHR X GAIN (RV33) and CHR X POSI (RV32)
Fig. 4-15 Adjustment position of VERT GAIN (RV3)
Fig. 4-16 Two horizontal cursors
Fig. 4-17 Adjustment positions of CHR Y GAIN (RV21) and CHR Y POSI (RV22)
Fig. 4-18 Adjustment position of ADD BAL (RV20), and CH1 SIGNAL OUT (RV18)
Fig. 4-19 Adjustment positions of CH3 and CH4 POSITION CENTER (RV14 and RV15) Adjustment position of CH3 GAIN (RV16) and CH4 GAIN (RV17)
R A N G E | ||||||
---|---|---|---|---|---|---|
1 m V | 10 m V | 0.1 V | 1 V | |||
C H 1 | Phase compensation | RV1 | _ | C5 | C8 | |
Input capacitance | Reference | C4 | C7 | |||
СН2 | Phase compensation | RV1 | _ | C5 | C8 | |
Input capacitance | Reference | C4 | C7 |
Table 4-9 Adjusting CH1 / CH2 input attenuator (ATT)
Fig. 4-21 Adjustment position of input attenuator (ATT)
Confirm that the input capacitance of each range of CH3 shown in Table 4-9 is within ±1pF compared to the input capacitance of the 0.1V range. If it is not, adjust the CH3 input capacitance (C4) on board CH3 / CH4 - ATT shown in Fig. 4-21.
RAN | I G E | ||
---|---|---|---|
0.1V | 0.5V | ||
СНЗ | Phase compensation | None | C5 |
Input capacitance | Refernce | C4 | |
CH4 | Phase compensation | None | C35 |
Input capacitance | Refernce | C34 |
Table 4-10 Adjustment of CH3 / CH4 input attentuator
Fig. 4-22 Adjustment position of HIGH FREQUENCY COMPENSATION on board A4
Fig. 4-23 Adjustment position of HIGH FREQUENCY COMPENSATION on board A5
Fig. 4-24 Adjustment position of TRIG CENTER (1) (RV25) and TRIG CENTER (2) (RV26)
Fig. 4-25 Adjustment positions of CH1 and CH2 TRIG OFFSET (RV6 and RV8)
Fig. 4-26 Adjustment positions of CH3 and CH4 TRIG OFFSET (RV10 and RV12)
Fig. 4-27 Two bright spots (lines)
(5) Confirm that the position between the two bright spots (lines) on the CRT screen is within 8.0±0.1 DIV.
If it is not, adjust COMP START ADJ (RV29) on board A4 shown in Fig. 4-28.
Fig. 4-28 Adjustment position of COMP START ADJ (RV29)
Fig. 4-29 Adjustment positions of X POSITION (RV30), and X-Y GAIN (RV31)
Fig. 4-30 Adjustment positions of A and B SWEEP LENGTH (RV27 and RV28) and x10 MAG GAIN (RV34)
Fig. 4-31 Connection position of oscilloscope (pin 16 of U21)
Fig. 4-32 Adjustment position of DVM COMPEN (RV19)
Before checking the storage system, confirm that the real time system has been checked and adjusted. If it has not, be sure to check and adjust it before adjusting the storage system.
Note: To cancel the service waveform, press "A" of "HORI.MODE".
Fig. 4-33 Self check short pin (A8 MAIN CPU board)
Fig. 4-34 2nd function key and SAVE key
Fig. 4-35 Service waveform
Fig. 4-36 AdjustING sweep gain
Fig. 4-37 Adjustment position of D/A GAIN (RV1), D/A OFFSET (RV2), HIGH FREQUENCY COMPENSATION (RV3), SWEEP GAIN (RV4) and SWEEP START (RV5)
Fig. 4-38 Adjusting vertical position and gain
Fig. 4-39 High frequency portion of square wave
Fig. 4-41 Positions of BRACKET and CONNECTOR (P1053)
(5) Perform initial setting of the instrument in accordance with Table 4-3.
(A)
Fig. 4-42 Storage waveform obtained when adjusting 2µs sweep
When checking the gain continuing on from the previous sub-section, start from step (5).
(10) Set "TIME/DIV" TO CH2 ONLY, and connect the signal output to CH2.
(11) Like CH1, confirm that the waveform on the CRT screen is clean as shown in Fig. 4-43(A).
If the waveform contains noise as shown in Fig. 4-43(B), adjust CH2 BOTTOM GAIN (RV4) and CH2 PEAK GAIN (RV3) on board A15 shown in Fig. 4-44 so that the amplitude of the waveform is 5 DIV±0.1 DIV
(A)
(B)
Fig. 4-43 Waveform when adjusting envelope gain
Fig. 4-44 Adjustment positions of CH1 GAIN ADJ (RV1) and CH2 GAIN ADJ (RV2), CH1 BOTTOM GAIN (RV6), CH1 PEAK GAIN (RV5). CH2 BOTTOM GAIN (RV4) and CH2 PEAK GAIN (RV3)
Item | Adjustment | Adjustment name |
Circuit
No. |
Board |
---|---|---|---|---|
Power | Power supply voltage | +12V ADJ | RV1 | A12 |
Supply | Rreference voltage | V REF 30mV | RV1 | A4 |
CRT | CRT system | GEOMETRY | RV4 | A6 |
Circuit | ASTIG | RV5 | A6 | |
SUB FOCUS | RV3 | A6 | ||
HALATION | RV6 | A6 | ||
CRT BIAS | RV2 | A6 | ||
Charactor gain (X) | CHR X GAIN | RV33 | A4 | |
Charactor position (X) | CHR X POSI | RV32 | A4 | |
Charactor gain (Y) | CHR Y GAIN | RV21 | A4 | |
i | Charactor position (Y) | CHR Y POSI | RV22 | A4 |
Vertical | ADD Balance | ADD BALANCE | RV20 | A4 |
Circuit | CH1 signal out offset | CH1 SIGNAL OUT | RV18 | A4 |
Vertical position center | CH3 POSITION CENTER | RV14 | A4 | |
CH4 POSITION CENTER | RV15 | A5 | ||
Vert final amp gain | VERT GAIN | RV3 | A4 | |
CH3 gain | CH3 GAIN | RV16 | A4 | |
CH4 gain | CH4 GAIN | RV17 | A4 | |
CH1 attenuator | CH1 1/1 ATT COMP | RV1 | A1 (CH1) | |
CH1 1/10 ATT PHASE | C5 | A1 (CH1) | ||
CH1 1/10 ATT CAP | C4 | A1 (CH1) | ||
CH1 1/100 ATT PHASE | C8 | A1 (CH1) | ||
1 | CH1 1/100 ATT CAP | C7 | A1 (CH1) | |
CH2 attenuator | CH2 1/1 ATT COMP | RV1 | A1 (CH2) | |
CH2 1/10 ATT PHASE | C5 | A1 (CH2) | ||
CH2 1/10 ATT CAP | C4 | A1 (CH2) | ||
l | CH2 1/100 ATT PHASE | C8 | A1 (CH2) | |
CH2 1/100 ATT CAP | C7 | A1 (CH2) | ||
CH3 attenuator | CH3 1/10 ATT PHASE | C5 | A3 (CH3) | |
CH3 1/10 ATT CAP | C4 | A3 (CH3) | ||
CH4 attenuator | CH4 1/10 ATT PHASE | C35 | A3 (CH4) | |
CH4 1/10 ATT CAP | C34 | A3 (CH4) | ||
High frequency compensation | HF COMPEN | RV23 | A4 | |
CV9 | A4 | |||
A4 | ||||
HF COMPEN (CH2) | RV9 | A4 | ||
CV6 | A4 | |||
RV4 | A4 | |||
A4
AE |
||||
High frequency compensation | HF COMPEN | CV2 |
AD
AE |
|
DV2 | AD | |||
RVZ
GW2 |
Að | |||
HO
AF |
||||
KV4 |
Að
AF |
|||
CW1 |
AD
AF |
|||
J Að |
Table 4-11 Adjustment Table (1)
Item | Adjustment | Adjustment name |
Circuit
No. |
Board |
---|---|---|---|---|
xx: 1.6 | HF COMPEN (CH1) | RV7 | A4 | |
Vertical | High frequency compensation | CV5 | A4 | |
Circuit | RV2 | A4 | ||
CV1 | A4 | |||
RV3 | A4 | |||
CV2 | A4 | |||
HF COMPEN (CH2) | RV5 | A4 | ||
CV4 | A4 | |||
HF COMPEN (CH3) | RV11 | A4 | ||
CV7 | A4 | |||
HF COMPEN (CH4) | RV13 | A4 | ||
CV8 | A4 | |||
Trigger | Trigger level (AUTO) | TRIG CENTER 3 | RV25 | A4 |
Circuit | TRIG CENTER 3 | RV26 | A4 | |
Ttrigger DC offset | CH1 TRIG OFFSET | RV6 | A4 | |
CH2 TRIG OFFSET | RV8 | A4 | ||
CH3 TRIG OFFSET | RV10 | A4 | ||
CH4 TRIG OFFSET | RV12 | A4 | ||
Horizontal | Horizontal amp gain | HORIZ GAIN ADJ | RV7 | A5 |
Circuit | Comparator start | COMP START ADJ | RV29 | A4 |
X-Y center | X POSITION | RV30 | A4 | |
Horizontal | X-Y gain | X-Y GAIN | RV31 | A4 |
Circuit | Sweep length | A SWEEP LENGTH | RV27 | A4 |
B SWEEP LENGTH | RV28 | A4 | ||
Horizontal amp ×10mag gain | ×10MAG GAIN | RV34 | A4 | |
5ns/DIV, 2ns/DIV sweep time | H-AMP HF COMPEN | RV8 | A5 | |
RV5 | A5 | |||
DVM | DVM compensation | DVM COMPEN | RV19 | A4 |
STORAGE | Storage horizontal positon | SWEEP START | RV5 | A18 |
Storage horizontal gain | SWEEP GAIN | RV4 | A18 | |
Storage vertical gain | D/A GAIN | RV1 | A18 | |
Storage vertical positoin | D/A OFFSET | RV2 | A18 | |
storage HF compensation | HF COMPEN (STR) | RV3 | A18 | |
CH1 A/D gain | CH1 A/D GAIN | RV1 | A16 | |
CH1 A/D offset | CH1 A/D OFFSET | RV2 | A16 | |
CH2 A/D gain | CH2 A/D GAIN | RV3 | A16 | |
CH2 A/D offset | CH2 A/D GAIN | RV4 | A16 | |
A/D gain balance | CH1 A/D GAIN ADJ | RV1 | A15 | |
CH2 A/D GAIN ADJ | RV2 | A15 | ||
CH1 envelope gain | CH1 BOTTOM GAIN | RV6 | A15 | |
CH1 PEAK GAIN | RV4 | A15 | ||
CH2 envelope gain | CH2 BOTTOM GAIN | RV5 | A15 | |
CH2 PEAK GAIN | RV3 | A15 |
Table 4-12 Adjustment Table (2)
5. | MA | INTEN/ | ANCE |
---|---|---|---|
5.1 | Preven | tive Maintenance | |
5.1.1 | Description | ||
5.1.2 | Cleaning | ||
5.1.3 | Visual inspection | ||
5.1.4 | Lubrication | ||
5.1.5 | Semiconductor check | ||
5.2 | Troubl | eshooting | |
5.2.1 | Description | ||
5.2.2 | Power supply, CRT and its related circuit | ||
5.2.3 | Vertical system | ||
5.2.4 | Trigger system | ||
5.2.5 | Time axis system | ||
5.2.6 | Horizontal axis system | ||
5.2.7 | Storage system | ||
5.2.8 | List of board with the parts | ||
5.2.9 | Table of HIC functions |
Preventive maintenance consist of cleaning and visual inspection. By performing such maintenance periodically, unforeseen breakdown can be minimized.
Remove all dirt and dust from inside the unit. Either blow them away using an air compressor or suck them up with a vacuum cleaner. Especially those stuck on the high voltage portions. Also the heat sink should be kept clean.
This unit must not be cleaned with water or cleaning agent. Including case, panel, etc. it is recommended to use a cloth moistened with Diflon to wipe out a part dirt and dust.
Never use benzine, thinner, toluene, for this purpose.
After completion of the cleaning, visually inspect the unit. Pay attention to the connectors, sockets, inner connecting cables, loose screws, and soon.
Since a maintenance-free type fan motor is used, no lubrication is needed.
There is no need to check transistors and other semiconductors of this unit. Periodically as long as the unit operate properly.
If the operation of this unit seems to be abnormal, have a performance check. If the performance check shows abnormal operation, examine which section of the unit (vertical system, horizontal system, or CRT and its related circuit) the malfunction belongs, and thoroughly understand the directions of signal conveying routes with the block diagram.
Also, look at the circuit diagram to find a defective circuit. Parts location on the board, etc. will be a great help at this time. After reaching a defective circuit and find out a defective part, refer to the parts list (electronic) for a capacity or a value. This unit utilizes the special parts to the circuit when it requires. When replacing, be sure to verify a capacity or a value of the defective part, and use the company's specified one or an equivalent one.
In addition, when repairing is performed, follow the calibrating items to adjust the defective portion or to make entire adjustments.
Figure 5-1 Flow Chart of Troubleshooting
Continued to 1.1
5-3
Table 5-1 shows the vertical system troubleshooting chart.
Defective Fun | ctions | Symptom | Defective Circuits | Replacement Parts | ||||
---|---|---|---|---|---|---|---|---|
Board | CKT No. | Code No. | Name of Parts | |||||
Defective & C/DC/GND/500 or 1/1 1/10 1/100 & TT | 1st ATT Unit | A1 | 36-00-1032 | H3 VERTICAL 1st ATT (CH1/CH2) | ||||
ATTENUATOR | CH1/CH2 | RELAY | A1 | 71-07-0370 | RELAY | |||
ATTENOATOR | Defective 1/2, 1/5 ATT. | 2nd ATT Unit | A4 | U3/U4 | 36-00-1052 | H5 VERTICAL 2nd ATT | ||
CH3/CH4 | Defective AC/DC/GND or 1/1, 1/5 ATT. | ATT Unit . | A3 | 36-00-1042 | H4 VERTICAL 1st ATT (CH3/CH4) | |||
VADIARIE | CH1 | Defective VARIABLE DC BAL or VARIABLE not functions. | CH1 1st AMP | A4 | U11 | 36-00-1062 | H6 VERTICAL 1st AMPLIFIER | |
VANIABLE | CH2 | Defective VARIABLE DC BAL or VARIABLE not functions. | CH2 1st AMP | A4 | U12 | 36-00-1062 | H6 VERTICAL 1st AMPLIFIER | |
CH1 | In despite of proper deflection factor, POSITION malfunctions. | CH1 2nd AMP | A4 | U13 | 36-00-1072 | H7 VERTICAL 2nd AMPLIFIER | ||
POSITION | CH2 | In despite of proper deflection factor, POSITION malfunctions. | CH2 2nd AMP | A4 | U14 | 36-00-1072 | H7 VERTICAL 2nd AMPLIFIER | |
control | CH3 | In despite of proper deflection factor, POSITION malfunctions. | CH3 2nd AMP | A4 | U15 | 36-00-1074 | H7 VERTICAL 2nd AMPLIFIER (CH3/CH4) | |
CH4 | In despite of proper deflection factor, POSITION malfunctions. | CH4 2nd AMP | A4 | U15 | 36-00-1082 | H7 VERTICAL 2nd AMPLIFIER (CH3/CH4) | ||
CH1 only | In despite of proper CH1 signal out, DEFLECTION factor is defective. | VERT MODE SWITCH circuit | A4 | U20 | 36-90-1082 | H8 VERT MODE SWITCH | ||
Defective CH1 signal out, also POSITION malfunctions. | CH1 2nd AMP | A4 | U13 | 36-00-1072 | H7 VERTICAL 2nd AMPLIFIER | |||
In despite of defective CH1 signal out, POSITION properly functions | CH1 1st AMP | A4 | U11 | 36-00-1062 | H6 VERTICAL 1st AMPLIFIER | |||
In despite of defective CH2 POSITION, CH2 VARIABLE, trigger is proper by CH2 signal. | VERT MODE SWITCH circuit | A4 | U20 | 36-00-1082 | H8 VERT MODE SWITCH | |||
DEFLECTION | CH2 only | Defective CH2 POSITION, CH2 VARIABLE, also trigger is defective by CH2 signal. | CH2 2nd AMP | A4 | U14 | 36-00-1072 | H7 VERTICAL 2nd AMPLIFIER | |
factor | In despite of defective CH2 VARIABLE, CH2 POSITION is proper. | CH2 1st AMP | A4 | U12 | 36-00-1062 | H6 VERTICAL 1st AMPLIFIER | ||
CH3 only | CH3 POSITION is also defective. | VERT MODE SWITCH circuit | A4 | U20 | 36-00-1082 | H8 VERT MODE SWITCH | ||
CI15 Unity | CH3 POSITION is proper. | CH3 2nd AMP | A4 | U15 | 36-00-1074 | H7 VERTICAL 2nd AMPLIFIER (CH3/CH4) | ||
CH4 only | CH4 POSITION is also defective. | VERT MODE SWITCH circuit | A4 | U20 | 36-00-1082 | H8 VERT MODE SWITCH | ||
- | CH4 POSITION is proper. | CH4 2nd AMP | A4 | U15 | 36-00-1074 | H7 VERTICAL 2nd AMPLIFIER (CH3/CH4) | ||
CH1 thru | CRT graphic display is proper. | VERT MODE SWITCH circuit | A4 | U20 | 36-00-1082 | H8 VERT MODE SWITCH | ||
CH4 all | CPT graphia display is also defactive | DELAY LINE DRIVER or VERT OUT | A4 | U25 | 36-00-1092 | H9 DELAY LINE DRIVER | ||
Defective | Civi graphic display is also delective. | DRIVER circuit | A5 | U2 | 36-00-1102 | H10 VERTICAL FINAL DRIVER |
Table 5-1 Troubleshooting Chart for Vertical System
Table 5-2 shows the trigger system troubleshooting chart.
Defective Functions | Symptom | Defective Circuits | Rej | placement Parts | |||
---|---|---|---|---|---|---|---|
-1 | Board | CKT No. | Code No. | Name of Parts | |||
CH1 only | In case of signal level is lesser when compared with CH2 trigger by observing the scope at A4 board U275-pin (A trigger out). | CH1 2nd AMP | A4 | U13 | 36-00-1072 | H7 VERTICAL 2nd AMPLIFIER | |
CH2 only | In case of signal level is lesser when compared with CH1 trigger by observing the scope at A4 board U275-pin (A trigger out). | CH2 2nd AMP | A4 | U14 | 36-00-1072 | H7 VERTICAL 2nd AMPLIFIER | |
Does not
A TRIGGER |
CH3 only | In case of signal level is lesser when compared with CH4 trigger by observing the scope at A4 board U275-pin (A trigger out). | CH3 2nd AMP | A4 | U15 | 36-00-1074 | H7 VERTICAL 2nd AMPLIFIER |
CH4 only | In case of signal level is lesser when compared with CH3 trigger by observing the scope at A4 board U275-pin (A trigger out). | CH4 2nd AMP | A4 | U16 | 36-00-1074 | H7 VERTICAL 2nd AMPLIFIER | |
Trigger signal is existing at A4 board U48 52-pin (A trig in), and B trigger functions. | SWEEP CONTROLLER | A4 | U48 | 36-00-1252 | H25 SWEEP CONTROLLER | ||
CH4 all
defective |
Trigger signal is existing at A4 board U30 2-pin, but the same level trigger signal not exists at the same IC 21-pin (change trigger level for trial). | A TRIGGER LEVEL COMPARATOR circuit | A4 | U30 | 36-00-1232 | H23 TRIGGER LEVEL COMPARATOR | |
Trigger signal is existing at A4 board U28 2-pin, but the same level trigger signal not exists at the same IC 4-pin (switch trigger coupling for trial). | B TRIGGER COUPLING circuit | A4 | U28 | 36-00-1220 | H22 TRIGGER COUPLING | ||
No trigger signal at A4 board U27 5-pin, but B trigger functions. | A/B TRIGGER SOURCE SWITCH | A4 | U27 | 36-00-1212 | H21 TRIGGER SOURCE SWITCH | ||
CH1 only | In case of signal level is lesser when compared with CH2 trigger by observing the scope at A4 board U27 22-pin (B trigger out). | CH1 2nd AMP | A4 | U13 | 36-00-1072 | H7 VERTICAL 2nd AMPLIFIER | |
CH2 only | In case of signal level is lesser when compared with CH1 trigger by observing the scope at A4 board U27 22-pin (B trigger out). | CH2 2nd AMP | A4 | U14 | 36-00-1072 | H7 VERTICAL 2nd AMPLIFIER | |
CH3 only | In case of signal level is lesser when compared with CH4 trigger by observing the scope at A4 board U27 22-pin (B trigger out). | CH3 2nd AMP | A4 | U15 | 36-00-1074 | H7 VERTICAL 2nd AMPLIFIER | |
Does not B
TRIGGER |
CH4 only | In case of signal level is lesser when compared with CH3 trigger by observing the scope at A4 board U27 22-pin (B trigger out). | CH4 2nd AMP | A4 | U16 | 36-00-1074 | H7 VERTICAL 2nd AMPLIFIER |
Trigger signal is existing at A4 board U48 50-pin (B trig in), and A trigger functions. | SWEEP CONTROLLER | A4 | U48 | 36-00-1252 | H25 SWEEP CONTROLLER | ||
CH1 thro
CH4 all |
Trigger signal is existing at A4 board U31 2-pin, but the same level trigger signal not exists at the same IC 21-pin (change trigger level for trial). | B TRIGGER LEVEL COMPARATOR circuit | A4 | U31 | 36-00-1232 | TRIGGER LEVEL COMPARATOR | |
defective | Trigger signal is existing at A4 board U29 2-pin, but the same level trigger signal not exists at the same IC 4-pin (switch trigger coupling for trial). | B TRIGGER COUPLING circuit | A4 | U29 | 36-00-1220 | TRIGGER COUPLING | |
No trigger signal at A4 board U27 22-pin, but A trigger functions. | TRIGGER SOURCE SWITCH | A4 | U27 | 36-00-1212 | TRIGGER SOURCE SWITCH | ||
In case of no trigger signal are existing both at A4 board U27 5-pin (A trigger out) and 22-pin (B trigger out). | TRIGGER SOURCE SWITCH | A4 | U27 | 36-00-1212 | TRIGGER SOURCE SWITCH | ||
Do not A/B TRIGC | jek | In case of trigger signals are existing both at A4 board U48 52-pin (A trig in) and 50-pin (B trig in). | SWEEP CONTROLLER | A4 | U48 | 36-00-1252 | H25 SWEEP CONTROLLER |
Table 5-2 Troubleshooting Chart for Trigger System
5-7
Table 5-3 shows the time axis system troubleshooting chart.
Г | 1 | 17 | |||||
---|---|---|---|---|---|---|---|
Defective Fur | nction | Symptom | Defective Circuits | ĸ | Replacement Parts | ||
Board | CKT No. | Code No. | Name of Parts | ||||
Sweep waveform is existing at A4 board U48 18-pin or U43 3-pin. Character display on the CRT is proper. | SWEEP & COMPARATOR SWITCH | A4 | U52 | 36-00-1290 | H29 SWEEP & COMPARATOR SWITCH | ||
A SWEEP | All ranges | Trigger signal is existing at A4 board U48 52-pin (A trig in) and X-Y function. | SWEEP CONTROLLER, or SWEEP | A4 | U48 | 36-00-1252 | H25 SWEEP CONTROLLER |
NO SWEEP | No sweep waveform exists at A4 board U48 18-pin or U43 3-pin. | GENERATOR | A4 | U43 | 36-00-1270 | H27 SWEEP GENERATOR | |
Some of the ranges |
Phenomenon on the CRT and the generated sweep waveform at A4 board U48
18-pin or U43 3-pin coincide. |
SWEEP GENERATOR | A4 | U43 | 36-00-1270 | H27 SWEEP GENERATOR | |
A SWEEP TIME or | at of spec. | Character display on the CRT is proper. | SWEEP GENERATOR | A4 | U43 | 36-00-1270 | H27 SWEEP GENERATOR |
Sweep waveform is existing at A4 board U48 6-pin or U44 3-pin. Character display on the CRT is proper. | SWEEP & COMPARATOR SWITCH | A4 | U52 | 36-00-1290 | H29 SWEEP & COMPARATOR SWITCH | ||
A sweep is normal. No sweep waveform exists at A4 board U52 20-pin. | SWEEP & COMPARATOR SWITCH | A4 | U52 | 36-00-1290 | H29 SWEEP & COMPARATOR SWITCH | ||
B SWEEP
NO SWEEP |
A sweep is normal. Sweep waveform is existing at A4 board U52 20-pin, but no signal exists at the same IC 11-pin or 12-pin. | DELAY TIME COMPARATOR | U56 | 36-00-1281 | H28 DELAY TIME COMPARATOR | ||
THI THIS | A sweep is normal. Signal is delivered to A4 board U48 28, 29-pin (DLY TRIG IN) from Comparator. No sweep waveform exists at A4 board U48 6-pin or U44 3-pin. |
SWEEP CONTROLLER or SWEEP
GENERATOR |
A4 | U48 | 36-00-1252 | H25 SWEEP CONTROLLER | |
Some of the ranges | Phenomenon on the CRT and the generated sweep waveform at A4 board U48 6-pin or U44 3-pin coincide. | SWEEP GENERATOR | A4 | U44 | 36-00-1270 | H27 SWEEP GENERATOR | |
B SWEEP TIME ou | it of spec. | Character display on the CRT is proper. | SWEEP GENERATOR | A4 | U44 | 36-00-1270 | H27 SWEEP GENERATOR |
Table 5-3 Troubleshooting Chart for Time Axis System
Table 5-4 shows the horizontal axis system troubleshooting
Defective Function | Symptom | Defective Circuits | Replacement Parts | ||||
---|---|---|---|---|---|---|---|
Board | CKT No. | Code No. | Name of Parts | ||||
X-Y function, character display on the CRT, and horizontal position are normal. | U52 SWEEP COMPARATOR SWITCH | A4 | U52 | 36-00-1290 | H29 SWEEP & COMPARATOR SWITCH | ||
SWEEP NO SWEEP | Horizontal position is abnormal, X-Y function and character display on the CRT are normal. | U55 HORIZONTAL SWITCHING & DRIVER | A4 | U55 | 36-00-1302 | H30 HORIZONTAL SWITCHING & DRIVER | |
X-Y function, character display on the CRT, and horizontal position are abnormal. | HORIZONTAL FINAL AMP | A5 | U3 | 36-00-1312 | H31 HORIZONTAL FINAL AMPLIFIER | ||
Abnormal HORIZONTAL
POSITION |
Sweep, X-Y function, and character display on the CRT are normal. | ANALOG MPX | A4 | U66 | 36-00-1140 | H14 ANALOG MULTIPLEXER | |
Abnormal ×10 MAG | In despite of A4 board U55 16-pin in "L", x10 MAG is abnormal. |
U55 HORIZONTAL SWITCHING &
DRIVER |
A4 | U55 | 36-00-1302 | H30 HORIZONTAL SWITCHING & DRIVER |
Table 5-4 Troubleshooting Chart for Horizontal Axis System
Table 5-5 shows the storage system troubleshooting chart.
Real time operation is in normal as a general rule.
Det | Defective Function | Symptom | Defective Circuits | Re | placement Part | |||
---|---|---|---|---|---|---|---|---|
~, | Board | CKT No. | Code No. | Name of Parts | ||||
CH1 only | No input signal at A4 board U26 6/5-pin and 10/9-pin. Input signal exists when | VERT MODE SWITCH, or STORAGE | A4 | U20 | 36-00-1082 | H8 VERT MODE SWITCH | ||
CIII OIIIy | the unit's vert mode is in CH2. | SIGNAL BUFFER. | A4 | U26 | 36-00-1110 | H11 STORAGE SIGNAL BUFFER | ||
CH2 only | No input signal at A4 board U26 6/5-pin and 10/9-pin. Input signal exists when | VERT MODE SWITCH, or STORAGE | A4 | U20 | 36-00-1082 | H8 VERT MODE SWITCH | ||
the unit's vert mode is in CH1. | SIGNAL BUFFER. | A4 | U26 | 36-00-1110 | H11 STORAGE SIGNAL BUFFER | |||
Sweep | Input signal is existing at A4 board U26 6/5-pin and 10/9-pin, but no input signal exists at A15 board H12 17/16-pin and 24/23-pin. | STORAGE SIGNAL DRIVER. | A15 | U5 | 36-00-1120 | H12 STORAGE SIGNAL DRIVER | ||
STOR-
AGE |
functions
(previous stage to A/D con- verter) |
Input signal is existing at A15 board H12 17/16-pin and 24/23-pin, but no input signal exists at A16 board U12A 23-pin. | A15 CHANNEL DIVIDER. | A15 | U6 | 36-00-1130 | H13 STORAGE CHANNEL DIVIDER | |
no-
storage |
o
on- All CH2 |
Input signal is existing at A16 board U12A 23-pin, but no signal exists at A16 board U12A 3-pin (SAMPLING OUT). (Compare with U12C 3-pin.) | A16 SAMPLE AND HOLD. | A16 | U12A | 36-00-1180 | H18 SAMPLE and HOLD | |
Input signal is existing at A16 board U12C 23-pin, but no signal exists at A16 board U12C 3-pin (SAMPLING OUT). (Compare with U12A 3-pin.) | A16 SAMPLE AND HOLD. | A16 | U12C | 36-00-1180 | H18 SAMPLE and HOLD | |||
"Sample and hold" input signal is existing at A16 board U11A 21-pin, but storage not functions. | A16 A/D CONVERTER. | A16 | UIIA | 34-21-0000 | A/D CONVERTER | |||
"Sample and hold" input signal is existing at A16 board U11C 21-pin, but storage not functions. | A16 A/D CONVERTER. | A16 | U11C | 34-21-0000 | A/D CONVERTER | |||
(Sub-
sequent stage to D/A con- verter) |
All CHs | Character display is normal on the CRT. Reemerged input waveform is observed at A18 board U1B 10-pin. | A4 U20 VERT MODE SWITCH. | A4 | U20 | 36-00-1082 | H8 VERT MODE SWITCH | |
Character display is normal on the CRT. D/A converted output signal is existing at A18 board U1B 5-pin (D/A SIGNAL IN), but no signal exists at the same IC 10-pin (OUT). | A18 U1B INTERPOLATOR. | A18 | U1B | 36-00-1200 | H20 INTERPOLATOR | |||
Ċ | Character display is normal on the CRT. Sweep signal (STORAGE) is observed at A18 board U1C 10-pin. |
A4 U52 SWEEP COMPARATOR
SWITCH. |
A4 | U52 | 36-00-1290 | H29 SWEEP & COMPARATOR SWITCH | ||
not func-
tions |
All CHs | Character display is normal on the CRT. Sweep signal (STORAGE) is observed at A18 board U1C 4-pin, but not at A18 board U1C 10-pin. | A18 UIC STORAGE DEGLITCHER. | A18 | UIC | 36-00-1320 | H32 STORAGE DEGLITCHER | |
Character display is normal on the CRT. No sweep signal is observed at A18 board U2C 18-pin. | A18 U2C D/A CONVERTER (12-Bit). | A18 | U2C | 36-20-0100 | D/A CONVERTER 12 Bit | |||
ENVELO | OPE does |
CH1/CH3
only |
PEAK or BOTTOM LEVEL moves out of the CRT screen when shift to EN-
VELOPE MODE. |
A15 U8 ENVELOPE PEAK HOLD. | A15 | U8 | 36-00-1160 | H16 STORAGE ENVELOPE PEAK HOLD |
not func | tion |
CH2/CH4
only |
PEAK or BOTTOM LEVEL moves out of the CRT screen when shift to EN VELOPE MODE. | A15 U7 ENVELOPE PEAK HOLD. | A15 | U7 | 36-00-1160 | H16 STORAGE ENVELOPE PEAK HOLD |
Abnorma | al REPEAT f | unction | Storage function (sweep time 50ms ~ 0.5 µs DIV) is normal in other than REPEAT MODE, but no waveform can be observed in REPEAT MODE. | A17 U3B JITTER INTERVAL METER. | A17 | U3B | 36-00-1330 | H33 JITTER INTERVAL METER |
Abnorm | al dot joint | Connecting function for each dot linking on the CRT screen waveform is defective that the CRT screen shows a staircase-like waveform. Or no waveform is displayed. (OVER SCALE.) | A18 U1B INTERPOLATOR. | A18 | U1B | 36-00-1200 | H20 INTERPOLATOR | |
Noise on
direction |
the horizon | tal | Apply an approx. 6 DIV 1 kHz sine wave, and when displaying 1 cycle on the CRT screen, a horizontal noise is observed. |
A18 U1C STORAGE SWEEP
DEGLITCHER. |
A18 | U1C | 36-00-1320 | H32 STORAGE SWEEP DEGLITCHER |
Table 5-5 Troubleshooting Chart for Storage System
Table 5-6 and 5-7 show the list of board with the parts employed in this unit.
1) COM7101A
Assembly
No. |
KIKUSUI
Parts No. |
Name of Board | |
---|---|---|---|
A1 | 36-00-1030 | H3 CH1, CH2 1st ATTENUATOR | |
A3 | 36-00-1040 | H4 CH3, CH4 1st ATTENUATOR | |
A4 | 97-11-0230 | A4 COM7101A MAIN BOARD FOR STORAGE | · |
A5 | 97-11-0032 | A5 COM71xxA VERTICAL & HORIZONTAL FINAL AMPL | IFIER |
A6 | 97-11-0040 | A6 COM71xxA HIGH VOLTAGE & Z-AXIS AMPLIFIER | *1 |
A7 | 97-11-0050 | A7 COM7xxxA CRT CONTROL | |
A8 | 97-11-0060 | A8 COM7xxxA MAIN CPU BOARD | *2 |
A10 | 97-11-0070 | A10 COM7xxxA FRONT PANEL CONTROL | |
A11 | 97-11-0261 | A11 COM7101A FRONT PANEL SWITCH | |
A12 | 97-11-0280 | A12 COM7101A STORAGE POWER SUPPLY | |
A13 | 97-11-0250 | A13 COM7101A MOTHER BOARD STORAGE | |
A14 | 97-11-0121 | A14 COM7101A SUB CPU BANK VERSION | |
A15 | 97-11-0170 | A15 COM7101A ANALOG PROCESSING | |
A16 | 97-11-0150 | A16 COM7101A A/D MEMORY | |
A17 | 97-11-0140 | A17 COM7101A ACQUISITION CONTROL | |
A18 | 97-11-0130 | A18 COM7101A STORAGE DISPLAY | |
A22 | 97-11-0200 | A22 COM71xxA H.V. UNIT | *1 |
Note: *1. A22 (H.V. UNIT) is not included in A6 (HIGH VOLTAGE & Z-AXIS AMPLIFIER).
*2. Because of PROGRAM ROM is built-in, specify the name of model when placing an order.
Table 5-6 List of Board with the Parts for COM7101A
2) COM7100A
Assembly
No. |
KIKUSUI
Parts No. |
Name of Board | |
---|---|---|---|
A1 | 36-00-1030 | H3 CH1, CH2 1st ATTENUATOR | |
A3 | 36-00-1040 | H4 CH3, CH4 1st ATTENUATOR | |
A4 | 97-11-0021 | A4 COM7100A MAIN BOARD | |
A5 | 97-11-0030 | A5 COM71xxA VERTICAL & HORIZONTAL FINAL AMPI | IFIER |
A6 | 97-11-0040 | A6 COM71xxA HIGH VOLTAGE & Z-AXIS AMPLIFIER | *1 |
A7 | 97-11-0050 | A7 COM7xxxA CRT CONTROL | |
A8 | 97-11-0060 | A8 COM7xxxA MAIN CPU BOARD | *2 |
A10 | 97-11-0070 | A10 COM7xxxA FRONT PANEL CONTROL | |
A11 | 97-11-0081 | A11 COM7100A FRONT PANEL SWITCH | |
A12 | 97-11-0090 | A12 COM7100A POWER SUPPLY | |
A13 | 97-11-0100 | A13 COM7100A MOTHER BOARD | |
A22 | 97-11-0200 | A22 COM71xxA H.V. UNIT | *1 |
Note: *1. A22 (H.V. UNIT) is not included in A6 (HIGH VOLTAGE & Z-AXIS AMPLIFIER).
*2. Because of PROGRAM ROM is built-in, specify the name of model when placing an order.
Table 5-7 List of Board with the Parts for COM7100A
Functions of HIC'utilized in this unit are as follows:
HIC for other than board assembly
CKT NO. | HIC NAME |
KIKUSUI'S
PARTS NO. |
FUNCTION | DESCRIPTIONS |
---|---|---|---|---|
H3 | 36-00-1030 | VERTICAL 1st ATT (CH1) | Coupling of CH1 signal (AC, DC, GND), and attenuation (1/1, 1/10, 1/100). | |
H3 | 36-00-1030 | VERTICAL 1st ATT (CH2) | Coupling of CH2 signal (AC, DC, GND), and attenuation (1/1, 1/10, 1/100). | |
H4 | 36-00-1040 | VERTICAL 1st ATT (CH3/CH4) | Coupling of CH3 and CH4 (AC, DC, GND), and attenuation (1/1, 1/5). |
CKT NO. | HIC NAME |
KIKUSUI'S
PARTS NO. |
FUNCTION | DESCRIPTIONS |
---|---|---|---|---|
U3 | H5 | 36-00-1050 | VERTICAL 2nd ATT | CH1 signal (1/1, 1/2, 1/5). |
U4 | H5 | 36-00-1050 | VERTICAL 2nd ATT | CH2 signal (1/1, 1/2, 1/5). |
U11 | H6 | 36-00-1060 | VERTICAL 1st AMPLIFIER | CH1 AMPLITUDE AND VARIABLE GAIN CONTROL. |
U12 | H6 | 36-00-1060 | VERTICAL 1st AMPLIFIER | CH2 AMPLITUDE AND VARIABLE GAIN CONTROL. |
U13 | H7 | 36-00-1070 | VERTICAL 2nd AMPLIFIER | CH1 AMPLITUDE AND POSITION CONTROL. |
U14 | H7 | 36-00-1070 | VERTICAL 2nd AMPLIFIER | CH2 AMPLITUDE AND POSITION CONTROL. |
U15 | H7 | 36-00-1073 | VERTICAL 2nd AMPLIFIER (CH3/CH4) | CH3 AMPLITUDE AND POSITION CONTROL. |
U16 | H7 | 36-00-1073 | VERTICAL 2nd AMPLIFIER (CH3/CH4) | CH4 AMPLITUDE AND POSITION CONTROL. |
U17 | H14 | 36-00-1140 | ANALOG MULTIPLEXER | Hold data (CH1, GAIN, CH1 POSITION, CH1 POSITION CENTER, CH1 VARIABLE, CH1 INPUT OFFSET, CH1 STEP BALANCE, DVM AUTO ZERO, DVM RMS OFFSET). |
U18 | H14 | 36-00-1140 | ANALOG MULTIPLEXER | Hold data (CH2 GAIN, CH2 POSITION, CH2 POSITION CENTER, CH2 VARIABLE, CH2 INPUT OFFSET, CH2 STEP BALANCE, CH3 POSITION, CH4 POSITION). |
U19 | H19 | 36-00-1190 | CH1 SIGNAL OUTPUT AMPLIFIER | CH1 SIGNAL OUTPUT. |
U20 | H8 | 36-00-1080 | VERTICAL MODE SWITCH | Switching of each vertical axis signal (CH1, CH2, CH3, CH4), and output (REAL SIGNAL, FOR X-Y SIGNAL (X AXIS), CHA & CHB SIGNAL (FOR STORAGE). |
U21 | H42 | 36-00-1420 | DVM TRUE RMS CONVERTER | True RMS conversion of vertical axis CH1 2nd ATT OUT, and output of each DVM function mode (DC, RMS, P-P, V-MONI). |
U22 | H43 | 36-00-1430 | DVM PEAK DETECTOR | Peak detector of H42 (DVM true RMS converter) To P-P signal, and re-outputs to H42 FROM P-P input. |
U25 | H9 | 36-00-1090 | DELAY LINE DRIVER | Delay line driver (VERTICAL REALTIME SIGNAL & VERTICAL CHARACTER SIGNAL). |
U26 | H11 | 36-00-1110 | STORAGE SIGNAL BUFFER | Buffering H8 (vertical mode switch) CHA and CHB signals, and outputs to A15 (Analog processing board). Band width limiter for storage is built-in. |
U27 | H21 | 36-00-1210 | TRIGGER SOURCE SWITCH | Switching of each vertical axis trigger signal (CH1, CH2, CH3, CH4), and A/B 2-SYSTEM trigger output of line trigger signal. |
U28 | H22 | 36-00-1220 | TRIGGER COUPLING SWITCH | A trigger signal coupling (AC, LF REJ, HF REJ, DC, TV-V, TV-H). |
U29 | H22 | 36-00-1220 | TRIGGER COUPLING SWITCH | B trigger signal coupling (AC, LF REJ, HF REJ, DC, TV-V, TV-H). |
U30 | H23 | 36-00-1230 | TRIGGER LEVEL COMPARATOR | A trigger comparator and slope control. |
U31 | H23 | 36-00-1230 | TRIGGER LEVEL COMPARATOR | B trigger comparator and slope control. |
U32 | H24 | 36-00-1240 | TV SYNCHRONIZE SEPARATOR | TV sync. separator circuit to detect TV synchro signal from A trigger signal. |
U43 | H27 | 36-00-1270 | SWEEP GENERATOR | A sweep generator. |
U44 | H27 | 36-00-1270 | SWEEP GENERATOR | B sweep generator. |
U48 | H25 | 36-00-1250 | SWEEP CONTROLLER | Overall controlling of A/B sweep circuit. |
U52 | H29 | 36-00-1290 | SWEEP & COMPARATOR SWITCH | Switching circuit of A/B sweep signals. |
U55 | H30 | 36-00-1302 | HORIZONTAL SWITCHING & DRIVER | Selecting and amplifying of horizontal axis signal (A/B sweep signals, X-Y signals, horizontal character signal), horizontal position, beam find, x10 magnifier, etc. |
U56 | H28 | 36-00-1280 | DELAY TIME COMPARATOR | Delay sweep comparator circuit, making B sweep gate signal from A sweep signal. |
U57 | H34 | 36-00-1340 | Z AXIS SWITCH & Z AXIS DRIVER | Switching circuit of each Z axis signal (A/B sweep gate, character intergate, storage intergate, ext Z in, etc.), and output buffer circuit. |
U58 | H26 | 36-00-1260 | PRESCALER | For frequency counter (switches to 1/1, 1/10, 1/100 according to the input frequency). |
CKT NO. | HIC NAME |
KIKUSUI'S
PARTS NO. |
FUNCTION | DESCRIPTION |
---|---|---|---|---|
U59 | H41 | 36-00-1410 | SEQUENCE CONTROLLER | Vertical mode and display mode on the panel. |
U65 | H14 | 36-00-1140 | ANALOG MULTIPLEXER | Hold data ((A/B TRIG LEVEL, SWEEP HOLDOFF, A/B SWEEP VARIABLE, A SWEEP POSITION, B SWEEP POSITION, COMPARATOR LEVEL) |
U66 | H14 | 36-00-1140 | ANALOG MULTIPLEXER | Hold data (CURSOR 1/2 LEVEL, B SWEEP INTEN, CHARACTER INTEN, HORIZONTAL POSITION, SCALE ILLUMINATION, TRACE SEPARATION). |
CKT NO. | HIC NAME |
KIKUSUI'S
PARTS NO. |
FUNCTION | DESCRIPTION |
---|---|---|---|---|
U2 | H10 | 36-00-1100 | VERTICAL FINAL DRIVER | Amplifying vertical signal, and drive final stage transistor. |
U3 | H31 | 36-00-1310 | HORIZONTAL FINAL AMPLIFIER | Amplifying horizontal signal, and final stage. |
CKT NO. | HIC NAME |
KIKUSUI'S
PARTS NO. |
FUNCTION | DESCRIPTION |
---|---|---|---|---|
U601 | H31 | 36-00-1310 | HORIZONTAL FINAL AMPLIFIER | Amplifying Z axis signal, and final stage of Z axis. |
CKT NO. | HIC NAME |
KIKUSUI'S
PARTS NO. |
FUNCTION | DESCRIPTION |
---|---|---|---|---|
U5 | H12 | 36-00-1120 | STORAGE SIGNAL DRIVER | Impedance conversion circuit for H13 & H16. |
U6 | H13 | 36-00-1130 | STORAGE CHANNEL DRIVER | Switching circuit obtains 2 pairs of balanced in and output and enable to set output according to dual mode/single mode, ALT chop, and sampling speed (Sweep speed of storage mode). |
U7 | H16 | 36-00-1160 | STORAGE ENVELOPE PEAK HOLD | Peak and bottom hold circuit for CHA (CH1 or CH3) (obtains 2 sets of peak hold circuit, performs reversing and non-reversing of differential). |
U8 | H16 | 36-00-1160 | STORAGE ENVELOPE PEAK HOLD | Peak and bottom hold circuit for CHB (CH2 or CH4) (obtains 2 sets of peak hold circuit, performs reversing and non-reversing of differential). |
CKT NO. | HIC NAME |
KIKUSUI'S
PARTS NO. |
FUNCTION | . DESCRIPTION |
---|---|---|---|---|
U12A | H18 | 36-00-1180 | SAMPLE & HOLD | Sample and hold circuit for CHA (CH1 or CH3) with reference voltage for A/D converter. |
U12C | H18 | 36-00-1180 | SAMPLE & HOLD | Sample and hold circuit for CHB (CH2 or CH4) with reference voltage for A/D converter. |
CKT NO. | HIC NAME |
KIKUSUI'S
PARTS NO. |
FUNCTION | DESCRIPTION |
---|---|---|---|---|
U1B | H15 | 36-00-1150 | ANALOG MULTIPLEXER DIP | Hold data (JITCAL, HOLDOFF RANDOMIZED, CHA BAL, CHB BAL, CHA PEAK OFFSET, CHA BOTTOM OFFSET, CHB PEAK OFFSET, CHB BOTTOM OFFSET) |
U14C | H36 | 36-00-1360 | CLOCK GENERATOR | Obtains 50MHz and 40MHz crystal oscillator and OR circuit, delivers one of which signal according to sampling speed. |
U3B | H33 | 36-00-1330 | JITTER INTERVAL METER | Expanding circuit of time from trigger signal to random sample signal by double integrally. |
СКТ NO | . HIC NAME |
KIKUSUI'S
PARTS NO. |
FUNCTION | DESCRIPTION |
---|---|---|---|---|
U1B | H20 | 36-00-1200 | INTERPOLATOR | Dot joinner to connect staircase-like vertical axis converter output signal in straight line at storage mode. |
UIC | H32 | 36-00-1320 | STORAGE SWEEP DEGLITCHER | Removing circuit to remove glitch noise with horizontal axis converter output integrally at storage mode. |
5. | CIR | CUIT DIAGRAM | ||||
---|---|---|---|---|---|---|
6.1 | Descrip | ption | ||||
6.1.1 | List of circuit diagrams | |||||
6.1.2 | Notes for circuit diagram | |||||
6.2 | Circuit | Diagram | ||||
6.3 | Parts L | ocation |